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platform: generic: andes/renesas: Add SBI EXT to check for enabling IOCP errata

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I/O Coherence Port (IOCP) provides an AXI interface for connecting
external non-caching masters, such as DMA controllers. The accesses
from IOCP are coherent with D-Caches and L2 Cache.

IOCP is a specification option and is disabled on the Renesas RZ/Five
SoC (which is based on Andes AX45MP core) due to this reason IP blocks
using DMA will fail.

As a workaround for SoCs with IOCP disabled CMO needs to be handled by
software. Firstly OpenSBI configures the memory region as
"Memory, Non-cacheable, Bufferable" and passes this region as a global
shared dma pool as a DT node. With DMA_GLOBAL_POOL enabled all DMA
allocations happen from this region and synchronization callbacks are
implemented to synchronize when doing DMA transactions.

SBI_EXT_ANDES_IOCP_SW_WORKAROUND checks if the IOCP errata should be
applied to handle cache management.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
This commit is contained in:
Lad Prabhakar
2023-04-11 17:36:33 +01:00
committed by Anup Patel
parent bf40e07f6f
commit eeab500a65
7 changed files with 95 additions and 2 deletions
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23
platform/generic/include/andes/andes45.h
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@@ -4,7 +4,26 @@
#define CSR_MARCHID_MICROID 0xfff
/* Memory and Miscellaneous Registers */
#define CSR_MCACHE_CTL 0x7ca
#define CSR_MCCTLCOMMAND 0x7cc
#define CSR_MCACHE_CTL 0x7ca
#define CSR_MCCTLCOMMAND 0x7cc
/* Configuration Control & Status Registers */
#define CSR_MICM_CFG 0xfc0
#define CSR_MDCM_CFG 0xfc1
#define CSR_MMSC_CFG 0xfc2
#define MICM_CFG_ISZ_OFFSET 6
#define MICM_CFG_ISZ_MASK (0x7 << MICM_CFG_ISZ_OFFSET)
#define MDCM_CFG_DSZ_OFFSET 6
#define MDCM_CFG_DSZ_MASK (0x7 << MDCM_CFG_DSZ_OFFSET)
#define MMSC_CFG_CCTLCSR_OFFSET 16
#define MMSC_CFG_CCTLCSR_MASK (0x1 << MMSC_CFG_CCTLCSR_OFFSET)
#define MMSC_IOCP_OFFSET 47
#define MMSC_IOCP_MASK (0x1ULL << MMSC_IOCP_OFFSET)
#define MCACHE_CTL_CCTL_SUEN_OFFSET 8
#define MCACHE_CTL_CCTL_SUEN_MASK (0x1 << MCACHE_CTL_CCTL_SUEN_OFFSET)
#endif /* _RISCV_ANDES45_H */

15
platform/generic/include/andes/andes_sbi.h Normal file
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@@ -0,0 +1,15 @@
// SPDX-License-Identifier: BSD-2-Clause
#ifndef _RISCV_ANDES_SBI_H
#define _RISCV_ANDES_SBI_H
#include <sbi/sbi_trap.h>
#include <sbi_utils/fdt/fdt_helper.h>
int andes_sbi_vendor_ext_provider(long funcid,
const struct sbi_trap_regs *regs,
unsigned long *out_value,
struct sbi_trap_info *out_trap,
const struct fdt_match *match);
#endif /* _RISCV_ANDES_SBI_H */