forked from Mirrors/opensbi
eeab500a65
I/O Coherence Port (IOCP) provides an AXI interface for connecting external non-caching masters, such as DMA controllers. The accesses from IOCP are coherent with D-Caches and L2 Cache. IOCP is a specification option and is disabled on the Renesas RZ/Five SoC (which is based on Andes AX45MP core) due to this reason IP blocks using DMA will fail. As a workaround for SoCs with IOCP disabled CMO needs to be handled by software. Firstly OpenSBI configures the memory region as "Memory, Non-cacheable, Bufferable" and passes this region as a global shared dma pool as a DT node. With DMA_GLOBAL_POOL enabled all DMA allocations happen from this region and synchronization callbacks are implemented to synchronize when doing DMA transactions. SBI_EXT_ANDES_IOCP_SW_WORKAROUND checks if the IOCP errata should be applied to handle cache management. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
30 lines
824 B
C
30 lines
824 B
C
#ifndef _RISCV_ANDES45_H
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#define _RISCV_ANDES45_H
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#define CSR_MARCHID_MICROID 0xfff
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/* Memory and Miscellaneous Registers */
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#define CSR_MCACHE_CTL 0x7ca
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#define CSR_MCCTLCOMMAND 0x7cc
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/* Configuration Control & Status Registers */
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#define CSR_MICM_CFG 0xfc0
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#define CSR_MDCM_CFG 0xfc1
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#define CSR_MMSC_CFG 0xfc2
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#define MICM_CFG_ISZ_OFFSET 6
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#define MICM_CFG_ISZ_MASK (0x7 << MICM_CFG_ISZ_OFFSET)
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#define MDCM_CFG_DSZ_OFFSET 6
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#define MDCM_CFG_DSZ_MASK (0x7 << MDCM_CFG_DSZ_OFFSET)
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#define MMSC_CFG_CCTLCSR_OFFSET 16
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#define MMSC_CFG_CCTLCSR_MASK (0x1 << MMSC_CFG_CCTLCSR_OFFSET)
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#define MMSC_IOCP_OFFSET 47
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#define MMSC_IOCP_MASK (0x1ULL << MMSC_IOCP_OFFSET)
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#define MCACHE_CTL_CCTL_SUEN_OFFSET 8
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#define MCACHE_CTL_CCTL_SUEN_MASK (0x1 << MCACHE_CTL_CCTL_SUEN_OFFSET)
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#endif /* _RISCV_ANDES45_H */
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