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firmware: Fix compile error for FW_PAYLOAD with latest GCC binutils

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We get following compile error for FW_PAYLOAD with latest GCC
binutils:
fw_payload.o(.text+0x1961): 15 bytes required for alignment to 16-byte
boundary, but only 14 present

Further investigating, it turn-out to be a known issue with RISC-V
GCC binutils.
(Refer, https://github.com/riscv/riscv-gnu-toolchain/issues/298)

As a work-around, we disable relaxation when including DTB and
PAYLOAD binary in fw_payload.S.

Reported-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Tested-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
This commit is contained in:
Anup Patel
2019-10-23 12:44:14 +05:30
committed by Anup Patel
parent be92da280d
commit dd8ef28b27
1 changed files with 10 additions and 0 deletions
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10
firmware/fw_payload.S
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@@ -85,6 +85,14 @@ fw_options:
add a0, zero, zero
ret
/*
* We disable relaxation because use of ".align"
* and ".balign" can potentially generate compile
* errors with latest RISC-V GCC Binutils.
*/
.option push
.option norelax
#ifdef FW_PAYLOAD_FDT_PATH
.align 4
.section .text, "ax", %progbits
@@ -103,3 +111,5 @@ payload_bin:
#else
.incbin FW_PAYLOAD_PATH
#endif
.option pop