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lib: sbi_trap: Add support for vectored interrupts

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When redirecting an exception to S-mode, transform the (v)stvec CSR
value as described in the privileged spec to derive the S-mode PC.
Since OpenSBI never redirects interrupts, only synchronous exceptions,
the only action needed is to mask out the (v)stvec.MODE field.

Reported-by: Jan Reinhard <jan.reinhard@sysgo.com>
Closes: https://github.com/riscv-software-src/opensbi/issues/391
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Reviwed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20250305014729.3143535-1-samuel.holland@sifive.com
Signed-off-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Samuel Holland
2025-03-04 17:45:43 -08:00
committed by Anup Patel
parent 995f226f3f
commit afa0e3091b
2 changed files with 4 additions and 2 deletions
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2
include/sbi/riscv_encoding.h
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@@ -86,6 +86,8 @@
#define HSTATUS_GVA _UL(0x00000040)
#define HSTATUS_VSBE _UL(0x00000020)
#define MTVEC_MODE _UL(0x00000003)
#define MCAUSE_IRQ_MASK (_UL(1) << (__riscv_xlen - 1))
#define IRQ_S_SOFT 1

4
lib/sbi/sbi_trap.c
View File

@@ -169,7 +169,7 @@ int sbi_trap_redirect(struct sbi_trap_regs *regs,
csr_write(CSR_VSCAUSE, trap->cause);
/* Set MEPC to VS-mode exception vector base */
regs->mepc = csr_read(CSR_VSTVEC);
regs->mepc = csr_read(CSR_VSTVEC) & ~MTVEC_MODE;
/* Set MPP to VS-mode */
regs->mstatus &= ~MSTATUS_MPP;
@@ -204,7 +204,7 @@ int sbi_trap_redirect(struct sbi_trap_regs *regs,
csr_write(CSR_SCAUSE, trap->cause);
/* Set MEPC to S-mode exception vector base */
regs->mepc = csr_read(CSR_STVEC);
regs->mepc = csr_read(CSR_STVEC) & ~MTVEC_MODE;
/* Set MPP to S-mode */
regs->mstatus &= ~MSTATUS_MPP;