From afa0e3091bebf2aaba167f37119a9a4f608a55a8 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Tue, 4 Mar 2025 17:45:43 -0800 Subject: [PATCH] lib: sbi_trap: Add support for vectored interrupts When redirecting an exception to S-mode, transform the (v)stvec CSR value as described in the privileged spec to derive the S-mode PC. Since OpenSBI never redirects interrupts, only synchronous exceptions, the only action needed is to mask out the (v)stvec.MODE field. Reported-by: Jan Reinhard Closes: https://github.com/riscv-software-src/opensbi/issues/391 Signed-off-by: Samuel Holland Reviwed-by: Anup Patel Link: https://lore.kernel.org/r/20250305014729.3143535-1-samuel.holland@sifive.com Signed-off-by: Anup Patel --- include/sbi/riscv_encoding.h | 2 ++ lib/sbi/sbi_trap.c | 4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h index 84d3c17b..64f0249b 100644 --- a/include/sbi/riscv_encoding.h +++ b/include/sbi/riscv_encoding.h @@ -86,6 +86,8 @@ #define HSTATUS_GVA _UL(0x00000040) #define HSTATUS_VSBE _UL(0x00000020) +#define MTVEC_MODE _UL(0x00000003) + #define MCAUSE_IRQ_MASK (_UL(1) << (__riscv_xlen - 1)) #define IRQ_S_SOFT 1 diff --git a/lib/sbi/sbi_trap.c b/lib/sbi/sbi_trap.c index e63a563b..f41db4d1 100644 --- a/lib/sbi/sbi_trap.c +++ b/lib/sbi/sbi_trap.c @@ -169,7 +169,7 @@ int sbi_trap_redirect(struct sbi_trap_regs *regs, csr_write(CSR_VSCAUSE, trap->cause); /* Set MEPC to VS-mode exception vector base */ - regs->mepc = csr_read(CSR_VSTVEC); + regs->mepc = csr_read(CSR_VSTVEC) & ~MTVEC_MODE; /* Set MPP to VS-mode */ regs->mstatus &= ~MSTATUS_MPP; @@ -204,7 +204,7 @@ int sbi_trap_redirect(struct sbi_trap_regs *regs, csr_write(CSR_SCAUSE, trap->cause); /* Set MEPC to S-mode exception vector base */ - regs->mepc = csr_read(CSR_STVEC); + regs->mepc = csr_read(CSR_STVEC) & ~MTVEC_MODE; /* Set MPP to S-mode */ regs->mstatus &= ~MSTATUS_MPP;