Fix plic warm init in platform code.

Pass S-Mode and M-mode context id separately to common warm init.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>

platform/kendryte/k210/platform.c

@@ -43,7 +43,9 @@ static int k210_cold_irqchip_init(void)
 
 static int k210_warm_irqchip_init(u32 core_id)
 {
-	return plic_warm_irqchip_init(core_id);
+	return plic_warm_irqchip_init(core_id,
+				      (2 * core_id),
+				      (2 * core_id + 1));
 }
 
 static int k210_cold_ipi_init(void)

platform/qemu/sifive_u/platform.c

@@ -28,7 +28,13 @@
 
 static int sifive_u_cold_final_init(void)
 {
-	return plic_fdt_fixup(sbi_scratch_thishart_arg1_ptr(), "riscv,plic0");
+	u32 i;
+	void *fdt = sbi_scratch_thishart_arg1_ptr();
+
+	for (i = 0; i < PLAT_HART_COUNT; i++)
+		plic_fdt_fixup(fdt, "riscv,plic0", 2 * i);
+
+	return 0;
 }
 
 static u32 sifive_u_pmp_region_count(u32 target_hart)
@@ -68,6 +74,13 @@ static int sifive_u_cold_irqchip_init(void)
 				      PLAT_HART_COUNT);
 }
 
+static int sifive_u_warm_irqchip_init(u32 target_hart)
+{
+	return plic_warm_irqchip_init(target_hart,
+				      (2 * target_hart),
+				      (2 * target_hart + 1));
+}
+
 static int sifive_u_cold_ipi_init(void)
 {
 	return clint_cold_ipi_init(SIFIVE_U_CLINT_ADDR,
@@ -98,7 +111,7 @@ struct sbi_platform platform = {
 	.console_getc = sifive_uart_getc,
 	.console_init = sifive_u_console_init,
 	.cold_irqchip_init = sifive_u_cold_irqchip_init,
-	.warm_irqchip_init = plic_warm_irqchip_init,
+	.warm_irqchip_init = sifive_u_warm_irqchip_init,
 	.ipi_inject = clint_ipi_inject,
 	.ipi_sync = clint_ipi_sync,
 	.ipi_clear = clint_ipi_clear,

platform/qemu/virt/platform.c

@@ -28,7 +28,13 @@
 
 static int virt_cold_final_init(void)
 {
-	return plic_fdt_fixup(sbi_scratch_thishart_arg1_ptr(), "riscv,plic0");
+	u32 i;
+	void *fdt = sbi_scratch_thishart_arg1_ptr();
+
+	for (i = 0; i < PLAT_HART_COUNT; i++)
+		plic_fdt_fixup(fdt, "riscv,plic0", 2 * i);
+
+	return 0;
 }
 
 static u32 virt_pmp_region_count(u32 target_hart)
@@ -69,6 +75,13 @@ static int virt_cold_irqchip_init(void)
 				      PLAT_HART_COUNT);
 }
 
+static int virt_warm_irqchip_init(u32 target_hart)
+{
+	return plic_warm_irqchip_init(target_hart,
+				      (2 * target_hart),
+				      (2 * target_hart + 1));
+}
+
 static int virt_cold_ipi_init(void)
 {
 	return clint_cold_ipi_init(VIRT_CLINT_ADDR,
@@ -99,7 +112,7 @@ struct sbi_platform platform = {
 	.console_getc = uart8250_getc,
 	.console_init = virt_console_init,
 	.cold_irqchip_init = virt_cold_irqchip_init,
-	.warm_irqchip_init = plic_warm_irqchip_init,
+	.warm_irqchip_init = virt_warm_irqchip_init,
 	.ipi_inject = clint_ipi_inject,
 	.ipi_sync = clint_ipi_sync,
 	.ipi_clear = clint_ipi_clear,

platform/sifive/hifive_u540/platform.c

@@ -35,7 +35,14 @@
 
 static int sifive_u_cold_final_init(void)
 {
-	return plic_fdt_fixup(sbi_scratch_thishart_arg1_ptr(), "riscv,plic0");
+	u32 i;
+	void *fdt = sbi_scratch_thishart_arg1_ptr();
+
+	plic_fdt_fixup(fdt, "riscv,plic0", 0);
+	for (i = 1; i < PLAT_HART_COUNT; i++)
+		plic_fdt_fixup(fdt, "riscv,plic0", 2 * i - 1);
+
+	return 0;
 }
 
 static u32 sifive_u_pmp_region_count(u32 target_hart)
@@ -85,6 +92,13 @@ static int sifive_u_cold_irqchip_init(void)
 				      PLAT_HART_COUNT);
 }
 
+static int sifive_u_warm_irqchip_init(u32 target_hart)
+{
+	return plic_warm_irqchip_init(target_hart,
+			(target_hart) ? (2 * target_hart - 1) : 0,
+			(target_hart) ? (2 * target_hart) : -1);
+}
+
 static int sifive_u_cold_ipi_init(void)
 {
 	return clint_cold_ipi_init(SIFIVE_U_CLINT_ADDR,
@@ -115,7 +129,7 @@ struct sbi_platform platform = {
 	.console_getc = sifive_uart_getc,
 	.console_init = sifive_u_console_init,
 	.cold_irqchip_init = sifive_u_cold_irqchip_init,
-	.warm_irqchip_init = plic_warm_irqchip_init,
+	.warm_irqchip_init = sifive_u_warm_irqchip_init,
 	.ipi_inject = clint_ipi_inject,
 	.ipi_sync = clint_ipi_sync,
 	.ipi_clear = clint_ipi_clear,