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Fix plic warm init in common code.

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Unleashed doesn't have S mode for hart 0.
PLIC register base calculation is current wrong because of that.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
This commit is contained in:
Anup Patel
2018-12-21 15:45:14 -08:00
committed by Atish Patra
parent 95fbe7d495
commit 5148499e03
2 changed files with 25 additions and 27 deletions
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5
platform/common/include/plat/irqchip/plic.h
View File

@@ -12,9 +12,10 @@
#include <sbi/sbi_types.h>
int plic_fdt_fixup(void *fdt, const char *compat);
void plic_fdt_fixup(void *fdt, const char *compat, u32 cntx_id);
int plic_warm_irqchip_init(u32 target_hart);
int plic_warm_irqchip_init(u32 target_hart,
int m_cntx_id, int s_cntx_id);
int plic_cold_irqchip_init(unsigned long base,
u32 num_sources, u32 hart_count);

47
platform/common/irqchip/plic.c
View File

@@ -27,28 +27,20 @@ static void plic_set_priority(u32 source, u32 val)
writel(val, plic_base);
}
static void plic_set_m_thresh(u32 hartid, u32 val)
static void plic_set_thresh(u32 cntxid, u32 val)
{
volatile void *plic_m_thresh = plic_base +
volatile void *plic_thresh = plic_base +
PLIC_CONTEXT_BASE +
PLIC_CONTEXT_STRIDE * (2 * hartid);
writel(val, plic_m_thresh);
PLIC_CONTEXT_STRIDE * cntxid;
writel(val, plic_thresh);
}
static void plic_set_s_thresh(u32 hartid, u32 val)
static void plic_set_ie(u32 cntxid, u32 word_index, u32 val)
{
volatile void *plic_s_thresh = plic_base +
PLIC_CONTEXT_BASE +
PLIC_CONTEXT_STRIDE * (2 * hartid + 1);
writel(val, plic_s_thresh);
}
static void plic_set_s_ie(u32 hartid, u32 word_index, u32 val)
{
volatile void *plic_s_ie = plic_base +
volatile void *plic_ie = plic_base +
PLIC_ENABLE_BASE +
PLIC_ENABLE_STRIDE * (2 * hartid + 1);
writel(val, plic_s_ie + word_index * 4);
PLIC_ENABLE_STRIDE * cntxid;
writel(val, plic_ie + word_index * 4);
}
static void plic_fdt_fixup_prop(const struct fdt_node *node,
@@ -57,6 +49,7 @@ static void plic_fdt_fixup_prop(const struct fdt_node *node,
{
u32 *cells;
u32 i, cells_count;
u32 *cntx_id = priv;
if (!prop)
return;
@@ -70,18 +63,18 @@ static void plic_fdt_fixup_prop(const struct fdt_node *node,
return;
for (i = 0; i < cells_count; i++) {
if (i % 4 == 1)
if (((i % 2) == 1) && ((i / 2) == *cntx_id))
cells[i] = fdt_rev32(0xffffffff);
}
}
int plic_fdt_fixup(void *fdt, const char *compat)
void plic_fdt_fixup(void *fdt, const char *compat, u32 cntx_id)
{
fdt_compat_node_prop(fdt, compat, plic_fdt_fixup_prop, NULL);
return 0;
fdt_compat_node_prop(fdt, compat, plic_fdt_fixup_prop, &cntx_id);
}
int plic_warm_irqchip_init(u32 target_hart)
int plic_warm_irqchip_init(u32 target_hart,
int m_cntx_id, int s_cntx_id)
{
size_t i, ie_words = plic_num_sources / 32 + 1;
@@ -89,14 +82,18 @@ int plic_warm_irqchip_init(u32 target_hart)
return -1;
/* By default, enable all IRQs for S-mode of target HART */
for (i = 0; i < ie_words; i++)
plic_set_s_ie(target_hart, i, -1);
if (s_cntx_id > -1) {
for (i = 0; i < ie_words; i++)
plic_set_ie(s_cntx_id, i, -1);
}
/* By default, enable M-mode threshold */
plic_set_m_thresh(target_hart, 1);
if (m_cntx_id > -1)
plic_set_thresh(m_cntx_id, 1);
/* By default, disable S-mode threshold */
plic_set_s_thresh(target_hart, 0);
if (s_cntx_id > -1)
plic_set_thresh(s_cntx_id, 0);
return 0;
}