Firmware/opensbi
8
0
Fork 0
forked from Mirrors/opensbi
Code Pull Requests Activity

include: Extend struct sbi_trap_info for mtval2 and mtinst

Browse Source 
We have two new trap CSRs namely mtval2 and mtinst when
RISC-V hypervisor extension is available hence we extend
struct sbi_trap_info accordingly.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Anup Patel
2019-12-12 07:22:03 +05:30
committed by Anup Patel
parent 6590a7dab9
commit 4370f18f34
2 changed files with 10 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
include/sbi/sbi_trap.h
View File

@@ -178,6 +178,10 @@ struct sbi_trap_info {
unsigned long cause;
/** tval Trap value */
unsigned long tval;
/** tval2 Trap value 2 */
unsigned long tval2;
/** tinst Trap instruction */
unsigned long tinst;
};
struct sbi_scratch;

6
lib/sbi/sbi_unpriv.c
View File

@@ -24,6 +24,8 @@
trap->epc = 0; \
trap->cause = 0; \
trap->tval = 0; \
trap->tval2 = 0; \
trap->tinst = 0; \
sbi_hart_set_trap_info(scratch, trap); \
asm volatile( \
"csrrs %0, " STR(CSR_MSTATUS) ", %3\n" \
@@ -47,6 +49,8 @@
trap->epc = 0; \
trap->cause = 0; \
trap->tval = 0; \
trap->tval2 = 0; \
trap->tinst = 0; \
sbi_hart_set_trap_info(scratch, trap); \
asm volatile( \
"csrrs %0, " STR(CSR_MSTATUS) ", %3\n" \
@@ -117,6 +121,8 @@ ulong sbi_get_insn(ulong mepc, struct sbi_scratch *scratch,
trap->epc = 0;
trap->cause = 0;
trap->tval = 0;
trap->tval2 = 0;
trap->tinst = 0;
sbi_hart_set_trap_info(scratch, trap);
#ifndef __riscv_compressed