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platform: Add AE350 cache control SBIs

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This patch contains the following AE350 specific SBIs:

- get mcache_ctl status
- get mmisc_ctl status
- set mcache_ctl status
- set mmisc_ctl status
- I-cache operation
- D-cache operation
- enable/disable L1-I-cache prefetch
- enable/disable L1-D-cache prefetch
- enable/disable non-blocking load store
- enable/disable write-around

Signed-off-by: Nylon Chen <nylon7@andestech.com>
Reviewed-by: Anup Patel <Anup.Patel@wdc.com>
Reviewed-by: Atish Patra <Atish.Patra@wdc.com>
This commit is contained in:
Nylon Chen
2020-06-09 13:56:58 +08:00
committed by Anup Patel
parent 980290651f
commit 32f87e5a86
5 changed files with 186 additions and 1 deletions
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89
platform/andes/ae350/cache.c Normal file
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/*
* SPDX-License-Identifier: BSD-2-Clause
*
* Copyright (c) 2020 Andes Technology Corporation
*
* Authors:
* Nylon Chen <nylon7@andestech.com>
*/
#include <sbi/riscv_asm.h>
#include <sbi/riscv_io.h>
#include <sbi/sbi_types.h>
#include "platform.h"
uintptr_t mcall_set_mcache_ctl(unsigned long input)
{
csr_clear(CSR_MCACHECTL, V5_MCACHE_CTL_MASK);
csr_write(CSR_MCACHECTL, input);
return 0;
}
uintptr_t mcall_set_mmisc_ctl(unsigned long input)
{
csr_clear(CSR_MMISCCTL, V5_MMISC_CTL_MASK);
csr_write(CSR_MMISCCTL, input);
return 0;
}
uintptr_t mcall_icache_op(unsigned int enable)
{
if (enable) {
csr_set(CSR_MCACHECTL, V5_MCACHE_CTL_IC_EN);
} else {
csr_clear(CSR_MCACHECTL, V5_MCACHE_CTL_IC_EN);
asm volatile("fence.i\n\t");
}
return 0;
}
uintptr_t mcall_dcache_op(unsigned int enable)
{
if (enable) {
csr_set(CSR_MCACHECTL, V5_MCACHE_CTL_DC_EN);
} else {
csr_clear(CSR_MCACHECTL, V5_MCACHE_CTL_DC_EN);
csr_write(CSR_MCCTLCOMMAND, V5_UCCTL_L1D_WBINVAL_ALL);
}
return 0;
}
uintptr_t mcall_l1_cache_i_prefetch_op(unsigned long enable)
{
if (enable) {
csr_set(CSR_MCACHECTL, V5_MCACHE_CTL_L1I_PREFETCH_EN);
} else {
csr_clear(CSR_MCACHECTL, V5_MCACHE_CTL_L1I_PREFETCH_EN);
}
return 0;
}
uintptr_t mcall_l1_cache_d_prefetch_op(unsigned long enable)
{
if (enable) {
csr_set(CSR_MCACHECTL, V5_MCACHE_CTL_L1D_PREFETCH_EN);
} else {
csr_clear(CSR_MCACHECTL, V5_MCACHE_CTL_L1D_PREFETCH_EN);
}
return 0;
}
uintptr_t mcall_non_blocking_load_store(unsigned long enable)
{
if (enable) {
csr_set(CSR_MCACHECTL, V5_MMISC_CTL_NON_BLOCKING_EN);
} else {
csr_clear(CSR_MCACHECTL, V5_MMISC_CTL_NON_BLOCKING_EN);
}
return 0;
}
uintptr_t mcall_write_around(unsigned long enable)
{
if (enable) {
csr_set(CSR_MCACHECTL, V5_MCACHE_CTL_DC_WAROUND_1_EN);
} else {
csr_clear(CSR_MCACHECTL, V5_MCACHE_CTL_DC_WAROUND_1_EN);
}
return 0;
}