forked from Mirrors/opensbi
32f87e5a86
This patch contains the following AE350 specific SBIs: - get mcache_ctl status - get mmisc_ctl status - set mcache_ctl status - set mmisc_ctl status - I-cache operation - D-cache operation - enable/disable L1-I-cache prefetch - enable/disable L1-D-cache prefetch - enable/disable non-blocking load store - enable/disable write-around Signed-off-by: Nylon Chen <nylon7@andestech.com> Reviewed-by: Anup Patel <Anup.Patel@wdc.com> Reviewed-by: Atish Patra <Atish.Patra@wdc.com>
90 lines
1.8 KiB
C
90 lines
1.8 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2020 Andes Technology Corporation
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*
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* Authors:
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* Nylon Chen <nylon7@andestech.com>
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*/
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#include <sbi/riscv_asm.h>
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#include <sbi/riscv_io.h>
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#include <sbi/sbi_types.h>
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#include "platform.h"
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uintptr_t mcall_set_mcache_ctl(unsigned long input)
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{
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csr_clear(CSR_MCACHECTL, V5_MCACHE_CTL_MASK);
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csr_write(CSR_MCACHECTL, input);
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return 0;
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}
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uintptr_t mcall_set_mmisc_ctl(unsigned long input)
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{
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csr_clear(CSR_MMISCCTL, V5_MMISC_CTL_MASK);
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csr_write(CSR_MMISCCTL, input);
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return 0;
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}
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uintptr_t mcall_icache_op(unsigned int enable)
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{
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if (enable) {
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csr_set(CSR_MCACHECTL, V5_MCACHE_CTL_IC_EN);
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} else {
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csr_clear(CSR_MCACHECTL, V5_MCACHE_CTL_IC_EN);
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asm volatile("fence.i\n\t");
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}
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return 0;
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}
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uintptr_t mcall_dcache_op(unsigned int enable)
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{
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if (enable) {
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csr_set(CSR_MCACHECTL, V5_MCACHE_CTL_DC_EN);
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} else {
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csr_clear(CSR_MCACHECTL, V5_MCACHE_CTL_DC_EN);
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csr_write(CSR_MCCTLCOMMAND, V5_UCCTL_L1D_WBINVAL_ALL);
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}
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return 0;
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}
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uintptr_t mcall_l1_cache_i_prefetch_op(unsigned long enable)
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{
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if (enable) {
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csr_set(CSR_MCACHECTL, V5_MCACHE_CTL_L1I_PREFETCH_EN);
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} else {
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csr_clear(CSR_MCACHECTL, V5_MCACHE_CTL_L1I_PREFETCH_EN);
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}
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return 0;
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}
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uintptr_t mcall_l1_cache_d_prefetch_op(unsigned long enable)
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{
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if (enable) {
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csr_set(CSR_MCACHECTL, V5_MCACHE_CTL_L1D_PREFETCH_EN);
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} else {
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csr_clear(CSR_MCACHECTL, V5_MCACHE_CTL_L1D_PREFETCH_EN);
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}
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return 0;
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}
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uintptr_t mcall_non_blocking_load_store(unsigned long enable)
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{
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if (enable) {
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csr_set(CSR_MCACHECTL, V5_MMISC_CTL_NON_BLOCKING_EN);
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} else {
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csr_clear(CSR_MCACHECTL, V5_MMISC_CTL_NON_BLOCKING_EN);
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}
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return 0;
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}
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uintptr_t mcall_write_around(unsigned long enable)
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{
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if (enable) {
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csr_set(CSR_MCACHECTL, V5_MCACHE_CTL_DC_WAROUND_1_EN);
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} else {
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csr_clear(CSR_MCACHECTL, V5_MCACHE_CTL_DC_WAROUND_1_EN);
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}
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return 0;
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}
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