forked from Mirrors/opensbi
include: sbi: Introduce debug trigger register encodings
This patch introduces Mcontrol and M6 control register encodings along with macros to manipulate them. Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Himanshu Chauhan
committed by
Anup Patel
Anup Patel
parent
20ca19ab03
commit
24997697ae
249
include/sbi/riscv_dbtr.h
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249
include/sbi/riscv_dbtr.h
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@@ -0,0 +1,249 @@
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/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2023 Ventana Micro System, Inc.
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*
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* Authors:
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* Himanshu Chauhan <hchauhan@ventanamicro.com>
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*/
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#ifndef __RISCV_DBTR_H__
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#define __RISCV_DBTR_H__
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#define RV_MAX_TRIGGERS 32
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enum {
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RISCV_DBTR_TRIG_NONE = 0,
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RISCV_DBTR_TRIG_LEGACY,
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RISCV_DBTR_TRIG_MCONTROL,
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RISCV_DBTR_TRIG_ICOUNT,
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RISCV_DBTR_TRIG_ITRIGGER,
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RISCV_DBTR_TRIG_ETRIGGER,
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RISCV_DBTR_TRIG_MCONTROL6,
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};
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#define RV_DBTR_BIT(_prefix, _name) \
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RV_DBTR_##_prefix##_##_name##_BIT
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#define RV_DBTR_BIT_MASK(_prefix, _name) \
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RV_DBTR_##_prefix##_name##_BIT_MASK
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#define RV_DBTR_DECLARE_BIT(_prefix, _name, _val) \
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RV_DBTR_BIT(_prefix, _name) = _val
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#define RV_DBTR_DECLARE_BIT_MASK(_prefix, _name, _width) \
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RV_DBTR_BIT_MASK(_prefix, _name) = \
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(((1UL << _width) - 1) << RV_DBTR_BIT(_prefix, _name))
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#define CLEAR_DBTR_BIT(_target, _prefix, _bit_name) \
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__clear_bit(RV_DBTR_BIT(_prefix, _bit_name), &_target)
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#define SET_DBTR_BIT(_target, _prefix, _bit_name) \
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__set_bit(RV_DBTR_BIT(_prefix, _bit_name), &_target)
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/* Trigger Data 1 */
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enum {
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RV_DBTR_DECLARE_BIT(TDATA1, DATA, 0),
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#if __riscv_xlen == 64
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RV_DBTR_DECLARE_BIT(TDATA1, DMODE, 59),
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RV_DBTR_DECLARE_BIT(TDATA1, TYPE, 60),
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#elif __riscv_xlen == 32
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RV_DBTR_DECLARE_BIT(TDATA1, DMODE, 27),
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RV_DBTR_DECLARE_BIT(TDATA1, TYPE, 28),
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#else
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#error "Unknown __riscv_xlen"
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#endif
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};
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enum {
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#if __riscv_xlen == 64
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RV_DBTR_DECLARE_BIT_MASK(TDATA1, DATA, 59),
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#elif __riscv_xlen == 32
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RV_DBTR_DECLARE_BIT_MASK(TDATA1, DATA, 27),
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#else
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#error "Unknown __riscv_xlen"
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#endif
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RV_DBTR_DECLARE_BIT_MASK(TDATA1, DMODE, 1),
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RV_DBTR_DECLARE_BIT_MASK(TDATA1, TYPE, 4),
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};
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/* MC - Match Control Type Register */
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enum {
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RV_DBTR_DECLARE_BIT(MC, LOAD, 0),
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RV_DBTR_DECLARE_BIT(MC, STORE, 1),
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RV_DBTR_DECLARE_BIT(MC, EXEC, 2),
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RV_DBTR_DECLARE_BIT(MC, U, 3),
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RV_DBTR_DECLARE_BIT(MC, S, 4),
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RV_DBTR_DECLARE_BIT(MC, RES2, 5),
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RV_DBTR_DECLARE_BIT(MC, M, 6),
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RV_DBTR_DECLARE_BIT(MC, MATCH, 7),
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RV_DBTR_DECLARE_BIT(MC, CHAIN, 11),
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RV_DBTR_DECLARE_BIT(MC, ACTION, 12),
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RV_DBTR_DECLARE_BIT(MC, SIZELO, 16),
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RV_DBTR_DECLARE_BIT(MC, TIMING, 18),
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RV_DBTR_DECLARE_BIT(MC, SELECT, 19),
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RV_DBTR_DECLARE_BIT(MC, HIT, 20),
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#if __riscv_xlen >= 64
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RV_DBTR_DECLARE_BIT(MC, SIZEHI, 21),
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#endif
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#if __riscv_xlen == 64
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RV_DBTR_DECLARE_BIT(MC, MASKMAX, 53),
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RV_DBTR_DECLARE_BIT(MC, DMODE, 59),
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RV_DBTR_DECLARE_BIT(MC, TYPE, 60),
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#elif __riscv_xlen == 32
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RV_DBTR_DECLARE_BIT(MC, MASKMAX, 21),
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RV_DBTR_DECLARE_BIT(MC, DMODE, 27),
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RV_DBTR_DECLARE_BIT(MC, TYPE, 28),
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#else
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#error "Unknown __riscv_xlen"
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#endif
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};
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enum {
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RV_DBTR_DECLARE_BIT_MASK(MC, LOAD, 1),
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RV_DBTR_DECLARE_BIT_MASK(MC, STORE, 1),
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RV_DBTR_DECLARE_BIT_MASK(MC, EXEC, 1),
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RV_DBTR_DECLARE_BIT_MASK(MC, U, 1),
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RV_DBTR_DECLARE_BIT_MASK(MC, S, 1),
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RV_DBTR_DECLARE_BIT_MASK(MC, RES2, 1),
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RV_DBTR_DECLARE_BIT_MASK(MC, M, 1),
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RV_DBTR_DECLARE_BIT_MASK(MC, MATCH, 4),
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RV_DBTR_DECLARE_BIT_MASK(MC, CHAIN, 1),
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RV_DBTR_DECLARE_BIT_MASK(MC, ACTION, 4),
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RV_DBTR_DECLARE_BIT_MASK(MC, SIZELO, 2),
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RV_DBTR_DECLARE_BIT_MASK(MC, TIMING, 1),
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RV_DBTR_DECLARE_BIT_MASK(MC, SELECT, 1),
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RV_DBTR_DECLARE_BIT_MASK(MC, HIT, 1),
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#if __riscv_xlen >= 64
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RV_DBTR_DECLARE_BIT_MASK(MC, SIZEHI, 2),
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#endif
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RV_DBTR_DECLARE_BIT_MASK(MC, MASKMAX, 6),
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RV_DBTR_DECLARE_BIT_MASK(MC, DMODE, 1),
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RV_DBTR_DECLARE_BIT_MASK(MC, TYPE, 4),
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};
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/* MC6 - Match Control 6 Type Register */
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enum {
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RV_DBTR_DECLARE_BIT(MC6, LOAD, 0),
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RV_DBTR_DECLARE_BIT(MC6, STORE, 1),
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RV_DBTR_DECLARE_BIT(MC6, EXEC, 2),
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RV_DBTR_DECLARE_BIT(MC6, U, 3),
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RV_DBTR_DECLARE_BIT(MC6, S, 4),
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RV_DBTR_DECLARE_BIT(MC6, RES2, 5),
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RV_DBTR_DECLARE_BIT(MC6, M, 6),
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RV_DBTR_DECLARE_BIT(MC6, MATCH, 7),
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RV_DBTR_DECLARE_BIT(MC6, CHAIN, 11),
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RV_DBTR_DECLARE_BIT(MC6, ACTION, 12),
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RV_DBTR_DECLARE_BIT(MC6, SIZE, 16),
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RV_DBTR_DECLARE_BIT(MC6, TIMING, 20),
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RV_DBTR_DECLARE_BIT(MC6, SELECT, 21),
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RV_DBTR_DECLARE_BIT(MC6, HIT, 22),
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RV_DBTR_DECLARE_BIT(MC6, VU, 23),
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RV_DBTR_DECLARE_BIT(MC6, VS, 24),
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#if __riscv_xlen == 64
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RV_DBTR_DECLARE_BIT(MC6, DMODE, 59),
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RV_DBTR_DECLARE_BIT(MC6, TYPE, 60),
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#elif __riscv_xlen == 32
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RV_DBTR_DECLARE_BIT(MC6, DMODE, 27),
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RV_DBTR_DECLARE_BIT(MC6, TYPE, 28),
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#else
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#error "Unknown __riscv_xlen"
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#endif
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};
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enum {
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RV_DBTR_DECLARE_BIT_MASK(MC6, LOAD, 1),
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RV_DBTR_DECLARE_BIT_MASK(MC6, STORE, 1),
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RV_DBTR_DECLARE_BIT_MASK(MC6, EXEC, 1),
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RV_DBTR_DECLARE_BIT_MASK(MC6, U, 1),
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RV_DBTR_DECLARE_BIT_MASK(MC6, S, 1),
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RV_DBTR_DECLARE_BIT_MASK(MC6, RES2, 1),
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RV_DBTR_DECLARE_BIT_MASK(MC6, M, 1),
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RV_DBTR_DECLARE_BIT_MASK(MC6, MATCH, 4),
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RV_DBTR_DECLARE_BIT_MASK(MC6, CHAIN, 1),
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RV_DBTR_DECLARE_BIT_MASK(MC6, ACTION, 4),
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RV_DBTR_DECLARE_BIT_MASK(MC6, SIZE, 4),
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RV_DBTR_DECLARE_BIT_MASK(MC6, TIMING, 1),
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RV_DBTR_DECLARE_BIT_MASK(MC6, SELECT, 1),
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RV_DBTR_DECLARE_BIT_MASK(MC6, HIT, 1),
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RV_DBTR_DECLARE_BIT_MASK(MC6, VU, 1),
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RV_DBTR_DECLARE_BIT_MASK(MC6, VS, 1),
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#if __riscv_xlen == 64
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RV_DBTR_DECLARE_BIT_MASK(MC6, DMODE, 1),
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RV_DBTR_DECLARE_BIT_MASK(MC6, TYPE, 4),
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#elif __riscv_xlen == 32
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RV_DBTR_DECLARE_BIT_MASK(MC6, DMODE, 1),
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RV_DBTR_DECLARE_BIT_MASK(MC6, TYPE, 4),
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#else
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#error "Unknown __riscv_xlen"
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#endif
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};
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#define RV_DBTR_SET_TDATA1_TYPE(_t1, _type) \
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do { \
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_t1 &= ~RV_DBTR_BIT_MASK(TDATA1, TYPE); \
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_t1 |= (((unsigned long)_type \
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<< RV_DBTR_BIT(TDATA1, TYPE)) \
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& RV_DBTR_BIT_MASK(TDATA1, TYPE)); \
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}while (0);
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#define RV_DBTR_SET_MC_TYPE(_t1, _type) \
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do { \
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_t1 &= ~RV_DBTR_BIT_MASK(MC, TYPE); \
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_t1 |= (((unsigned long)_type \
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<< RV_DBTR_BIT(MC, TYPE)) \
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& RV_DBTR_BIT_MASK(MC, TYPE)); \
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}while (0);
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#define RV_DBTR_SET_MC6_TYPE(_t1, _type) \
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do { \
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_t1 &= ~RV_DBTR_BIT_MASK(MC6, TYPE); \
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_t1 |= (((unsigned long)_type \
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<< RV_DBTR_BIT(MC6, TYPE)) \
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& RV_DBTR_BIT_MASK(MC6, TYPE)); \
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}while (0);
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#define RV_DBTR_SET_MC_EXEC(_t1) \
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SET_DBTR_BIT(_t1, MC, EXEC)
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#define RV_DBTR_SET_MC_LOAD(_t1) \
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SET_DBTR_BIT(_t1, MC, LOAD)
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#define RV_DBTR_SET_MC_STORE(_t1) \
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SET_DBTR_BIT(_t1, MC, STORE)
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#define RV_DBTR_SET_MC_SIZELO(_t1, _val) \
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do { \
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_t1 &= ~RV_DBTR_BIT_MASK(MC, SIZELO); \
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_t1 |= ((_val << RV_DBTR_BIT(MC, SIZELO)) \
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& RV_DBTR_BIT_MASK(MC, SIZELO)); \
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} while(0);
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#define RV_DBTR_SET_MC_SIZEHI(_t1, _val) \
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do { \
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_t1 &= ~RV_DBTR_BIT_MASK(MC, SIZEHI); \
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_t1 |= ((_val << RV_DBTR_BIT(MC, SIZEHI)) \
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& RV_DBTR_BIT_MASK(MC, SIZEHI)); \
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} while(0);
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#define RV_DBTR_SET_MC6_EXEC(_t1) \
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SET_DBTR_BIT(_t1, MC6, EXEC)
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#define RV_DBTR_SET_MC6_LOAD(_t1) \
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SET_DBTR_BIT(_t1, MC6, LOAD)
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#define RV_DBTR_SET_MC6_STORE(_t1) \
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SET_DBTR_BIT(_t1, MC6, STORE)
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#define RV_DBTR_SET_MC6_SIZE(_t1, _val) \
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do { \
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_t1 &= ~RV_DBTR_BIT_MASK(MC6, SIZE); \
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_t1 |= ((_val << RV_DBTR_BIT(MC6, SIZE)) \
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& RV_DBTR_BIT_MASK(MC6, SIZE)); \
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} while(0);
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typedef unsigned long riscv_dbtr_tdata1_mcontrol_t;
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typedef unsigned long riscv_dbtr_tdata1_mcontrol6_t;
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typedef unsigned long riscv_dbtr_tdata1_t;
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#endif /* __RISCV_DBTR_H__ */
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