Firmware
/
MNRS-BM-BSP
7
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

cleans bsp a bit up

This commit is contained in:
Eyck Jentzsch 2024-01-14 08:14:57 +01:00
parent 5e7c2cbce9
commit b5101117aa
17 changed files with 150 additions and 387 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

52
env/abi_eabi.txt vendored Normal file
View File

@ -0,0 +1,52 @@
EABI Name Description Saver
x0 zero Hard-wired zero value -
x1 ra Return address Caller
x2 sp Stack pointer Callee
x3 gp Global pointer -
x4 tp Thread pointer -
x5 t0 Temporary/link register Caller
x6 s3 Saved register Callee
x7 s4 Saved register Callee
x8 s0/fp Saved register/frame pointer Callee
x9 s1 Saved register Callee
x10 a0 Argument/return value Caller
x11 a1 Argument/return value Caller
x12 a2 Argument Caller
x13 a3 Argument Caller
x14 s2 Saved register Callee
x15 t1 Temporary Caller
x16-x31 s5-s20 Saved registers Callee
reg ABI Use by convention Preserved?
x0 zero hardwired to 0, ignores writes n/a
x1 ra return address for jumps no
x2 sp stack pointer yes
x3 gp global pointer n/a
x4 tp thread pointer n/a
x5 t0 temporary register 0 no
x6 t1 temporary register 1 no
x7 t2 temporary register 2 no
x8 s0/fp saved register 0 or frame pointer yes
x9 s1 saved register 1 yes
x10 a0 argument/return value 0 no
x11 a1 argument/return value 1 no
x12 a2 argument 2 no
x13 a3 argument 3 no
x14 a4 argument 4 no
x15 a5 argument 5 no
x16 a6 argument 6 no
x17 a7 argument 7 no
x18 s2 saved register 2 yes
x19 s3 saved register 3 yes
x20 s4 saved register 4 yes
x21 s5 saved register 5 yes
x22 s6 saved register 6 yes
x23 s7 saved register 7 yes
x24 s8 saved register 8 yes
x25 s9 saved register 9 yes
x26 s10 saved register 10 yes
x27 s11 saved register 11 yes
x28 t3 temporary register 3 no
x29 t4 temporary register 4 no
x30 t5 temporary register 5 no
x31 t6 temporary register 6 no

112
env/ehrenberg/platform.h vendored
View File

@ -8,104 +8,32 @@
#define MCAUSE_CAUSE 0x7FFFFFFF
#include "ehrenberg/const.h"
#include "ehrenberg/devices.h"
/****************************************************************************
* Platform definitions
*****************************************************************************/
#define APB_BUS
// Memory map
#define MASKROM_BASE_ADDR _AC(0x00001000,UL)
#define TRAPVEC_TABLE_BASE_ADDR _AC(0x00001010,UL)
#define OTP_MMAP_ADDR _AC(0x00020000,UL)
#define CLINT_BASE_ADDR _AC(0x02000000,UL)
#define PLIC_BASE_ADDR _AC(0x0C000000,UL)
#define AON_BASE_ADDR _AC(0x10000000,UL)
#define PRCI_BASE_ADDR _AC(0x10008000,UL)
#define OTP_BASE_ADDR _AC(0x10010000,UL)
#define GPIO_BASE_ADDR _AC(0x10012000,UL)
#define UART0_BASE_ADDR _AC(0x10013000,UL)
#define SPI0_BASE_ADDR _AC(0x10014000,UL)
#define PWM0_BASE_ADDR _AC(0x10015000,UL)
#define UART1_BASE_ADDR _AC(0x10023000,UL)
#define SPI1_BASE_ADDR _AC(0x10024000,UL)
#define PWM1_BASE_ADDR _AC(0x10025000,UL)
#define SPI2_BASE_ADDR _AC(0x10034000,UL)
#define PWM2_BASE_ADDR _AC(0x10035000,UL)
#define SPI0_MMAP_ADDR _AC(0x20000000,UL)
#define MEM_BASE_ADDR _AC(0x80000000,UL)
#include "devices/gpio.h"
#include "devices/interrupt.h"
#include "devices/timer.h"
#include "devices/uart.h"
#include "devices/qspi.h"
// IOF masks
#define IOF0_SPI1_MASK _AC(0x000007FC,UL)
#define SPI11_NUM_SS (4)
#define IOF_SPI1_SS0 (2u)
#define IOF_SPI1_SS1 (8u)
#define IOF_SPI1_SS2 (9u)
#define IOF_SPI1_SS3 (10u)
#define IOF_SPI1_MOSI (3u)
#define IOF_SPI1_MISO (4u)
#define IOF_SPI1_SCK (5u)
#define IOF_SPI1_DQ0 (3u)
#define IOF_SPI1_DQ1 (4u)
#define IOF_SPI1_DQ2 (6u)
#define IOF_SPI1_DQ3 (7u)
#define PERIPH(TYPE, ADDR) ((volatile TYPE*) (ADDR))
#define IOF0_SPI2_MASK _AC(0xFC000000,UL)
#define SPI2_NUM_SS (1)
#define IOF_SPI2_SS0 (26u)
#define IOF_SPI2_MOSI (27u)
#define IOF_SPI2_MISO (28u)
#define IOF_SPI2_SCK (29u)
#define IOF_SPI2_DQ0 (27u)
#define IOF_SPI2_DQ1 (28u)
#define IOF_SPI2_DQ2 (30u)
#define IOF_SPI2_DQ3 (31u)
#define APB_BASE 0xF0000000
#define TIMER_BASE (APB_BASE+0x30000)
//#define IOF0_I2C_MASK _AC(0x00003000,UL)
#define gpio_a PERIPH(gpio_t, APB_BASE+0x00000)
//#define gpio_b PERIPH(gpio_t, APB_BASE+0x10000)
#define uart PERIPH(uart_t, APB_BASE+0x10000)
#define prescaler PERIPH(uart_t, TIMER_BASE+0x0)
#define timer_a PERIPH(uart_t, TIMER_BASE+0x10)
#define timer_b PERIPH(uart_t, TIMER_BASE+0x20)
#define mtimer PERIPH(mtimer_t, APB_BASE+0x30000)
#define irq PERIPH(irq_t, APB_BASE+0x40000)
#define qspi PERIPH(qspi_t, APB_BASE+0x50000)
//volatile qspi_t* const qspi = (qspi_t*)(APB_BASE+0x50000);
#define IOF0_UART0_MASK _AC(0x00030000, UL)
#define IOF_UART0_RX (16u)
#define IOF_UART0_TX (17u)
#define IOF0_UART1_MASK _AC(0x03000000, UL)
#define IOF_UART1_RX (24u)
#define IOF_UART1_TX (25u)
#define IOF1_PWM0_MASK _AC(0x0000000F, UL)
#define IOF1_PWM1_MASK _AC(0x00780000, UL)
#define IOF1_PWM2_MASK _AC(0x00003C00, UL)
// Interrupt numbers
#define INT_RESERVED 0
#define INT_WDOGCMP 1
#define INT_RTCCMP 2
#define INT_UART0_BASE 3
#define INT_UART1_BASE 4
#define INT_SPI0_BASE 5
#define INT_SPI1_BASE 6
#define INT_SPI2_BASE 7
#define INT_GPIO_BASE 8
#define INT_PWM0_BASE 40
#define INT_PWM1_BASE 44
#define INT_PWM2_BASE 48
// Helper functions
#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i)))
#define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i)))
#define AON_REG(offset) _REG32(AON_BASE_ADDR, offset)
#define CLINT_REG(offset) _REG32(CLINT_BASE_ADDR, offset)
#define GPIO_REG(offset) _REG32(GPIO_BASE_ADDR, offset)
#define OTP_REG(offset) _REG32(OTP_BASE_ADDR, offset)
#define PLIC_REG(offset) _REG32(PLIC_BASE_ADDR, offset)
#define PRCI_REG(offset) _REG32(PRCI_BASE_ADDR, offset)
#define PWM0_REG(offset) _REG32(PWM0_BASE_ADDR, offset)
#define PWM1_REG(offset) _REG32(PWM1_BASE_ADDR, offset)
#define PWM2_REG(offset) _REG32(PWM2_BASE_ADDR, offset)
#define SPI0_REG(offset) _REG32(SPI0_BASE_ADDR, offset)
#define SPI1_REG(offset) _REG32(SPI1_BASE_ADDR, offset)
#define SPI2_REG(offset) _REG32(SPI2_BASE_ADDR, offset)
#define UART0_REG(offset) _REG32(UART0_BASE_ADDR, offset)
#define UART1_REG(offset) _REG32(UART1_BASE_ADDR, offset)
#define XIP_START_LOC 0xE0040000
// Misc

122
env/entry.S vendored
View File

@ -10,85 +10,67 @@
.align 2
.global trap_entry
trap_entry:
addi sp, sp, -32*REGBYTES
STORE x1, 1*REGBYTES(sp)
STORE x2, 2*REGBYTES(sp)
STORE x3, 3*REGBYTES(sp)
STORE x4, 4*REGBYTES(sp)
STORE x5, 5*REGBYTES(sp)
STORE x6, 6*REGBYTES(sp)
STORE x7, 7*REGBYTES(sp)
STORE x8, 8*REGBYTES(sp)
STORE x9, 9*REGBYTES(sp)
STORE x10, 10*REGBYTES(sp)
STORE x11, 11*REGBYTES(sp)
STORE x12, 12*REGBYTES(sp)
STORE x13, 13*REGBYTES(sp)
STORE x14, 14*REGBYTES(sp)
STORE x15, 15*REGBYTES(sp)
#ifndef __riscv_abi_rve
STORE x16, 16*REGBYTES(sp)
STORE x17, 17*REGBYTES(sp)
STORE x18, 18*REGBYTES(sp)
STORE x19, 19*REGBYTES(sp)
STORE x20, 20*REGBYTES(sp)
STORE x21, 21*REGBYTES(sp)
STORE x22, 22*REGBYTES(sp)
STORE x23, 23*REGBYTES(sp)
STORE x24, 24*REGBYTES(sp)
STORE x25, 25*REGBYTES(sp)
STORE x26, 26*REGBYTES(sp)
STORE x27, 27*REGBYTES(sp)
STORE x28, 28*REGBYTES(sp)
STORE x29, 29*REGBYTES(sp)
STORE x30, 30*REGBYTES(sp)
STORE x31, 31*REGBYTES(sp)
addi sp, sp, -8*REGBYTES
STORE x1, 1*REGBYTES(sp) // ra
STORE x5, 2*REGBYTES(sp) // t0
STORE x10, 3*REGBYTES(sp) // a0
STORE x11, 4*REGBYTES(sp) // a1
STORE x12, 5*REGBYTES(sp) // a2
STORE x13, 6*REGBYTES(sp) // a3
STORE x15, 7*REGBYTES(sp) // t1
#else
addi sp, sp, -16*REGBYTES
STORE x1, 1*REGBYTES(sp) // ra
STORE x5, 2*REGBYTES(sp) // t0
STORE x6, 3*REGBYTES(sp) // t1
STORE x7, 4*REGBYTES(sp) // t2
STORE x10, 5*REGBYTES(sp) // a0
STORE x11, 6*REGBYTES(sp) // a1
STORE x12, 7*REGBYTES(sp) // a2
STORE x13, 8*REGBYTES(sp) // a3
STORE x14, 9*REGBYTES(sp) // a4
STORE x15, 10*REGBYTES(sp) // a5
STORE x16, 11*REGBYTES(sp) // a6
STORE x17, 12*REGBYTES(sp) // a7
STORE x28, 13*REGBYTES(sp) // t3
STORE x29, 14*REGBYTES(sp) // t4
STORE x30, 15*REGBYTES(sp) // t5
STORE x31, 16*REGBYTES(sp) // t6
#endif
csrr a0, mcause
csrr a1, mepc
mv a2, sp
call handle_trap
csrw mepc, a0
# Remain in M-mode after mret
li t0, MSTATUS_MPP
csrs mstatus, t0
LOAD x1, 1*REGBYTES(sp)
LOAD x2, 2*REGBYTES(sp)
LOAD x3, 3*REGBYTES(sp)
LOAD x4, 4*REGBYTES(sp)
LOAD x5, 5*REGBYTES(sp)
LOAD x6, 6*REGBYTES(sp)
LOAD x7, 7*REGBYTES(sp)
LOAD x8, 8*REGBYTES(sp)
LOAD x9, 9*REGBYTES(sp)
LOAD x10, 10*REGBYTES(sp)
LOAD x11, 11*REGBYTES(sp)
LOAD x12, 12*REGBYTES(sp)
LOAD x13, 13*REGBYTES(sp)
LOAD x14, 14*REGBYTES(sp)
LOAD x15, 15*REGBYTES(sp)
#ifndef __riscv_abi_rve
LOAD x16, 16*REGBYTES(sp)
LOAD x17, 17*REGBYTES(sp)
LOAD x18, 18*REGBYTES(sp)
LOAD x19, 19*REGBYTES(sp)
LOAD x20, 20*REGBYTES(sp)
LOAD x21, 21*REGBYTES(sp)
LOAD x22, 22*REGBYTES(sp)
LOAD x23, 23*REGBYTES(sp)
LOAD x24, 24*REGBYTES(sp)
LOAD x25, 25*REGBYTES(sp)
LOAD x26, 26*REGBYTES(sp)
LOAD x27, 27*REGBYTES(sp)
LOAD x28, 28*REGBYTES(sp)
LOAD x29, 29*REGBYTES(sp)
LOAD x30, 30*REGBYTES(sp)
LOAD x31, 31*REGBYTES(sp)
addi sp, sp, -8*REGBYTES
LOAD x1, 1*REGBYTES(sp) // ra
LOAD x5, 2*REGBYTES(sp) // t0
LOAD x10, 3*REGBYTES(sp) // a0
LOAD x11, 4*REGBYTES(sp) // a1
LOAD x12, 5*REGBYTES(sp) // a2
LOAD x13, 6*REGBYTES(sp) // a3
LOAD x15, 7*REGBYTES(sp) // t1
#else
addi sp, sp, -16*REGBYTES
LOAD x1, 1*REGBYTES(sp) // ra
LOAD x5, 2*REGBYTES(sp) // t0
LOAD x6, 3*REGBYTES(sp) // t1
LOAD x7, 4*REGBYTES(sp) // t2
LOAD x10, 5*REGBYTES(sp) // a0
LOAD x11, 6*REGBYTES(sp) // a1
LOAD x12, 7*REGBYTES(sp) // a2
LOAD x13, 8*REGBYTES(sp) // a3
LOAD x14, 9*REGBYTES(sp) // a4
LOAD x15, 10*REGBYTES(sp) // a5
LOAD x16, 11*REGBYTES(sp) // a6
LOAD x17, 12*REGBYTES(sp) // a7
LOAD x28, 13*REGBYTES(sp) // t3
LOAD x29, 14*REGBYTES(sp) // t4
LOAD x30, 15*REGBYTES(sp) // t5
LOAD x31, 16*REGBYTES(sp) // t6
#endif
addi sp, sp, 32*REGBYTES
mret
.weak handle_trap

2
env/hifive1/platform.h vendored
View File

@ -7,7 +7,7 @@
#define MCAUSE_INT 0x80000000
#define MCAUSE_CAUSE 0x7FFFFFFF
#include "sifive/const.h"
#include "bits.h"
#include "sifive/devices/aon.h"
#include "sifive/devices/clint.h"
#include "sifive/devices/gpio.h"

13
env/rtl/platform.h vendored
View File

@ -7,7 +7,18 @@
#define MCAUSE_INT 0x80000000
#define MCAUSE_CAUSE 0x7FFFFFFF
#include "rtl/const.h"
#define UART0_BASE_ADDR 0xffff0000ULL
#define UART_REG_TXFIFO 0x00
#define UART_REG_RXFIFO 0x04
#define UART_REG_TXCTRL 0x08
#define UART_REG_RXCTRL 0x0c
#define UART_REG_IE 0x10
#define UART_REG_IP 0x14
#define UART_REG_DIV 0x18
#define UART_TXEN 0x1
#define UART0_REG(ADDR) *((volatile uint32_t*) (UART0_BASE_ADDR + ADDR))
/****************************************************************************
* Platform definitions
*****************************************************************************/

4
env/start.S vendored
View File

@ -5,10 +5,10 @@
.type _start,@function
_start:
la gp, trap_entry
csrw mtvec, gp
.option push
.option norelax
la gp, trap_entry
csrw mtvec, gp
la gp, __global_pointer$
.option pop
la sp, _sp

11
include/tgc-vp/bits.h → include/bits.h
View File

@ -32,4 +32,15 @@
#endif
#define REGBYTES (1 << LOG_REGBYTES)
#ifdef __ASSEMBLER__
#define _AC(X,Y) X
#define _AT(T,X) X
#else
#define _AC(X,Y) (X##Y)
#define _AT(T,X) ((T)(X))
#endif /* !__ASSEMBLER__*/
#define _BITUL(x) (_AC(1,UL) << (x))
#define _BITULL(x) (_AC(1,ULL) << (x))
#endif

18
include/ehrenberg/const.h
View File

@ -1,18 +0,0 @@
// See LICENSE for license details.
/* Derived from <linux/const.h> */
#ifndef _SIFIVE_CONST_H
#define _SIFIVE_CONST_H
#ifdef __ASSEMBLER__
#define _AC(X,Y) X
#define _AT(T,X) X
#else
#define _AC(X,Y) (X##Y)
#define _AT(T,X) ((T)(X))
#endif /* !__ASSEMBLER__*/
#define _BITUL(x) (_AC(1,UL) << (x))
#define _BITULL(x) (_AC(1,ULL) << (x))
#endif /* _SIFIVE_CONST_H */

37
include/ehrenberg/devices.h
View File

@ -1,37 +0,0 @@
/*
* devices.c
*
* Created on: Aug 15, 2020
* Author: eyck
*/
#ifndef _BSP_EHRENBERG_DEVICES_C_
#define _BSP_EHRENBERG_DEVICES_C_
#define APB_BUS
#include "devices/gpio.h"
#include "devices/interrupt.h"
#include "devices/timer.h"
#include "devices/uart.h"
#include "devices/qspi.h"
#define PERIPH(TYPE, ADDR) ((volatile TYPE*) (ADDR))
#define APB_BASE 0xF0000000
#define TIMER_BASE (APB_BASE+0x30000)
#define gpio_a PERIPH(gpio_t, APB_BASE+0x00000)
//#define gpio_b PERIPH(gpio_t, APB_BASE+0x10000)
#define uart PERIPH(uart_t, APB_BASE+0x10000)
#define prescaler PERIPH(uart_t, TIMER_BASE+0x0)
#define timer_a PERIPH(uart_t, TIMER_BASE+0x10)
#define timer_b PERIPH(uart_t, TIMER_BASE+0x20)
#define mtimer PERIPH(mtimer_t, APB_BASE+0x30000)
#define irq PERIPH(irq_t, APB_BASE+0x40000)
#define qspi PERIPH(qspi_t, APB_BASE+0x50000)
//volatile qspi_t* const qspi = (qspi_t*)(APB_BASE+0x50000);
#define XIP_START_LOC 0xE0040000
#endif /* _BSP_EHRENBERG_DEVICES_C_ */

35
include/rtl/bits.h
View File

@ -1,35 +0,0 @@
#ifndef _RISCV_BITS_H
#define _RISCV_BITS_H
#define likely(x) __builtin_expect((x), 1)
#define unlikely(x) __builtin_expect((x), 0)
#define ROUNDUP(a, b) ((((a)-1)/(b)+1)*(b))
#define ROUNDDOWN(a, b) ((a)/(b)*(b))
#define MAX(a, b) ((a) > (b) ? (a) : (b))
#define MIN(a, b) ((a) < (b) ? (a) : (b))
#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi)
#define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1)))
#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1))))
#define STR(x) XSTR(x)
#define XSTR(x) #x
#ifdef __riscv64
# define SLL32 sllw
# define STORE sd
# define LOAD ld
# define LWU lwu
# define LOG_REGBYTES 3
#else
# define SLL32 sll
# define STORE sw
# define LOAD lw
# define LWU lw
# define LOG_REGBYTES 2
#endif
#define REGBYTES (1 << LOG_REGBYTES)
#endif

27
include/rtl/const.h
View File

@ -1,27 +0,0 @@
#ifndef _RTL_CONST_H
#define _RTL_CONST_H
#ifdef __ASSEMBLER__
#define _AC(X,Y) X
#define _AT(T,X) X
#else
#define _AC(X,Y) (X##Y)
#define _AT(T,X) ((T)(X))
#endif /* !__ASSEMBLER__*/
#define _BITUL(x) (_AC(1,UL) << (x))
#define _BITULL(x) (_AC(1,ULL) << (x))
#define UART0_BASE_ADDR 0xffff0000ULL
#define UART_REG_TXFIFO 0x00
#define UART_REG_RXFIFO 0x04
#define UART_REG_TXCTRL 0x08
#define UART_REG_RXCTRL 0x0c
#define UART_REG_IE 0x10
#define UART_REG_IP 0x14
#define UART_REG_DIV 0x18
#define UART_TXEN 0x1
#define UART0_REG(ADDR) *((volatile uint32_t*) (UART0_BASE_ADDR + ADDR))
#endif /* _RTL_CONST_H */

0
include/rtl/sections.h → include/sections.h
View File

36
include/sifive/bits.h
View File

@ -1,36 +0,0 @@
// See LICENSE for license details.
#ifndef _RISCV_BITS_H
#define _RISCV_BITS_H
#define likely(x) __builtin_expect((x), 1)
#define unlikely(x) __builtin_expect((x), 0)
#define ROUNDUP(a, b) ((((a)-1)/(b)+1)*(b))
#define ROUNDDOWN(a, b) ((a)/(b)*(b))
#define MAX(a, b) ((a) > (b) ? (a) : (b))
#define MIN(a, b) ((a) < (b) ? (a) : (b))
#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi)
#define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1)))
#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1))))
#define STR(x) XSTR(x)
#define XSTR(x) #x
#if __riscv_xlen == 64
# define SLL32 sllw
# define STORE sd
# define LOAD ld
# define LWU lwu
# define LOG_REGBYTES 3
#else
# define SLL32 sll
# define STORE sw
# define LOAD lw
# define LWU lw
# define LOG_REGBYTES 2
#endif
#define REGBYTES (1 << LOG_REGBYTES)
#endif

18
include/sifive/const.h
View File

@ -1,18 +0,0 @@
// See LICENSE for license details.
/* Derived from <linux/const.h> */
#ifndef _SIFIVE_CONST_H
#define _SIFIVE_CONST_H
#ifdef __ASSEMBLER__
#define _AC(X,Y) X
#define _AT(T,X) X
#else
#define _AC(X,Y) (X##Y)
#define _AT(T,X) ((T)(X))
#endif /* !__ASSEMBLER__*/
#define _BITUL(x) (_AC(1,UL) << (x))
#define _BITULL(x) (_AC(1,ULL) << (x))
#endif /* _SIFIVE_CONST_H */

17
include/sifive/sections.h
View File

@ -1,17 +0,0 @@
// See LICENSE for license details.
#ifndef _SECTIONS_H
#define _SECTIONS_H
extern unsigned char _rom[];
extern unsigned char _rom_end[];
extern unsigned char _ram[];
extern unsigned char _ram_end[];
extern unsigned char _ftext[];
extern unsigned char _etext[];
extern unsigned char _fbss[];
extern unsigned char _ebss[];
extern unsigned char _end[];
#endif /* _SECTIONS_H */

17
include/tgc-vp/const.h
View File

@ -1,17 +0,0 @@
/* Derived from <linux/const.h> */
#ifndef _SIFIVE_CONST_H
#define _SIFIVE_CONST_H
#ifdef __ASSEMBLER__
#define _AC(X,Y) X
#define _AT(T,X) X
#else
#define _AC(X,Y) (X##Y)
#define _AT(T,X) ((T)(X))
#endif /* !__ASSEMBLER__*/
#define _BITUL(x) (_AC(1,UL) << (x))
#define _BITULL(x) (_AC(1,ULL) << (x))
#endif /* _SIFIVE_CONST_H */

16
include/tgc-vp/sections.h
View File

@ -1,16 +0,0 @@
#ifndef _SECTIONS_H
#define _SECTIONS_H
extern unsigned char _rom[];
extern unsigned char _rom_end[];
extern unsigned char _ram[];
extern unsigned char _ram_end[];
extern unsigned char _ftext[];
extern unsigned char _etext[];
extern unsigned char _fbss[];
extern unsigned char _ebss[];
extern unsigned char _end[];
#endif /* _SECTIONS_H */