adds support for new mnrs peripherals

include/ehrenberg/devices/aclint.h

@@ -0,0 +1,29 @@
+#ifndef _BSP_ACLINT_H
+#define _BSP_ACLINT_H
+
+#include <stdint.h>
+#include "gen/Apb3AClint.h"
+
+#define aclint_t apb3aclint_t
+
+static void set_aclint_mtime(volatile aclint_t* reg, uint64_t value){
+    set_aclint_mtime_hi(reg, (uint32_t)(value >> 32));
+    set_aclint_mtime_lo(reg, (uint32_t)value);
+}
+
+static uint64_t get_aclint_mtime(volatile aclint_t* reg){
+    uint64_t value = ((uint64_t)get_aclint_mtime_hi(reg) << 32) | (uint64_t)get_aclint_mtime_lo(reg);
+    return value;
+}
+
+static void set_aclint_mtimecmp(volatile aclint_t* reg, uint64_t value){
+    set_aclint_mtimecmp0hi(reg, (uint32_t)(value >> 32));
+    set_aclint_mtimecmp0lo(reg, (uint32_t)value);
+}
+
+static uint64_t get_aclint_mtimecmp(volatile aclint_t* reg){
+    uint64_t value = ((uint64_t)get_aclint_mtimecmp0hi(reg) << 32) | (uint64_t)get_aclint_mtimecmp0lo(reg);
+    return value;
+}
+
+#endif /* _BSP_ACLINT_H */

include/ehrenberg/devices/gen/Apb3AClint.h

@@ -0,0 +1,53 @@
+/*
+* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Generated at 2024-02-19 14:24:37 UTC 
+* by peakrdl_mnrs version 1.2.2
+*/
+
+#ifndef _BSP_APB3ACLINT_H
+#define _BSP_APB3ACLINT_H
+
+#include <stdint.h>
+
+typedef struct __attribute((__packed__)) {
+    volatile uint32_t MSIP0;
+    volatile uint32_t MTIMECMP0LO;
+    volatile uint32_t MTIMECMP0HI;
+    volatile uint32_t MTIME_LO;
+    volatile uint32_t MTIME_HI;
+}apb3aclint_t;
+
+inline uint32_t get_aclint_msip0(volatile apb3aclint_t *reg){
+    return (reg->MSIP0 >> 0) & 0x1;
+}
+inline void set_aclint_msip0(volatile apb3aclint_t *reg, uint8_t value){
+    reg->MSIP0 = (reg->MSIP0 & ~(0x1U << 0)) | (value << 0);
+}
+inline uint32_t get_aclint_mtimecmp0lo(volatile apb3aclint_t *reg){
+    return (reg->MTIMECMP0LO >> 0) & 0xffffffff;
+}
+inline void set_aclint_mtimecmp0lo(volatile apb3aclint_t *reg, uint32_t value){
+    reg->MTIMECMP0LO = (reg->MTIMECMP0LO & ~(0xffffffffU << 0)) | (value << 0);
+}
+inline uint32_t get_aclint_mtimecmp0hi(volatile apb3aclint_t *reg){
+    return (reg->MTIMECMP0HI >> 0) & 0xffffffff;
+}
+inline void set_aclint_mtimecmp0hi(volatile apb3aclint_t *reg, uint32_t value){
+    reg->MTIMECMP0HI = (reg->MTIMECMP0HI & ~(0xffffffffU << 0)) | (value << 0);
+}
+inline uint32_t get_aclint_mtime_lo(volatile apb3aclint_t *reg){
+    return (reg->MTIME_LO >> 0) & 0xffffffff;
+}
+inline void set_aclint_mtime_lo(volatile apb3aclint_t *reg, uint32_t value){
+    reg->MTIME_LO = (reg->MTIME_LO & ~(0xffffffffU << 0)) | (value << 0);
+}
+inline uint32_t get_aclint_mtime_hi(volatile apb3aclint_t *reg){
+    return (reg->MTIME_HI >> 0) & 0xffffffff;
+}
+inline void set_aclint_mtime_hi(volatile apb3aclint_t *reg, uint32_t value){
+    reg->MTIME_HI = (reg->MTIME_HI & ~(0xffffffffU << 0)) | (value << 0);
+}
+#endif /* _BSP_APB3ACLINT_H */

include/ehrenberg/devices/gen/Apb3Gpio.h

@@ -0,0 +1,36 @@
+/*
+* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Generated at 2024-02-19 14:24:37 UTC 
+* by peakrdl_mnrs version 1.2.2
+*/
+
+#ifndef _BSP_APB3GPIO_H
+#define _BSP_APB3GPIO_H
+
+#include <stdint.h>
+
+typedef struct __attribute((__packed__)) {
+    volatile uint32_t VALUE;
+    volatile uint32_t WRITE;
+    volatile uint32_t WRITEENABLE;
+}apb3gpio_t;
+
+inline uint32_t get_gpio_value(volatile apb3gpio_t *reg){
+    return (reg->VALUE >> 0) & 0xffffffff;
+}
+inline uint32_t get_gpio_write(volatile apb3gpio_t *reg){
+    return (reg->WRITE >> 0) & 0xffffffff;
+}
+inline void set_gpio_write(volatile apb3gpio_t *reg, uint32_t value){
+    reg->WRITE = (reg->WRITE & ~(0xffffffffU << 0)) | (value << 0);
+}
+inline uint32_t get_gpio_writeEnable(volatile apb3gpio_t *reg){
+    return (reg->WRITEENABLE >> 0) & 0xffffffff;
+}
+inline void set_gpio_writeEnable(volatile apb3gpio_t *reg, uint32_t value){
+    reg->WRITEENABLE = (reg->WRITEENABLE & ~(0xffffffffU << 0)) | (value << 0);
+}
+#endif /* _BSP_APB3GPIO_H */

include/ehrenberg/devices/gen/Apb3IrqCtrl.h

@@ -0,0 +1,32 @@
+/*
+* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Generated at 2024-02-19 14:24:37 UTC 
+* by peakrdl_mnrs version 1.2.2
+*/
+
+#ifndef _BSP_APB3IRQCTRL_H
+#define _BSP_APB3IRQCTRL_H
+
+#include <stdint.h>
+
+typedef struct __attribute((__packed__)) {
+    volatile uint32_t PENDINGSREG;
+    volatile uint32_t MASKSREG;
+}apb3irqctrl_t;
+
+inline uint32_t get_irq_pendingsReg(volatile apb3irqctrl_t *reg){
+    return (reg->PENDINGSREG >> 0) & 0xf;
+}
+inline void set_irq_pendingsReg(volatile apb3irqctrl_t *reg, uint8_t value){
+    reg->PENDINGSREG = (reg->PENDINGSREG & ~(0xfU << 0)) | (value << 0);
+}
+inline uint32_t get_irq_masksReg(volatile apb3irqctrl_t *reg){
+    return (reg->MASKSREG >> 0) & 0xf;
+}
+inline void set_irq_masksReg(volatile apb3irqctrl_t *reg, uint8_t value){
+    reg->MASKSREG = (reg->MASKSREG & ~(0xfU << 0)) | (value << 0);
+}
+#endif /* _BSP_APB3IRQCTRL_H */

include/ehrenberg/devices/gen/Apb3SpiXdrMasterCtrl.h

@@ -0,0 +1,189 @@
+/*
+* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Generated at 2024-02-19 14:24:37 UTC 
+* by peakrdl_mnrs version 1.2.2
+*/
+
+#ifndef _BSP_APB3SPIXDRMASTERCTRL_H
+#define _BSP_APB3SPIXDRMASTERCTRL_H
+
+#include <stdint.h>
+
+typedef struct __attribute((__packed__)) {
+    volatile uint32_t DATA;
+    volatile uint32_t STATUS;
+    volatile uint32_t CONFIG;
+    volatile uint32_t INTR;
+    volatile uint32_t SCLK_CONFIG;
+    volatile uint32_t SSGEN_SETUP;
+    volatile uint32_t SSGEN_HOLD;
+    volatile uint32_t SSGEN_DISABLE;
+    volatile uint32_t SSGEN_ACTIVE_HIGH;
+    volatile uint32_t XIP_ENABLE;
+    volatile uint32_t XIP_CONFIG;
+    volatile uint32_t XIP_MODE;
+    volatile uint32_t XIP_WRITE;
+    volatile uint32_t XIP_READ_WRITE;
+    volatile uint32_t XIP_READ;
+}apb3spixdrmasterctrl_t;
+
+inline void set_spi_data_data(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
+    reg->DATA = (reg->DATA & ~(0xffU << 0)) | (value << 0);
+}
+inline uint32_t get_spi_data_write(volatile apb3spixdrmasterctrl_t *reg){
+    return (reg->DATA >> 8) & 0x1;
+}
+inline void set_spi_data_write(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
+    reg->DATA = (reg->DATA & ~(0x1U << 8)) | (value << 8);
+}
+inline uint32_t get_spi_data_read(volatile apb3spixdrmasterctrl_t *reg){
+    return (reg->DATA >> 9) & 0x1;
+}
+inline void set_spi_data_read(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
+    reg->DATA = (reg->DATA & ~(0x1U << 9)) | (value << 9);
+}
+inline uint32_t get_spi_data_kind(volatile apb3spixdrmasterctrl_t *reg){
+    return (reg->DATA >> 11) & 0x1;
+}
+inline void set_spi_data_kind(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
+    reg->DATA = (reg->DATA & ~(0x1U << 11)) | (value << 11);
+}
+inline uint32_t get_spi_data_rx_data_invalid(volatile apb3spixdrmasterctrl_t *reg){
+    return (reg->DATA >> 31) & 0x1;
+}
+inline uint32_t get_spi_status_tx_free(volatile apb3spixdrmasterctrl_t *reg){
+    return (reg->STATUS >> 0) & 0x3f;
+}
+inline uint32_t get_spi_status_rx_avail(volatile apb3spixdrmasterctrl_t *reg){
+    return (reg->STATUS >> 16) & 0x3f;
+}
+inline uint32_t get_spi_config_kind(volatile apb3spixdrmasterctrl_t *reg){
+    return (reg->CONFIG >> 0) & 0x3;
+}
+inline void set_spi_config_kind(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
+    reg->CONFIG = (reg->CONFIG & ~(0x3U << 0)) | (value << 0);
+}
+inline uint32_t get_spi_config_mode(volatile apb3spixdrmasterctrl_t *reg){
+    return (reg->CONFIG >> 4) & 0x7;
+}
+inline void set_spi_config_mode(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
+    reg->CONFIG = (reg->CONFIG & ~(0x7U << 4)) | (value << 4);
+}
+inline uint32_t get_spi_intr_tx_ie(volatile apb3spixdrmasterctrl_t *reg){
+    return (reg->INTR >> 0) & 0x1;
+}
+inline void set_spi_intr_tx_ie(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
+    reg->INTR = (reg->INTR & ~(0x1U << 0)) | (value << 0);
+}
+inline uint32_t get_spi_intr_rx_ie(volatile apb3spixdrmasterctrl_t *reg){
+    return (reg->INTR >> 1) & 0x1;
+}
+inline void set_spi_intr_rx_ie(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
+    reg->INTR = (reg->INTR & ~(0x1U << 1)) | (value << 1);
+}
+inline uint32_t get_spi_intr_tx_ip(volatile apb3spixdrmasterctrl_t *reg){
+    return (reg->INTR >> 8) & 0x1;
+}
+inline uint32_t get_spi_intr_rx_ip(volatile apb3spixdrmasterctrl_t *reg){
+    return (reg->INTR >> 9) & 0x1;
+}
+inline uint32_t get_spi_intr_tx_active(volatile apb3spixdrmasterctrl_t *reg){
+    return (reg->INTR >> 16) & 0x1;
+}
+inline uint32_t get_spi_sclk_config(volatile apb3spixdrmasterctrl_t *reg){
+    return (reg->SCLK_CONFIG >> 0) & 0xfff;
+}
+inline void set_spi_sclk_config(volatile apb3spixdrmasterctrl_t *reg, uint16_t value){
+    reg->SCLK_CONFIG = (reg->SCLK_CONFIG & ~(0xfffU << 0)) | (value << 0);
+}
+inline uint32_t get_spi_ssgen_setup(volatile apb3spixdrmasterctrl_t *reg){
+    return (reg->SSGEN_SETUP >> 0) & 0xfff;
+}
+inline void set_spi_ssgen_setup(volatile apb3spixdrmasterctrl_t *reg, uint16_t value){
+    reg->SSGEN_SETUP = (reg->SSGEN_SETUP & ~(0xfffU << 0)) | (value << 0);
+}
+inline uint32_t get_spi_ssgen_hold(volatile apb3spixdrmasterctrl_t *reg){
+    return (reg->SSGEN_HOLD >> 0) & 0xfff;
+}
+inline void set_spi_ssgen_hold(volatile apb3spixdrmasterctrl_t *reg, uint16_t value){
+    reg->SSGEN_HOLD = (reg->SSGEN_HOLD & ~(0xfffU << 0)) | (value << 0);
+}
+inline uint32_t get_spi_ssgen_disable(volatile apb3spixdrmasterctrl_t *reg){
+    return (reg->SSGEN_DISABLE >> 0) & 0xfff;
+}
+inline void set_spi_ssgen_disable(volatile apb3spixdrmasterctrl_t *reg, uint16_t value){
+    reg->SSGEN_DISABLE = (reg->SSGEN_DISABLE & ~(0xfffU << 0)) | (value << 0);
+}
+inline uint32_t get_spi_ssgen_active_high(volatile apb3spixdrmasterctrl_t *reg){
+    return (reg->SSGEN_ACTIVE_HIGH >> 0) & 0x1;
+}
+inline void set_spi_ssgen_active_high(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
+    reg->SSGEN_ACTIVE_HIGH = (reg->SSGEN_ACTIVE_HIGH & ~(0x1U << 0)) | (value << 0);
+}
+inline uint32_t get_spi_xip_enable(volatile apb3spixdrmasterctrl_t *reg){
+    return (reg->XIP_ENABLE >> 0) & 0x1;
+}
+inline void set_spi_xip_enable(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
+    reg->XIP_ENABLE = (reg->XIP_ENABLE & ~(0x1U << 0)) | (value << 0);
+}
+inline uint32_t get_spi_xip_config_instruction(volatile apb3spixdrmasterctrl_t *reg){
+    return (reg->XIP_CONFIG >> 0) & 0xff;
+}
+inline void set_spi_xip_config_instruction(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
+    reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 0)) | (value << 0);
+}
+inline uint32_t get_spi_xip_config_enable(volatile apb3spixdrmasterctrl_t *reg){
+    return (reg->XIP_CONFIG >> 8) & 0x1;
+}
+inline void set_spi_xip_config_enable(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
+    reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0x1U << 8)) | (value << 8);
+}
+inline uint32_t get_spi_xip_config_dummy_value(volatile apb3spixdrmasterctrl_t *reg){
+    return (reg->XIP_CONFIG >> 16) & 0xff;
+}
+inline void set_spi_xip_config_dummy_value(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
+    reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 16)) | (value << 16);
+}
+inline uint32_t get_spi_xip_config_dummy_count(volatile apb3spixdrmasterctrl_t *reg){
+    return (reg->XIP_CONFIG >> 24) & 0xf;
+}
+inline void set_spi_xip_config_dummy_count(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
+    reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xfU << 24)) | (value << 24);
+}
+inline uint32_t get_spi_xip_mode_instruction(volatile apb3spixdrmasterctrl_t *reg){
+    return (reg->XIP_MODE >> 0) & 0x7;
+}
+inline void set_spi_xip_mode_instruction(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
+    reg->XIP_MODE = (reg->XIP_MODE & ~(0x7U << 0)) | (value << 0);
+}
+inline uint32_t get_spi_xip_mode_address(volatile apb3spixdrmasterctrl_t *reg){
+    return (reg->XIP_MODE >> 8) & 0x7;
+}
+inline void set_spi_xip_mode_address(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
+    reg->XIP_MODE = (reg->XIP_MODE & ~(0x7U << 8)) | (value << 8);
+}
+inline uint32_t get_spi_xip_mode_dummy(volatile apb3spixdrmasterctrl_t *reg){
+    return (reg->XIP_MODE >> 16) & 0x7;
+}
+inline void set_spi_xip_mode_dummy(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
+    reg->XIP_MODE = (reg->XIP_MODE & ~(0x7U << 16)) | (value << 16);
+}
+inline uint32_t get_spi_xip_mode_payload(volatile apb3spixdrmasterctrl_t *reg){
+    return (reg->XIP_MODE >> 24) & 0x7;
+}
+inline void set_spi_xip_mode_payload(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
+    reg->XIP_MODE = (reg->XIP_MODE & ~(0x7U << 24)) | (value << 24);
+}
+inline void set_spi_xip_write(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
+    reg->XIP_WRITE = (reg->XIP_WRITE & ~(0xffU << 0)) | (value << 0);
+}
+inline void set_spi_xip_read_write(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
+    reg->XIP_READ_WRITE = (reg->XIP_READ_WRITE & ~(0xffU << 0)) | (value << 0);
+}
+inline uint32_t get_spi_xip_read(volatile apb3spixdrmasterctrl_t *reg){
+    return (reg->XIP_READ >> 0) & 0xff;
+}
+#endif /* _BSP_APB3SPIXDRMASTERCTRL_H */

include/ehrenberg/devices/gen/Apb3Timer.h

@@ -0,0 +1,73 @@
+/*
+* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Generated at 2024-02-19 14:24:37 UTC 
+* by peakrdl_mnrs version 1.2.2
+*/
+
+#ifndef _BSP_APB3TIMER_H
+#define _BSP_APB3TIMER_H
+
+#include <stdint.h>
+
+typedef struct __attribute((__packed__)) {
+    volatile uint32_t PRESCALER;
+    volatile uint32_t T0_CTRL;
+    volatile uint32_t T0_OVERFLOW;
+    volatile uint32_t T0_VALUE;
+    volatile uint32_t T1_CTRL;
+    volatile uint32_t T1_OVERFLOW;
+    volatile uint32_t T1_VALUE;
+}apb3timer_t;
+
+inline uint32_t get_timer_prescaler(volatile apb3timer_t *reg){
+    return (reg->PRESCALER >> 0) & 0xffff;
+}
+inline void set_timer_prescaler(volatile apb3timer_t *reg, uint16_t value){
+    reg->PRESCALER = (reg->PRESCALER & ~(0xffffU << 0)) | (value << 0);
+}
+inline uint32_t get_timer_t0_ctrl_enable(volatile apb3timer_t *reg){
+    return (reg->T0_CTRL >> 0) & 0x7;
+}
+inline void set_timer_t0_ctrl_enable(volatile apb3timer_t *reg, uint8_t value){
+    reg->T0_CTRL = (reg->T0_CTRL & ~(0x7U << 0)) | (value << 0);
+}
+inline uint32_t get_timer_t0_ctrl_clear(volatile apb3timer_t *reg){
+    return (reg->T0_CTRL >> 3) & 0x3;
+}
+inline void set_timer_t0_ctrl_clear(volatile apb3timer_t *reg, uint8_t value){
+    reg->T0_CTRL = (reg->T0_CTRL & ~(0x3U << 3)) | (value << 3);
+}
+inline uint32_t get_timer_t0_overflow(volatile apb3timer_t *reg){
+    return (reg->T0_OVERFLOW >> 0) & 0xffffffff;
+}
+inline void set_timer_t0_overflow(volatile apb3timer_t *reg, uint32_t value){
+    reg->T0_OVERFLOW = (reg->T0_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0);
+}
+inline uint32_t get_timer_t0_value(volatile apb3timer_t *reg){
+    return (reg->T0_VALUE >> 0) & 0xffffffff;
+}
+inline uint32_t get_timer_t1_ctrl_enable(volatile apb3timer_t *reg){
+    return (reg->T1_CTRL >> 0) & 0x7;
+}
+inline void set_timer_t1_ctrl_enable(volatile apb3timer_t *reg, uint8_t value){
+    reg->T1_CTRL = (reg->T1_CTRL & ~(0x7U << 0)) | (value << 0);
+}
+inline uint32_t get_timer_t1_ctrl_clear(volatile apb3timer_t *reg){
+    return (reg->T1_CTRL >> 3) & 0x3;
+}
+inline void set_timer_t1_ctrl_clear(volatile apb3timer_t *reg, uint8_t value){
+    reg->T1_CTRL = (reg->T1_CTRL & ~(0x3U << 3)) | (value << 3);
+}
+inline uint32_t get_timer_t1_overflow(volatile apb3timer_t *reg){
+    return (reg->T1_OVERFLOW >> 0) & 0xffffffff;
+}
+inline void set_timer_t1_overflow(volatile apb3timer_t *reg, uint32_t value){
+    reg->T1_OVERFLOW = (reg->T1_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0);
+}
+inline uint32_t get_timer_t1_value(volatile apb3timer_t *reg){
+    return (reg->T1_VALUE >> 0) & 0xffffffff;
+}
+#endif /* _BSP_APB3TIMER_H */

include/ehrenberg/devices/gen/Apb3Uart.h

@@ -0,0 +1,104 @@
+/*
+* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Generated at 2024-02-19 14:24:37 UTC 
+* by peakrdl_mnrs version 1.2.2
+*/
+
+#ifndef _BSP_APB3UART_H
+#define _BSP_APB3UART_H
+
+#include <stdint.h>
+
+typedef struct __attribute((__packed__)) {
+    volatile uint32_t RX_TX_REG;
+    volatile uint32_t INT_CTRL_REG;
+    volatile uint32_t CLK_DIVIDER_REG;
+    volatile uint32_t FRAME_CONFIG_REG;
+    volatile uint32_t STATUS_REG;
+}apb3uart_t;
+
+inline uint32_t get_uart_rx_tx_reg_data(volatile apb3uart_t *reg){
+    return (reg->RX_TX_REG >> 0) & 0xff;
+}
+inline void set_uart_rx_tx_reg_data(volatile apb3uart_t *reg, uint8_t value){
+    reg->RX_TX_REG = (reg->RX_TX_REG & ~(0xffU << 0)) | (value << 0);
+}
+inline uint32_t get_uart_rx_tx_reg_rx_avail(volatile apb3uart_t *reg){
+    return (reg->RX_TX_REG >> 14) & 0x1;
+}
+inline uint32_t get_uart_rx_tx_reg_tx_free(volatile apb3uart_t *reg){
+    return (reg->RX_TX_REG >> 15) & 0x1;
+}
+inline uint32_t get_uart_int_ctrl_reg_write_intr_enable(volatile apb3uart_t *reg){
+    return (reg->INT_CTRL_REG >> 0) & 0x1;
+}
+inline void set_uart_int_ctrl_reg_write_intr_enable(volatile apb3uart_t *reg, uint8_t value){
+    reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 0)) | (value << 0);
+}
+inline uint32_t get_uart_int_ctrl_reg_read_intr_enable(volatile apb3uart_t *reg){
+    return (reg->INT_CTRL_REG >> 1) & 0x1;
+}
+inline void set_uart_int_ctrl_reg_read_intr_enable(volatile apb3uart_t *reg, uint8_t value){
+    reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 1)) | (value << 1);
+}
+inline uint32_t get_uart_int_ctrl_reg_write_intr_pend(volatile apb3uart_t *reg){
+    return (reg->INT_CTRL_REG >> 8) & 0x1;
+}
+inline uint32_t get_uart_int_ctrl_reg_read_intr_pend(volatile apb3uart_t *reg){
+    return (reg->INT_CTRL_REG >> 9) & 0x1;
+}
+inline uint32_t get_uart_clk_divider_reg(volatile apb3uart_t *reg){
+    return (reg->CLK_DIVIDER_REG >> 0) & 0xfffff;
+}
+inline void set_uart_clk_divider_reg(volatile apb3uart_t *reg, uint32_t value){
+    reg->CLK_DIVIDER_REG = (reg->CLK_DIVIDER_REG & ~(0xfffffU << 0)) | (value << 0);
+}
+inline uint32_t get_uart_frame_config_reg_data_lenght(volatile apb3uart_t *reg){
+    return (reg->FRAME_CONFIG_REG >> 0) & 0x7;
+}
+inline void set_uart_frame_config_reg_data_lenght(volatile apb3uart_t *reg, uint8_t value){
+    reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x7U << 0)) | (value << 0);
+}
+inline uint32_t get_uart_frame_config_reg_parity(volatile apb3uart_t *reg){
+    return (reg->FRAME_CONFIG_REG >> 3) & 0x3;
+}
+inline void set_uart_frame_config_reg_parity(volatile apb3uart_t *reg, uint8_t value){
+    reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x3U << 3)) | (value << 3);
+}
+inline uint32_t get_uart_frame_config_reg_stop_bit(volatile apb3uart_t *reg){
+    return (reg->FRAME_CONFIG_REG >> 5) & 0x1;
+}
+inline void set_uart_frame_config_reg_stop_bit(volatile apb3uart_t *reg, uint8_t value){
+    reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x1U << 5)) | (value << 5);
+}
+inline uint32_t get_uart_status_reg_read_error(volatile apb3uart_t *reg){
+    return (reg->STATUS_REG >> 0) & 0x1;
+}
+inline uint32_t get_uart_status_reg_stall(volatile apb3uart_t *reg){
+    return (reg->STATUS_REG >> 1) & 0x1;
+}
+inline uint32_t get_uart_status_reg_break(volatile apb3uart_t *reg){
+    return (reg->STATUS_REG >> 8) & 0x1;
+}
+inline uint32_t get_uart_status_reg_break_detected(volatile apb3uart_t *reg){
+    return (reg->STATUS_REG >> 9) & 0x1;
+}
+inline void set_uart_status_reg_break_detected(volatile apb3uart_t *reg, uint8_t value){
+    reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 9)) | (value << 9);
+}
+inline uint32_t get_uart_status_reg_set_break(volatile apb3uart_t *reg){
+    return (reg->STATUS_REG >> 10) & 0x1;
+}
+inline void set_uart_status_reg_set_break(volatile apb3uart_t *reg, uint8_t value){
+    reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 10)) | (value << 10);
+}
+inline uint32_t get_uart_status_reg_clear_break(volatile apb3uart_t *reg){
+    return (reg->STATUS_REG >> 11) & 0x1;
+}
+inline void set_uart_status_reg_clear_break(volatile apb3uart_t *reg, uint8_t value){
+    reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 11)) | (value << 11);
+}
+#endif /* _BSP_APB3UART_H */

include/ehrenberg/devices/gpio.h

@@ -2,16 +2,13 @@
 #define _BSP_GPIO_H
 
 #include <stdint.h>
+#include "gen/Apb3Gpio.h"
 
-typedef struct __attribute((__packed__)) {
+#define gpio_t apb3gpio_t
-    volatile uint32_t pin_in;
-    volatile uint32_t pin_out;
-    volatile uint32_t out_en;
-} gpio_t;
 
 inline void gpio_init(gpio_t* reg) {
-    reg->out_en=0;
+    set_gpio_write(reg, 0);
-    reg->pin_out=0;
+    set_gpio_writeEnable(reg, 0);
 }
 
 #endif /* _BSP_GPIO_H */

include/ehrenberg/devices/interrupt.h

@@ -2,15 +2,13 @@
 #define _BSP_INTERRUPT_H
 
 #include <stdint.h>
+#include "gen/Apb3IrqCtrl.h"
 
-typedef struct __attribute((__packed__)) {
+#define irq_t apb3irqctrl_t
-    volatile uint32_t ip;
-    volatile uint32_t ie;
-} irq_t;
 
 inline void irq_init(irq_t* reg){
-    reg->ie = 0;
+    set_irq_masksReg(reg, 0);
-    reg->ip = 0xFFFFFFFF;
+    set_irq_pendingsReg(reg, 0xff);
 }
 
 #endif /* _BSP_INTERRUPT_H */

include/ehrenberg/devices/qspi.h

@@ -2,31 +2,9 @@
 #define _BSP_QSPI_H
 
 #include <stdint.h>
+#include "gen/Apb3SpiXdrMasterCtrl.h"
 
-#define __IO volatile
+#define qspi_t apb3spixdrmasterctrl_t
-
-typedef struct {
-    __IO uint32_t data;             // 0x0/0: data, 8bits, 8:write, 9:read, 11:data/ctrl, 31:rxdata valid
-    __IO uint32_t status;           // 0x4/0: txavail, 16: rxused
-    __IO uint32_t config;           // 0x8/0:1 cpol/cpha, 4: transfer mode (0-FullDuplex)
-    __IO uint32_t intr;             // 0xc/0: txien, 1: rxien, 8: txip, 9: rxip, 16: valid?
-    __IO uint32_t __fill0[4];
-    __IO uint32_t clk_divider;      // 0x20/0: sclkToogle
-    // ssGen config
-    __IO uint32_t ss_setup;         // 0x24/0: setup
-    __IO uint32_t ss_hold;          // 0x28/0: hold
-    __IO uint32_t ss_disable;       // 0x2c/0: disable
-    __IO uint32_t ss_activeHigh;    // 0x30/0: disable
-    __IO uint32_t __fill1[3];
-    __IO uint32_t xip_enable;       // 0x40/0: enable
-    __IO uint32_t xip_instr;        // 0x44/0:7 data, 8: enable, 16:23 dummy data, 24:27 dummy count
-    __IO uint32_t xip_mode;         // 0x48/0: instr transfer mode, 8: addr transfer mode, 16: dummy transfer mode, 24: data transfer mode
-    __IO uint32_t __fill2[2];
-    __IO uint32_t xip_write32;      // 0x50
-    __IO uint32_t xip_readwrite32;  // 0x54
-    __IO uint32_t xip_read32;       // 0x58
-}  __attribute((__packed__)) qspi_t;
-
 typedef struct {
     uint32_t cpol;
     uint32_t cpha;

include/ehrenberg/devices/timer.h

@@ -2,51 +2,20 @@
 #define _BSP_TIMER_H
 
 #include <stdint.h>
+#include "gen/Apb3Timer.h"
 
-typedef struct __attribute((__packed__)) {
+#define timer_t apb3timer_t
-    volatile uint32_t mtime;     // 0x0:0
-    volatile uint32_t mtimeh;    // 0x4:0
-    volatile uint32_t mtimecmp;  // 0x8:0
-    volatile uint32_t mtimecmph; // 0xc:0
-} mtimer_t;
 
-#ifndef APB_BUS
+inline void prescaler_init(timer_t* reg, uint16_t value){
-typedef struct __attribute((__packed__)) {
+    set_timer_prescaler(reg, value);
-    volatile uint16_t count;
-} prescaler_t;
-
-typedef struct __attribute((__packed__)) {
-    volatile uint16_t clk_en;      // 0x0:0, 0->always, 1->prescaler
-    volatile uint16_t clr_en;      // 0x2:0, 0->on overflow
-    volatile uint32_t limit;       // 0x4:0, upper limit of counter
-    volatile uint32_t timer_value; // 0x8:0 current timer value
-} timer_a_t;
-
-#else
-
-typedef struct __attribute((__packed__)) {
-  volatile uint32_t LIMIT;
-} prescaler_t;
-
-typedef struct __attribute((__packed__)) {
-  volatile uint32_t CLEARS_TICKS;   // 0x0/0:0->always, 1->prescaler; 16:0->on overflow
-  volatile uint32_t LIMIT;          // 0x4/0 upper limit of counter
-  volatile uint32_t VALUE;          // 0x8/0 current timer value
-} timer_a_t;
-
-inline void prescaler_init(prescaler_t* reg){
-    (void)reg;
 }
 
-inline void timer_init(timer_a_t *reg){
+inline void timer_t0__init(timer_t *reg){
-    reg->CLEARS_TICKS  = 0;
+    set_timer_t0_overflow(reg, 0xffffffff);
-    reg->VALUE = 0;
 }
 
-inline void mtimer_init(mtimer_t *reg){
+inline void timer_t1__init(timer_t *reg){
-    reg->mtimecmph  = UINT32_MAX;
+    set_timer_t1_overflow(reg, 0xffffffff);
-    reg->mtimecmp = UINT32_MAX;
 }
 
-#endif
 #endif /* _BSP_TIMER_H */

include/ehrenberg/devices/uart.h

@@ -2,66 +2,19 @@
 #define _BSP_UART_H
 
 #include <stdint.h>
+#include "gen/Apb3Uart.h"
 
-enum uart_parity_e {NONE = 0, EVEN = 1, ODD = 2};
+#define uart_t apb3uart_t
-enum uart_stop_e   {ONE = 0, TWO = 1};
-
-#ifndef APB_BUS
-typedef struct __attribute((__packed__)){
-    // 0x0
-    volatile uint16_t rx_tx_reg; // 8bit, 0x0
-    volatile uint16_t rx_avail;  // 1bit, 0x0:16
-    // 0x4
-    volatile uint16_t irq_ctrl; // 0->tx_ie, 1->rx_ie, 8->tx_ip, 9->rx_ip
-    volatile uint8_t num_tx_avail; // 8bit, 0x4:16
-    volatile uint8_t num_rx_avail; // 8bit, 0x4:24
-    volatile uint32_t dummy;
-    // 0xc
-    volatile uint8_t clock_div;  // 3bit, 0xc:0
-    volatile uint8_t frame;     // 2bit, 0xc:8
-    volatile uint8_t stop_bits; // 1bit, 0xc:16
-    // 0x10
-    volatile uint8_t status; // readError->0, readOverflowError->1,
-    volatile uint8_t active; // rx_active->0, tx_active-1, set_tx_active->2, clear_tx_active->3
-} uart_t;
-#else
-typedef struct __attribute((__packed__)) {
-  volatile uint32_t DATA;
-  volatile uint32_t STATUS;
-  volatile uint32_t CLOCK_DIVIDER;
-  volatile uint32_t FRAME_CONFIG;
-} uart_t;
-
-
-typedef struct __attribute((__packed__)) {
-    uint32_t data_length;
-    enum uart_parity_e parity;
-    enum uart_stop_e stop;
-    uint32_t clock_divider;
-} uart_config_t;
-
-static inline uint32_t uart_get_tx_free(volatile uart_t *reg){
-    return (reg->STATUS >> 16) & 0xFF;
-}
-
-static inline uint32_t uart_get_rx_avail(volatile uart_t *reg){
-    return reg->STATUS >> 24;
-}
 
 static void uart_write(volatile uart_t *reg, uint8_t data){
-    while(uart_get_tx_free(reg) == 0);
+    while(get_uart_rx_tx_reg_tx_free(reg) == 0);
-    reg->DATA = data;
+    set_uart_rx_tx_reg_data(reg, data);
 }
 
 static inline uint8_t uart_read(volatile uart_t *reg){
-    uint32_t res = reg->DATA;
+    uint32_t res = get_uart_rx_tx_reg_data(reg);
-    while((res&0x10000) == 0) res = reg->DATA;
+    while((res&0x10000) == 0) res = get_uart_rx_tx_reg_data(reg);
     return res;
 }
 
-static inline void uart_set_config(volatile uart_t *reg, uart_config_t *config){
-    reg->CLOCK_DIVIDER = config->clock_divider;
-    reg->FRAME_CONFIG = ((config->data_length-1) << 0) | (config->parity << 8) | (config->stop << 16);
-}
-#endif
 #endif /* _BSP_UART_H */