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fixes rve settings

This commit is contained in:
Eyck Jentzsch 2024-03-21 07:23:21 +01:00
parent 4d25972e4d
commit 3389875643
2 changed files with 3 additions and 3 deletions
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2
env/common-gcc.mk vendored
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@ -2,6 +2,7 @@ ifndef _MK_COMMON
_MK_COMMON := # defined _MK_COMMON := # defined
TL_TARGET?=all TL_TARGET?=all
BOARD?=iss
.PHONY: $(TL_TARGET) .PHONY: $(TL_TARGET)
$(TL_TARGET): $(TARGET) $(TL_TARGET): $(TARGET)
@ -12,7 +13,6 @@ PLATFORM_DIR = $(ENV_DIR)/$(BOARD)
include $(BSP_BASE)/libwrap/libwrap.mk include $(BSP_BASE)/libwrap/libwrap.mk
BOARD?=iss
ASM_SRCS += $(ENV_DIR)/start.S $(ENV_DIR)/entry.S ASM_SRCS += $(ENV_DIR)/start.S $(ENV_DIR)/entry.S
C_SRCS += $(PLATFORM_DIR)/init.c C_SRCS += $(PLATFORM_DIR)/init.c

4
env/entry.S vendored
View File

@ -10,7 +10,7 @@
.align 2 .align 2
.global trap_entry .global trap_entry
trap_entry: trap_entry:
#ifndef __riscv_abi_rve #ifdef __riscv_abi_rve
addi sp, sp, -8*REGBYTES addi sp, sp, -8*REGBYTES
STORE x1, 1*REGBYTES(sp) // ra STORE x1, 1*REGBYTES(sp) // ra
STORE x5, 2*REGBYTES(sp) // t0 STORE x5, 2*REGBYTES(sp) // t0
@ -43,7 +43,7 @@ trap_entry:
mv a2, sp mv a2, sp
call handle_trap call handle_trap
csrw mepc, a0 csrw mepc, a0
#ifndef __riscv_abi_rve #ifdef __riscv_abi_rve
addi sp, sp, -8*REGBYTES addi sp, sp, -8*REGBYTES
LOAD x1, 1*REGBYTES(sp) // ra LOAD x1, 1*REGBYTES(sp) // ra
LOAD x5, 2*REGBYTES(sp) // t0 LOAD x5, 2*REGBYTES(sp) // t0