Firmware/MNRS-BM-BSP
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Update cluster_info header

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This commit is contained in:
Johannes Wirth
2025-04-08 21:40:46 +02:00
parent aca6bc8a20
commit 263d7d9074
1 changed files with 48 additions and 1 deletions
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49
include/ehrenberg/devices/fki_cluster_info.h
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@@ -1,4 +1,3 @@
#pragma once
#ifndef _FKI_CLUSTER_INFO_H
#define _FKI_CLUSTER_INFO_H
@@ -28,17 +27,41 @@ static uint64_t fki_addr_sram3(uint8_t cluster);
#define Compute0_dma 2,4
#define Compute0_dma_adapter 2,5
#define ADDR_Compute0_ccc_idxJobs 0x80004000
#define BYTES_Compute0_ccc_idxJobs 4096
#define HIGH_Compute0_ccc_idxJobs 0x80004fff
#define ADDR_Compute0_ccc_idxTasks 0x80005000
#define BYTES_Compute0_ccc_idxTasks 4096
#define HIGH_Compute0_ccc_idxTasks 0x80005fff
#define ADDR_Compute0_ccc_configMem 0x80000000
#define BYTES_Compute0_ccc_configMem 16384
#define HIGH_Compute0_ccc_configMem 0x80003fff
#define ADDR_Compute0_ccc_peMapping 0x80006000
#define BYTES_Compute0_ccc_peMapping 4096
#define HIGH_Compute0_ccc_peMapping 0x80006fff
#define ADDR_Compute0_aes_adapter 0x80007000
#define BYTES_Compute0_aes_adapter 4096
#define HIGH_Compute0_aes_adapter 0x80007fff
#define ADDR_Compute0_cntrl_cva5 0x80008000
#define BYTES_Compute0_cntrl_cva5 16384
#define HIGH_Compute0_cntrl_cva5 0x8000bfff
#define ADDR_Compute0_cntrl_tgc 0x8000c000
#define BYTES_Compute0_cntrl_tgc 16384
#define HIGH_Compute0_cntrl_tgc 0x8000ffff
#define ADDR_Compute0_ut_adapter 0x80010000
#define BYTES_Compute0_ut_adapter 4096
#define HIGH_Compute0_ut_adapter 0x80010fff
#define ADDR_Compute0_sram0 0x80011000
#define BYTES_Compute0_sram0 524288
#define HIGH_Compute0_sram0 0x80090fff
#define ADDR_Compute0_sram1 0x80091000
#define BYTES_Compute0_sram1 262144
#define HIGH_Compute0_sram1 0x800d0fff
#define ADDR_Compute0_sram2 0x800d1000
#define BYTES_Compute0_sram2 262144
#define HIGH_Compute0_sram2 0x80110fff
#define ADDR_Compute0_sram3 0x80111000
#define BYTES_Compute0_sram3 262144
#define HIGH_Compute0_sram3 0x80150fff
#define Compute1 3
#define Compute1_ccc 3,0
#define Compute1_stream2axi 3,1
@@ -46,17 +69,41 @@ static uint64_t fki_addr_sram3(uint8_t cluster);
#define Compute1_dma 3,4
#define Compute1_dma_adapter 3,5
#define ADDR_Compute1_ccc_idxJobs 0x90004000
#define BYTES_Compute1_ccc_idxJobs 4096
#define HIGH_Compute1_ccc_idxJobs 0x90004fff
#define ADDR_Compute1_ccc_idxTasks 0x90005000
#define BYTES_Compute1_ccc_idxTasks 4096
#define HIGH_Compute1_ccc_idxTasks 0x90005fff
#define ADDR_Compute1_ccc_configMem 0x90000000
#define BYTES_Compute1_ccc_configMem 16384
#define HIGH_Compute1_ccc_configMem 0x90003fff
#define ADDR_Compute1_ccc_peMapping 0x90006000
#define BYTES_Compute1_ccc_peMapping 4096
#define HIGH_Compute1_ccc_peMapping 0x90006fff
#define ADDR_Compute1_aes_adapter 0x90007000
#define BYTES_Compute1_aes_adapter 4096
#define HIGH_Compute1_aes_adapter 0x90007fff
#define ADDR_Compute1_cntrl_cva5 0x90008000
#define BYTES_Compute1_cntrl_cva5 16384
#define HIGH_Compute1_cntrl_cva5 0x9000bfff
#define ADDR_Compute1_cntrl_tgc 0x9000c000
#define BYTES_Compute1_cntrl_tgc 16384
#define HIGH_Compute1_cntrl_tgc 0x9000ffff
#define ADDR_Compute1_ut_adapter 0x90010000
#define BYTES_Compute1_ut_adapter 4096
#define HIGH_Compute1_ut_adapter 0x90010fff
#define ADDR_Compute1_sram0 0x90011000
#define BYTES_Compute1_sram0 524288
#define HIGH_Compute1_sram0 0x90090fff
#define ADDR_Compute1_sram1 0x90091000
#define BYTES_Compute1_sram1 262144
#define HIGH_Compute1_sram1 0x900d0fff
#define ADDR_Compute1_sram2 0x900d1000
#define BYTES_Compute1_sram2 262144
#define HIGH_Compute1_sram2 0x90110fff
#define ADDR_Compute1_sram3 0x90111000
#define BYTES_Compute1_sram3 262144
#define HIGH_Compute1_sram3 0x90150fff
static uint8_t fki_ccc(uint8_t cluster) {
switch(cluster) {