Initial version

FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/pin_mux.c

@@ -0,0 +1,65 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ * 
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v3.0
+processor: RV32M1
+package_id: RV32M1
+mcu_data: ksdk2_0
+processor_version: 0.0.0
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_port.h"
+#include "pin_mux.h"
+
+/*FUNCTION**********************************************************************
+ * 
+ * Function Name : BOARD_InitBootPins
+ * Description   : Calls initialization functions.
+ * 
+ *END**************************************************************************/
+void BOARD_InitBootPins(void) {
+    BOARD_InitPins();
+}
+
+#define PIN7_IDX                         7u   /*!< Pin number for pin 7 in a port */
+#define PIN8_IDX                         8u   /*!< Pin number for pin 8 in a port */
+#define PIN24_IDX                       24u   /*!< Pin number for pin 24 in a port */
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: cm4, enableClock: 'true'}
+- pin_list:
+  - {pin_num: D6, peripheral: GPIOA, signal: 'GPIO, 24', pin_signal: PTA24/LPSPI2_PCS0/LPSPI1_SCK/LPI2C2_SCL/FB_OE_b/TPM2_CH0}
+  - {pin_num: N2, peripheral: LPUART0, signal: RX, pin_signal: LPCMP0_IN0/PTC7/LLWU_P15/LPSPI0_PCS3/LPUART0_RX/LPI2C1_HREQ/TPM0_CH0/LPTMR1_ALT1}
+  - {pin_num: P3, peripheral: LPUART0, signal: TX, pin_signal: LPCMP0_IN1/PTC8/LPSPI0_SCK/LPUART0_TX/LPI2C0_HREQ/TPM0_CH1}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description   : Configures pin routing and optionally pin electrical features.
+ *
+ *END**************************************************************************/
+void BOARD_InitPins(void) {
+  CLOCK_EnableClock(kCLOCK_PortA);                           /* Clock Gate Control: 0x01u */
+  CLOCK_EnableClock(kCLOCK_PortC);                           /* Clock Gate Control: 0x01u */
+
+  PORT_SetPinMux(PORTA, PIN24_IDX, kPORT_MuxAsGpio);         /* PORTA24 (pin D6) is configured as PTA24 */
+  PORT_SetPinMux(PORTC, PIN7_IDX, kPORT_MuxAlt3);            /* PORTC7 (pin N2) is configured as LPUART0_RX */
+  PORT_SetPinMux(PORTC, PIN8_IDX, kPORT_MuxAlt3);            /* PORTC8 (pin P3) is configured as LPUART0_TX */
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/

FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/pin_mux.h

@@ -0,0 +1,59 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ * 
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Direction type  */
+typedef enum _pin_mux_direction
+{
+  kPIN_MUX_DirectionInput = 0U,         /* Input direction */
+  kPIN_MUX_DirectionOutput = 1U,        /* Output direction */
+  kPIN_MUX_DirectionInputOrOutput = 2U  /* Input or output direction */
+} pin_mux_direction_t;
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/

FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_ri5cy.cfg

@@ -0,0 +1,150 @@
+set _WORKAREASIZE 0x2000
+
+adapter_khz 1000
+
+interface jlink
+transport select jtag
+
+set _WORKAREASIZE 0x1000
+
+set _CHIPNAME rv32m1
+
+reset_config srst_only
+
+# OpenCores Mohor JTAG TAP ID
+set _CPUTAPID  0x249511C3
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME rv32m1 -endian little -chain-position $_TARGETNAME
+
+# Select the TAP core we are using
+tap_select mohor
+
+# Select the debug unit core we are using. This debug unit as an option.
+
+set ADBG_USE_HISPEED		1
+
+# If ADBG_USE_HISPEED is set (options bit 1), status bits will be skipped
+# on burst reads and writes to improve download speeds.
+# This option must match the RTL configured option.
+
+du_select adv [expr $ADBG_USE_HISPEED]
+
+# Select core 0
+core_select 0
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+$_TARGETNAME configure -event gdb-detach {
+    resume
+}
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_CHIPNAME.flash0 rv32m1 0 0 0 0 $_TARGETNAME # For core 0
+flash bank $_CHIPNAME.flash1 rv32m1 0x01000000 0 0 0 $_TARGETNAME # For core 1
+
+proc ri5cy_boot { } {
+
+    # Erase all blok unsecure
+    mwb 0x40023000 0x70
+    mww 0x40023004 0x49000000
+    mwb 0x40023000 0x80
+
+    sleep 1000
+
+    mwb 0x40023000 0x70
+    mww 0x40023008 0xFFFF03FF
+    mww 0x40023004 0x43840000
+    mwb 0x40023000 0x80
+
+    sleep 2
+}
+
+proc cm4_boot { } {
+
+    # Erase all blok unsecure
+    mwb 0x40023000 0x70
+    mww 0x40023004 0x49000000
+    mwb 0x40023000 0x80
+
+    sleep 1000
+
+    mwb 0x40023000 0x70
+    mww 0x40023008 0xFFFFFFFF
+    mww 0x40023004 0x43840000
+    mwb 0x40023000 0x80
+
+    sleep 2
+}
+
+proc zero_boot { } {
+
+    # Erase all blok unsecure
+    mwb 0x40023000 0x70
+    mww 0x40023004 0x49000000
+    mwb 0x40023000 0x80
+
+    sleep 1000
+
+    mwb 0x40023000 0x70
+    mww 0x40023008 0xFFFF03BF
+    mww 0x40023004 0x43840000
+    mwb 0x40023000 0x80
+
+    sleep 2
+}
+
+proc cm0_boot { } {
+
+    # Erase all blok unsecure
+    mwb 0x40023000 0x70
+    mww 0x40023004 0x49000000
+    mwb 0x40023000 0x80
+
+    sleep 1000
+
+    mwb 0x40023000 0x70
+    mww 0x40023008 0xFFFFFFBF
+    mww 0x40023004 0x43840000
+    mwb 0x40023000 0x80
+
+    sleep 2
+}
+
+# All cores are available, CM4 & RI5CY boot first
+proc core0_boot { } {
+
+    # Erase all blok unsecure
+    mwb 0x40023000 0x70
+    mww 0x40023004 0x49000000
+    mwb 0x40023000 0x80
+
+    sleep 1000
+
+    mwb 0x40023000 0x70
+    mww 0x40023008 0xFFFFA3FF
+    mww 0x40023004 0x43840000
+    mwb 0x40023000 0x80
+
+    sleep 2
+}
+
+# All cores are available, CM0 & ZERO_RISCY boot first
+proc core1_boot { } {
+
+    # Erase all blok unsecure
+    mwb 0x40023000 0x70
+    mww 0x40023004 0x49000000
+    mwb 0x40023000 0x80
+
+    sleep 1000
+
+    mwb 0x40023000 0x70
+    mww 0x40023008 0xFFFFA3BF
+    mww 0x40023004 0x43840000
+    mwb 0x40023000 0x80
+
+    sleep 2
+}
+
+init

FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/RISCV/core_riscv32.h

@@ -0,0 +1,123 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+#ifndef __CORE_RISCV32_H__
+#define __CORE_RISCV32_H__
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define RISCV32
+
+#if defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler */
+  #define __STATIC_INLINE  static inline
+
+#else
+  #error Unknown compiler
+#endif
+
+#if defined ( __GNUC__ )
+
+#define __BKPT(x) __ASM("ebreak")
+
+__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
+{
+  __ASM volatile ("nop");
+}
+
+__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
+{
+  __ASM volatile ("nop");
+}
+
+__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
+{
+  __ASM volatile ("nop");
+}
+
+__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
+{
+  __ASM volatile ("wfi");
+}
+
+__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
+{
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+  __ASM volatile ("csrsi mstatus, 8");
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+  __ASM volatile ("csrci mstatus, 8");
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+  return __builtin_bswap32(value);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  return __builtin_bswap16(value);
+}
+
+#else
+  #error Unknown compiler
+#endif
+
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_RISCV32_H__ */

FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/board/board.c

@@ -0,0 +1,29 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ * 
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "board.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+    CLOCK_SetIpSrc(kCLOCK_Lpuart0, kCLOCK_IpSrcFircAsync);
+
+    uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+
+    DbgConsole_Init(BOARD_DEBUG_UART_BASEADDR, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}

FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/board/board.h

@@ -0,0 +1,183 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#include "clock_config.h"
+#include "fsl_gpio.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "RV32M1-VEGA"
+
+/* The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE DEBUG_CONSOLE_DEVICE_TYPE_LPUART
+#define BOARD_DEBUG_UART_BAUDRATE 115200U
+#define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART0
+#define BOARD_DEBUG_UART_INSTANCE    0U
+#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetIpFreq(kCLOCK_Lpuart0)
+#define BOARD_UART_IRQ LPUART0_IRQn
+#define BOARD_UART_IRQ_HANDLER LPUART0_IRQHandler
+
+/* Definitions for eRPC MU transport layer */
+#if defined(FSL_FEATURE_MU_SIDE_A)
+#define MU_BASE MUA
+#define MU_IRQ MUA_IRQn
+#define MU_IRQ_HANDLER MUA_IRQHandler
+#endif
+#if defined(FSL_FEATURE_MU_SIDE_B)
+#define MU_BASE MUB
+#define MU_IRQ MUB_IRQn
+#define MU_IRQ_HANDLER MUB_IRQHandler
+#endif
+#define MU_IRQ_PRIORITY (2)
+
+/*! @brief Define the port interrupt number for the board switches */
+#define BOARD_SW2_GPIO GPIOA
+#define BOARD_SW2_PORT PORTA
+#define BOARD_SW2_GPIO_PIN 0U
+#define BOARD_SW2_IRQ PORTA_IRQn
+#define BOARD_SW2_IRQ_HANDLER PORTA_IRQHandler
+#define BOARD_SW2_NAME "SW2"
+
+/* Board led color mapping */
+#define BOARD_LED_RED_GPIO GPIOA
+#define BOARD_LED_RED_GPIO_PIN 24U
+
+/*! @brief The TPM channel used for board */
+#define BOARD_TPM_CHANNEL 0U
+
+#define LOGIC_LED_ON 1U
+#define LOGIC_LED_OFF 0U
+#define BOARD_LED1_GPIO GPIOA
+#define BOARD_LED1_GPIO_PIN 24U
+#define BOARD_LED2_GPIO GPIOA
+#define BOARD_LED2_GPIO_PIN 23U
+#define BOARD_LED3_GPIO GPIOA
+#define BOARD_LED3_GPIO_PIN 22U
+
+#define LED1_INIT(output)                                              \
+    GPIO_WritePinOutput(BOARD_LED1_GPIO, BOARD_LED1_GPIO_PIN, output); \
+    BOARD_LED1_GPIO->PDDR |= (1U << BOARD_LED1_GPIO_PIN)                                /*!< Enable target LED1 */
+#define LED1_ON() GPIO_SetPinsOutput(BOARD_LED1_GPIO, 1U << BOARD_LED1_GPIO_PIN)        /*!< Turn on target LED1 */
+#define LED1_OFF() GPIO_ClearPinsOutput(BOARD_LED1_GPIO, 1U << BOARD_LED1_GPIO_PIN)     /*!< Turn off target LED1 */
+#define LED1_TOGGLE() GPIO_TogglePinsOutput(BOARD_LED1_GPIO, 1U << BOARD_LED1_GPIO_PIN) /*!< Toggle on target LED1 */
+
+#define LED2_INIT(output)                                              \
+    GPIO_WritePinOutput(BOARD_LED2_GPIO, BOARD_LED2_GPIO_PIN, output); \
+    BOARD_LED2_GPIO->PDDR |= (1U << BOARD_LED2_GPIO_PIN)                                /*!< Enable target LED2 */
+#define LED2_ON() GPIO_SetPinsOutput(BOARD_LED2_GPIO, 1U << BOARD_LED2_GPIO_PIN)        /*!< Turn on target LED2 */
+#define LED2_OFF() GPIO_ClearPinsOutput(BOARD_LED2_GPIO, 1U << BOARD_LED2_GPIO_PIN)     /*!< Turn off target LED2 */
+#define LED2_TOGGLE() GPIO_TogglePinsOutput(BOARD_LED2_GPIO, 1U << BOARD_LED2_GPIO_PIN) /*!< Toggle on target LED2 */
+
+#define LED3_INIT(output)                                              \
+    GPIO_WritePinOutput(BOARD_LED3_GPIO, BOARD_LED3_GPIO_PIN, output); \
+    BOARD_LED3_GPIO->PDDR |= (1U << BOARD_LED3_GPIO_PIN)                                /*!< Enable target LED3 */
+#define LED3_ON() GPIO_SetPinsOutput(BOARD_LED3_GPIO, 1U << BOARD_LED3_GPIO_PIN)        /*!< Turn on target LED3 */
+#define LED3_OFF() GPIO_ClearPinsOutput(BOARD_LED3_GPIO, 1U << BOARD_LED3_GPIO_PIN)     /*!< Turn off target LED3 */
+#define LED3_TOGGLE() GPIO_TogglePinsOutput(BOARD_LED3_GPIO, 1U << BOARD_LED3_GPIO_PIN) /*!< Toggle on target LED3 */
+
+#define BOARD_USDHC0_BASEADDR USDHC0
+#define BOARD_USDHC_CD_PORT_BASE PORTC
+#define BOARD_USDHC_CD_GPIO_BASE GPIOC
+#define BOARD_USDHC_CD_GPIO_PIN 27
+#define BOARD_USDHC_CD_PORT_IRQ PORTC_IRQn
+#define BOARD_USDHC_CD_PORT_IRQ_HANDLER PORTC_IRQHandler
+
+#define BOARD_USDHC_CD_GPIO_INIT()                                                                                \
+    {                                                                                                             \
+        gpio_pin_config_t sw_config = {kGPIO_DigitalInput, 0};                                                    \
+        GPIO_PinInit(BOARD_USDHC_CD_GPIO_BASE, BOARD_USDHC_CD_GPIO_PIN, &sw_config);                              \
+        PORT_SetPinInterruptConfig(BOARD_USDHC_CD_PORT_BASE, BOARD_USDHC_CD_GPIO_PIN, kPORT_InterruptRisingEdge); \
+    }
+
+#define BOARD_USDHC_CD_STATUS() (GPIO_ReadPinInput(BOARD_USDHC_CD_GPIO_BASE, BOARD_USDHC_CD_GPIO_PIN))
+
+#define BOARD_USDHC_CD_INTERRUPT_STATUS() (GPIO_GetPinsInterruptFlags(BOARD_USDHC_CD_GPIO_BASE))
+#define BOARD_USDHC_CD_CLEAR_INTERRUPT(flag) (GPIO_ClearPinsInterruptFlags(BOARD_USDHC_CD_GPIO_BASE, flag))
+#define BOARD_USDHC_CARD_INSERT_CD_LEVEL (1U)
+#define BOARD_USDHC0_CLK_FREQ (CLOCK_GetIpFreq(kCLOCK_Sdhc0))
+
+#define BOARD_SD_HOST_BASEADDR BOARD_USDHC0_BASEADDR
+#define BOARD_SD_HOST_CLK_FREQ BOARD_USDHC0_CLK_FREQ
+#define BOARD_SD_HOST_IRQ USDHC0_IRQn
+#define BOARD_SD_SUPPORT_180V (0U)
+#define BOARD_MMC_HOST_BASEADDR BOARD_USDHC0_BASEADDR
+#define BOARD_MMC_HOST_CLK_FREQ BOARD_USDHC0_CLK_FREQ
+#define BOARD_MMC_HOST_IRQ USDHC0_IRQn
+#define BOARD_MMC_VCCQ_SUPPLY kMMC_VoltageWindows270to360
+#define BOARD_MMC_VCC_SUPPLY kMMC_VoltageWindows270to360
+#define BOARD_MMC_PIN_CONFIG(speed, strength)
+
+/* this define not implement, due to EVK board have no power reset circuit */
+#define BOARD_SD_POWER_RESET_GPIO ()
+#define BOARD_SD_POWER_RESET_GPIO_PIN ()
+#define BOARD_USDHC_SDCARD_POWER_CONTROL_INIT()
+#define BOARD_USDHC_SDCARD_POWER_CONTROL(state)
+#define BOARD_SD_PIN_CONFIG(speed, strength)
+#define BOARD_USDHC_MMCCARD_POWER_CONTROL(enable)
+#define BOARD_USDHC_MMCCARD_POWER_CONTROL_INIT()
+
+#define LLWU_SW_GPIO BOARD_SW2_GPIO
+#define LLWU_SW_PORT BOARD_SW2_PORT
+#define LLWU_SW_GPIO_PIN BOARD_SW2_GPIO_PIN
+#define LLWU_SW_IRQ BOARD_SW2_IRQ
+#define LLWU_SW_IRQ_HANDLER BOARD_SW2_IRQ_HANDLER
+#define LLWU_SW_NAME BOARD_SW2_NAME
+
+#define NMI_PIN                0U
+#define JTAG_TCLK_PIN          1U
+#define JTAG_TDI_PIN           2U
+#define JTAG_TDO_PIN           3U
+#define JTAG_TMS_PIN           4U
+
+#define NMI_PORT               PORTA
+#define JTAG_TCLK_PORT         PORTA
+#define JTAG_TDI_PORT          PORTA
+#define JTAG_TDO_PORT          PORTA
+#define JTAG_TMS_PORT          PORTA 
+
+#define NMI_GPIO               GPIOA
+#define JTAG_TCLK_GPIO         GPIOA
+#define JTAG_TDI_GPIO          GPIOA
+#define JTAG_TDO_GPIO          GPIOA
+#define JTAG_TMS_GPIO          GPIOA
+
+#define BOARD_SPI_FLASH_SCLK_PORT       PORTB
+#define BOARD_SPI_FLASH_SCLK_GPIO       GPIOB
+#define BOARD_SPI_FLASH_SCLK_GPIO_PIN   20U
+
+#define BOARD_SPI_FLASH_SI_PORT         PORTB
+#define BOARD_SPI_FLASH_SI_GPIO         GPIOB
+#define BOARD_SPI_FLASH_SI_GPIO_PIN     21U
+
+#define BOARD_SPI_FLASH_CS_PORT         PORTB
+#define BOARD_SPI_FLASH_CS_GPIO         GPIOB
+#define BOARD_SPI_FLASH_CS_GPIO_PIN     22U
+
+#define BOARD_SPI_FLASH_SO_PORT         PORTB
+#define BOARD_SPI_FLASH_SO_GPIO         GPIOB
+#define BOARD_SPI_FLASH_SO_GPIO_PIN     24U
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */

FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/board/clock_config.c

@@ -0,0 +1,436 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ * 
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. Call CLOCK_InitXXX() to configure corresponding SCG clock source.
+ *    Note: The clock could not be set when it is being used as system clock.
+ *    In default out of reset, the CPU is clocked from FIRC(IRC48M),
+ *    so before setting FIRC, change to use another avaliable clock source.
+ *
+ * 2. Call CLOCK_SetXtal0Freq() to set XTAL0 frequency based on board settings.
+ *
+ * 3. Call CLOCK_SetXxxModeSysClkConfig() to set SCG mode for Xxx run mode.
+ *    Wait until the system clock source is changed to target source.
+ *
+ * 4. If power mode change is needed, call SMC_SetPowerModeProtection() to allow
+ *    corresponding power mode and SMC_SetPowerModeXxx() to change to Xxx mode.
+ *    Supported run mode and clock restrictions could be found in Reference Manual.
+ */
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v3.0
+processor: RV32M1
+package_id: RV32M1
+mcu_data: ksdk2_0
+processor_version: 0.0.0
+board: RV32M1_VEGA
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+#include "fsl_msmc.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define SCG_LPFLL_DISABLE                                 0U  /*!< LPFLL clock disabled */
+#define SCG_SOSC_DISABLE                                  0U  /*!< System OSC disabled */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+#ifndef SDK_SECONDARY_CORE
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_CONFIG_FircSafeConfig
+ * Description   : This function is used to safely configure FIRC clock.
+ *                 In default out of reset, the CPU is clocked from FIRC(IRC48M).
+ *                 Before setting FIRC, change to use SIRC as system clock,
+ *                 then configure FIRC. 
+ * Param fircConfig  : FIRC configuration.
+ *
+ *END**************************************************************************/
+static void CLOCK_CONFIG_FircSafeConfig(const scg_firc_config_t *fircConfig)
+{
+    scg_sys_clk_config_t curConfig;
+    const scg_sirc_config_t scgSircConfig = {.enableMode = kSCG_SircEnable,
+                                             .div1 = kSCG_AsyncClkDisable,
+                                             .div2 = kSCG_AsyncClkDivBy2,
+                                             .range = kSCG_SircRangeHigh};
+    scg_sys_clk_config_t sysClkSafeConfigSource = {
+         .divSlow = kSCG_SysClkDivBy4, /* Slow clock divider. */
+         .divCore = kSCG_SysClkDivBy1, /* Core clock divider. */
+         .src = kSCG_SysClkSrcSirc     /* System clock source. */
+    };
+    /* Init Sirc */
+    CLOCK_InitSirc(&scgSircConfig);
+    /* Change to use SIRC as system clock source to prepare to change FIRCCFG register */
+    CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
+    /* Wait for clock source switch finished */
+    do
+    {
+        CLOCK_GetCurSysClkConfig(&curConfig);
+    } while (curConfig.src != sysClkSafeConfigSource.src);
+
+    /* Init Firc */
+    CLOCK_InitFirc(fircConfig);
+}
+#endif
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockRUN();
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: Bus_clock.outFreq, value: 48 MHz}
+- {id: Core_clock.outFreq, value: 48 MHz}
+- {id: FIRCDIV1_CLK.outFreq, value: 48 MHz}
+- {id: FIRCDIV2_CLK.outFreq, value: 48 MHz}
+- {id: FIRCDIV3_CLK.outFreq, value: 48 MHz}
+- {id: LPO_CLK.outFreq, value: 1 kHz}
+- {id: Platform_clock.outFreq, value: 48 MHz}
+- {id: SIRCDIV3_CLK.outFreq, value: 8 MHz}
+- {id: Slow_clock.outFreq, value: 24 MHz}
+- {id: System_clock.outFreq, value: 48 MHz}
+settings:
+- {id: SCG.FIRCDIV1.scale, value: '1', locked: true}
+- {id: SCG.FIRCDIV2.scale, value: '1', locked: true}
+- {id: SCG.FIRCDIV3.scale, value: '1', locked: true}
+- {id: SCG.LPFLLDIV1.scale, value: '1', locked: true}
+- {id: SCG.LPFLLDIV3.scale, value: '0', locked: true}
+- {id: SCG.SIRCDIV1.scale, value: '0', locked: true}
+- {id: SCG.SIRCDIV3.scale, value: '1', locked: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN =
+    {
+        .divSlow = kSCG_SysClkDivBy2,             /* Slow Clock Divider: divided by 2 */
+        .divBus = kSCG_SysClkDivBy1,              /* Bus Clock Divider: divided by 1 */
+        .divExt = kSCG_SysClkDivBy1,              /* External Clock Divider: divided by 1 */
+        .divCore = kSCG_SysClkDivBy1,             /* Core Clock Divider: divided by 1 */
+        .src = kSCG_SysClkSrcFirc,                /* Fast IRC is selected as System Clock Source */
+    };
+const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockRUN =
+    {
+        .freq = 0U,                               /* System Oscillator frequency: 0Hz */
+        .monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
+        .enableMode = SCG_SOSC_DISABLE,           /* System OSC disabled */
+        .div1 = kSCG_AsyncClkDisable,             /* System OSC Clock Divider 1: Clock output is disabled */
+        .div2 = kSCG_AsyncClkDisable,             /* System OSC Clock Divider 2: Clock output is disabled */
+        .div3 = kSCG_AsyncClkDisable,             /* System OSC Clock Divider 3: Clock output is disabled */
+    };
+const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN =
+    {
+        .enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
+        .div1 = kSCG_AsyncClkDisable,             /* Slow IRC Clock Divider 1: Clock output is disabled */
+        .div2 = kSCG_AsyncClkDisable,             /* Slow IRC Clock Divider 2: Clock output is disabled */
+        .div3 = kSCG_AsyncClkDivBy1,              /* Slow IRC Clock Divider 3: divided by 1 */
+        .range = kSCG_SircRangeHigh,              /* Slow IRC high range clock (8 MHz) */
+    };
+const scg_firc_config_t g_scgFircConfig_BOARD_BootClockRUN =
+    {
+        .enableMode = kSCG_FircEnable,            /* Enable FIRC clock */
+        .div1 = kSCG_AsyncClkDivBy1,              /* Fast IRC Clock Divider 1: divided by 1 */
+        .div2 = kSCG_AsyncClkDivBy1,              /* Fast IRC Clock Divider 2: divided by 1 */
+        .div3 = kSCG_AsyncClkDivBy1,              /* Fast IRC Clock Divider 3: divided by 1 */
+        .range = kSCG_FircRange48M,               /* Fast IRC is trimmed to 48MHz */
+        .trimConfig = NULL,
+    };
+const scg_lpfll_config_t g_scgLpFllConfig_BOARD_BootClockRUN =
+    {
+        .enableMode = SCG_LPFLL_DISABLE,          /* LPFLL clock disabled */
+        .div1 = kSCG_AsyncClkDivBy1,              /* Low Power FLL Clock Divider 1: divided by 1 */
+        .div2 = kSCG_AsyncClkDisable,             /* Low Power FLL Clock Divider 2: Clock output is disabled */
+        .div3 = kSCG_AsyncClkDisable,             /* Low Power FLL Clock Divider 3: Clock output is disabled */
+        .range = kSCG_LpFllRange48M,              /* LPFLL is trimmed to 48MHz */
+        .trimConfig = NULL,
+    };
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    scg_sys_clk_config_t curConfig;
+
+    /* Init FIRC */
+    CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockRUN);
+    /* Set SCG to FIRC mode. */
+    CLOCK_SetRunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockRUN);
+    /* Wait for clock source switch finished */
+    do
+    {
+        CLOCK_GetCurSysClkConfig(&curConfig);
+    } while (curConfig.src != g_sysClkConfig_BOARD_BootClockRUN.src);
+    /* Init SIRC */
+    CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockRUN);
+    /* Init LPFLL */
+    CLOCK_InitLpFll(&g_scgLpFllConfig_BOARD_BootClockRUN);
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+#endif
+}
+
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockHSRUN **********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockHSRUN
+outputs:
+- {id: Bus_clock.outFreq, value: 72 MHz}
+- {id: Core_clock.outFreq, value: 72 MHz}
+- {id: FIRCDIV1_CLK.outFreq, value: 48 MHz}
+- {id: FIRCDIV2_CLK.outFreq, value: 48 MHz}
+- {id: FIRCDIV3_CLK.outFreq, value: 48 MHz}
+- {id: LPO_CLK.outFreq, value: 1 kHz}
+- {id: Platform_clock.outFreq, value: 72 MHz}
+- {id: SIRCDIV3_CLK.outFreq, value: 8 MHz}
+- {id: Slow_clock.outFreq, value: 8 MHz}
+- {id: System_clock.outFreq, value: 72 MHz}
+settings:
+- {id: SCGMode, value: LPFLL}
+- {id: powerMode, value: HSRUN}
+- {id: SCG.DIVCORE.scale, value: '1', locked: true}
+- {id: SCG.DIVSLOW.scale, value: '9'}
+- {id: SCG.FIRCDIV1.scale, value: '1', locked: true}
+- {id: SCG.FIRCDIV2.scale, value: '1', locked: true}
+- {id: SCG.FIRCDIV3.scale, value: '1', locked: true}
+- {id: SCG.LPFLLDIV1.scale, value: '0', locked: true}
+- {id: SCG.LPFLL_mul.scale, value: '36', locked: true}
+- {id: SCG.SCSSEL.sel, value: SCG.LPFLL}
+- {id: SCG.SIRCDIV3.scale, value: '1', locked: true}
+- {id: SCG.TRIMDIV.scale, value: '24'}
+- {id: SCG.TRIMSRCSEL.sel, value: SCG.FIRC}
+- {id: 'SCG::RCCR[SCS].bitField', value: '5'}
+- {id: SCG_LPFLLCSR_LPFLLEN_CFG, value: Enabled}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockHSRUN configuration
+ ******************************************************************************/
+const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockHSRUN =
+    {
+        .divSlow = kSCG_SysClkDivBy9,             /* Slow Clock Divider: divided by 9 */
+        .divBus = kSCG_SysClkDivBy1,              /* Bus Clock Divider: divided by 1 */
+        .divExt = kSCG_SysClkDivBy1,              /* External Clock Divider: divided by 1 */
+        .divCore = kSCG_SysClkDivBy1,             /* Core Clock Divider: divided by 1 */
+        .src = kSCG_SysClkSrcLpFll,               /* Low power FLL is selected as System Clock Source */
+    };
+const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockHSRUN =
+    {
+        .freq = 0U,                               /* System Oscillator frequency: 0Hz */
+        .monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
+        .enableMode = SCG_SOSC_DISABLE,           /* System OSC disabled */
+        .div1 = kSCG_AsyncClkDisable,             /* System OSC Clock Divider 1: Clock output is disabled */
+        .div2 = kSCG_AsyncClkDisable,             /* System OSC Clock Divider 2: Clock output is disabled */
+        .div3 = kSCG_AsyncClkDisable,             /* System OSC Clock Divider 3: Clock output is disabled */
+    };
+const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockHSRUN =
+    {
+        .enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
+        .div1 = kSCG_AsyncClkDisable,             /* Slow IRC Clock Divider 1: Clock output is disabled */
+        .div2 = kSCG_AsyncClkDisable,             /* Slow IRC Clock Divider 2: Clock output is disabled */
+        .div3 = kSCG_AsyncClkDivBy1,              /* Slow IRC Clock Divider 3: divided by 1 */
+        .range = kSCG_SircRangeHigh,              /* Slow IRC high range clock (8 MHz) */
+    };
+const scg_firc_config_t g_scgFircConfig_BOARD_BootClockHSRUN =
+    {
+        .enableMode = kSCG_FircEnable,            /* Enable FIRC clock */
+        .div1 = kSCG_AsyncClkDivBy1,              /* Fast IRC Clock Divider 1: divided by 1 */
+        .div2 = kSCG_AsyncClkDivBy1,              /* Fast IRC Clock Divider 2: divided by 1 */
+        .div3 = kSCG_AsyncClkDivBy1,              /* Fast IRC Clock Divider 3: divided by 1 */
+        .range = kSCG_FircRange48M,               /* Fast IRC is trimmed to 48MHz */
+        .trimConfig = NULL,
+    };
+const scg_lpfll_config_t g_scgLpFllConfig_BOARD_BootClockHSRUN =
+    {
+        .enableMode = kSCG_LpFllEnable,           /* Enable LPFLL clock */
+        .div1 = kSCG_AsyncClkDisable,             /* Low Power FLL Clock Divider 1: Clock output is disabled */
+        .div2 = kSCG_AsyncClkDisable,             /* Low Power FLL Clock Divider 2: Clock output is disabled */
+        .div3 = kSCG_AsyncClkDisable,             /* Low Power FLL Clock Divider 3: Clock output is disabled */
+        .range = kSCG_LpFllRange72M,              /* LPFLL is trimmed to 72MHz */
+        .trimConfig = NULL,
+    };
+/*******************************************************************************
+ * Code for BOARD_BootClockHSRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockHSRUN(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    scg_sys_clk_config_t curConfig;
+
+    /* Init FIRC */
+    CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockHSRUN);
+    /* Init LPFLL */
+    CLOCK_InitLpFll(&g_scgLpFllConfig_BOARD_BootClockHSRUN);
+#if defined(CPU_RV32M1_cm4) || defined(CPU_RV32M1_ri5cy)
+    /* Set HSRUN power mode */
+    SMC_SetPowerModeProtection(SMC0, kSMC_AllowPowerModeAll);
+    SMC_SetPowerModeHsrun(SMC0);
+    while (SMC_GetPowerModeState(SMC0) != kSMC_PowerStateHsrun)
+    {
+    }
+#elif defined(CPU_RV32M1_cm0plus) || defined(CPU_RV32M1_zero_riscy)
+    SMC_SetPowerModeProtection(SMC1, kSMC_AllowPowerModeAll);
+    SMC_SetPowerModeHsrun(SMC1);
+    while (SMC_GetPowerModeState(SMC1) != kSMC_PowerStateHsrun)
+    {
+    }
+#endif
+    /* Set SCG to LPFLL mode. */
+    CLOCK_SetHsrunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockHSRUN);
+    /* Wait for clock source switch finished */
+    do
+    {
+        CLOCK_GetCurSysClkConfig(&curConfig);
+    } while (curConfig.src != g_sysClkConfig_BOARD_BootClockHSRUN.src);
+    /* Init SIRC */
+    CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockHSRUN);
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKHSRUN_CORE_CLOCK;
+#endif
+}
+
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockVLPR ***********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockVLPR
+outputs:
+- {id: Bus_clock.outFreq, value: 2 MHz}
+- {id: Core_clock.outFreq, value: 4 MHz}
+- {id: LPO_CLK.outFreq, value: 1 kHz}
+- {id: Platform_clock.outFreq, value: 4 MHz}
+- {id: SIRCDIV1_CLK.outFreq, value: 8 MHz}
+- {id: SIRCDIV2_CLK.outFreq, value: 8 MHz}
+- {id: SIRCDIV3_CLK.outFreq, value: 8 MHz}
+- {id: Slow_clock.outFreq, value: 4000/9 kHz}
+- {id: System_clock.outFreq, value: 4 MHz}
+settings:
+- {id: SCGMode, value: SIRC}
+- {id: powerMode, value: VLPR}
+- {id: SCG.DIVBUS.scale, value: '2', locked: true}
+- {id: SCG.DIVCORE.scale, value: '2', locked: true}
+- {id: SCG.DIVSLOW.scale, value: '9'}
+- {id: SCG.FIRCDIV1.scale, value: '1'}
+- {id: SCG.SCSSEL.sel, value: SCG.SIRC}
+- {id: SCG.SIRCDIV1.scale, value: '1', locked: true}
+- {id: SCG.SIRCDIV2.scale, value: '1', locked: true}
+- {id: SCG.SIRCDIV3.scale, value: '1', locked: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockVLPR =
+    {
+        .divSlow = kSCG_SysClkDivBy9,             /* Slow Clock Divider: divided by 9 */
+        .divBus = kSCG_SysClkDivBy2,              /* Bus Clock Divider: divided by 2 */
+        .divExt = kSCG_SysClkDivBy1,              /* External Clock Divider: divided by 1 */
+        .divCore = kSCG_SysClkDivBy2,             /* Core Clock Divider: divided by 2 */
+        .src = kSCG_SysClkSrcSirc,                /* Slow IRC is selected as System Clock Source */
+    };
+const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockVLPR =
+    {
+        .freq = 0U,                               /* System Oscillator frequency: 0Hz */
+        .monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
+        .enableMode = SCG_SOSC_DISABLE,           /* System OSC disabled */
+        .div1 = kSCG_AsyncClkDisable,             /* System OSC Clock Divider 1: Clock output is disabled */
+        .div2 = kSCG_AsyncClkDisable,             /* System OSC Clock Divider 2: Clock output is disabled */
+        .div3 = kSCG_AsyncClkDisable,             /* System OSC Clock Divider 3: Clock output is disabled */
+    };
+const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR =
+    {
+        .enableMode = kSCG_SircEnable | kSCG_SircEnableInLowPower,/* Enable SIRC clock, Enable SIRC in low power mode */
+        .div1 = kSCG_AsyncClkDivBy1,              /* Slow IRC Clock Divider 1: divided by 1 */
+        .div2 = kSCG_AsyncClkDivBy1,              /* Slow IRC Clock Divider 2: divided by 1 */
+        .div3 = kSCG_AsyncClkDivBy1,              /* Slow IRC Clock Divider 3: divided by 1 */
+        .range = kSCG_SircRangeHigh,              /* Slow IRC high range clock (8 MHz) */
+    };
+const scg_firc_config_t g_scgFircConfig_BOARD_BootClockVLPR =
+    {
+        .enableMode = kSCG_FircEnable,            /* Enable FIRC clock */
+        .div1 = kSCG_AsyncClkDivBy1,              /* Fast IRC Clock Divider 1: divided by 1 */
+        .div2 = kSCG_AsyncClkDisable,             /* Fast IRC Clock Divider 2: Clock output is disabled */
+        .div3 = kSCG_AsyncClkDisable,             /* Fast IRC Clock Divider 3: Clock output is disabled */
+        .range = kSCG_FircRange48M,               /* Fast IRC is trimmed to 48MHz */
+        .trimConfig = NULL,
+    };
+const scg_lpfll_config_t g_scgLpFllConfig_BOARD_BootClockVLPR =
+    {
+        .enableMode = SCG_LPFLL_DISABLE,          /* LPFLL clock disabled */
+        .div1 = kSCG_AsyncClkDisable,             /* Low Power FLL Clock Divider 1: Clock output is disabled */
+        .div2 = kSCG_AsyncClkDisable,             /* Low Power FLL Clock Divider 2: Clock output is disabled */
+        .div3 = kSCG_AsyncClkDisable,             /* Low Power FLL Clock Divider 3: Clock output is disabled */
+        .range = kSCG_LpFllRange48M,              /* LPFLL is trimmed to 48MHz */
+        .trimConfig = NULL,
+    };
+/*******************************************************************************
+ * Code for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+void BOARD_BootClockVLPR(void)
+{
+#ifndef SDK_SECONDARY_CORE
+    scg_sys_clk_config_t curConfig;
+
+    /* Init SIRC */
+    CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockVLPR);
+    /* Set SCG to SIRC mode. */
+    CLOCK_SetVlprModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockVLPR);
+    /* Init FIRC */
+    CLOCK_InitFirc(&g_scgFircConfig_BOARD_BootClockVLPR);
+    /* Init LPFLL */
+    CLOCK_InitLpFll(&g_scgLpFllConfig_BOARD_BootClockVLPR);
+#if defined(CPU_RV32M1_cm4) || defined(CPU_RV32M1_ri5cy)
+    /* Set VLPR power mode. */
+    SMC_SetPowerModeProtection(SMC0, kSMC_AllowPowerModeAll);
+    SMC_SetPowerModeVlpr(SMC0);
+    while (SMC_GetPowerModeState(SMC0) != kSMC_PowerStateVlpr)
+    {
+    }
+#elif defined(CPU_RV32M1_cm0plus) || defined(CPU_RV32M1_zero_riscy)
+    /* Set VLPR power mode. */
+    SMC_SetPowerModeProtection(SMC1, kSMC_AllowPowerModeAll);
+    SMC_SetPowerModeVlpr(SMC1);
+    while (SMC_GetPowerModeState(SMC1) != kSMC_PowerStateVlpr)
+    {
+    }
+#endif
+    /* Wait for clock source switch finished */
+    do
+    {
+        CLOCK_GetCurSysClkConfig(&curConfig);
+    } while (curConfig.src != g_sysClkConfig_BOARD_BootClockVLPR.src);
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
+#endif
+}
+

FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/board/clock_config.h

@@ -0,0 +1,159 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ * 
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+ 
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK              48000000U  /*!< Core clock frequency: 48000000Hz */
+
+/*! @brief SCG set for BOARD_BootClockRUN configuration.
+ */
+extern const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN;
+/*! @brief System OSC set for BOARD_BootClockRUN configuration.
+ */
+extern const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockRUN;
+/*! @brief SIRC set for BOARD_BootClockRUN configuration.
+ */
+extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN;
+/*! @brief FIRC set for BOARD_BootClockRUN configuration.
+ */
+extern const scg_firc_config_t g_scgFircConfigBOARD_BootClockRUN;
+/*! @brief Low Power FLL set for BOARD_BootClockRUN configuration.
+ */
+extern const scg_lpfll_config_t g_scgLpFllConfigBOARD_BootClockRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockHSRUN **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockHSRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKHSRUN_CORE_CLOCK            72000000U  /*!< Core clock frequency: 72000000Hz */
+
+/*! @brief SCG set for BOARD_BootClockHSRUN configuration.
+ */
+extern const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockHSRUN;
+/*! @brief System OSC set for BOARD_BootClockHSRUN configuration.
+ */
+extern const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockHSRUN;
+/*! @brief SIRC set for BOARD_BootClockHSRUN configuration.
+ */
+extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockHSRUN;
+/*! @brief FIRC set for BOARD_BootClockHSRUN configuration.
+ */
+extern const scg_firc_config_t g_scgFircConfigBOARD_BootClockHSRUN;
+/*! @brief Low Power FLL set for BOARD_BootClockHSRUN configuration.
+ */
+extern const scg_lpfll_config_t g_scgLpFllConfigBOARD_BootClockHSRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockHSRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockHSRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************* Configuration BOARD_BootClockVLPR ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKVLPR_CORE_CLOCK              4000000U  /*!< Core clock frequency: 4000000Hz */
+
+/*! @brief SCG set for BOARD_BootClockVLPR configuration.
+ */
+extern const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockVLPR;
+/*! @brief System OSC set for BOARD_BootClockVLPR configuration.
+ */
+extern const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockVLPR;
+/*! @brief SIRC set for BOARD_BootClockVLPR configuration.
+ */
+extern const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR;
+/*! @brief FIRC set for BOARD_BootClockVLPR configuration.
+ */
+extern const scg_firc_config_t g_scgFircConfigBOARD_BootClockVLPR;
+/*! @brief Low Power FLL set for BOARD_BootClockVLPR configuration.
+ */
+extern const scg_lpfll_config_t g_scgLpFllConfigBOARD_BootClockVLPR;
+
+/*******************************************************************************
+ * API for BOARD_BootClockVLPR configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockVLPR(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
+

FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/board/readme.txt

@@ -0,0 +1,48 @@
+Overview
+========
+The Hello World demo application provides a sanity check for the new SDK build environments and board bring up. The Hello
+World demo prints the "Hello World" string to the terminal using the SDK UART drivers. The purpose of this demo is to
+show how to use the UART, and to provide a simple project for debugging and further development.
+
+Toolchain supported
+===================
+- GCC RISC-V Embedded 7.1.1
+- RISC-V Eclipse IDE 4.7.2
+
+Hardware requirements
+=====================
+- Mini/micro USB cable
+- RV32M1-VEGA board
+- Personal Computer
+
+Board settings
+==============
+No special settings are required.
+If download M0+ core project, need to let MCU boot from M0+ core, please follow below steps:
+1. Download blhost.exe from www.nxp.com/kboot.
+2. Connect J8 on board to PC using USB cable.
+3. After PC recognize the USB HID device, go to blhost.exe folder, open command line.
+4. Run command "blhost.exe -u -- flash-erase-all-unsecure", it will erase the flash on chip.
+5. Run command "blhost.exe -u -- flash-program-once 0x84 4 ffffffbf", set FOPT3 to boot from M0+ core.
+
+Prepare the Demo
+================
+1.  Connect a USB cable between the host PC and the OpenSDA USB port on the target board. 
+2.  Open a serial terminal with the following settings:
+    - 115200 baud rate
+    - 8 data bits
+    - No parity
+    - One stop bit
+    - No flow control
+3.  Download the program to the target board.
+4.  Either press the reset button on your board or launch the debugger in your IDE to begin running the demo.
+
+Running the demo
+================
+The log below shows the output of the hello world demo in the terminal window:
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+hello world.
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Customization options
+=====================
+

FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_clock.c

@@ -0,0 +1,794 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright (c) 2016 - 2017 , NXP
+ * All rights reserved.
+ *
+ * 
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+#define SCG_SIRC_LOW_RANGE_FREQ 2000000U  /* Slow IRC low range clock frequency. */
+#define SCG_SIRC_HIGH_RANGE_FREQ 8000000U /* Slow IRC high range clock frequency.   */
+
+#define SCG_FIRC_FREQ0 48000000U /* Fast IRC trimed clock frequency(48MHz). */
+#define SCG_FIRC_FREQ1 52000000U /* Fast IRC trimed clock frequency(52MHz). */
+#define SCG_FIRC_FREQ2 56000000U /* Fast IRC trimed clock frequency(56MHz). */
+#define SCG_FIRC_FREQ3 60000000U /* Fast IRC trimed clock frequency(60MHz). */
+
+#define SCG_LPFLL_FREQ0 48000000U  /* LPFLL trimed clock frequency(48MHz). */
+#define SCG_LPFLL_FREQ1 72000000U  /* LPFLL trimed clock frequency(72MHz). */
+#define SCG_LPFLL_FREQ2 96000000U  /* LPFLL trimed clock frequency(96MHz). */
+#define SCG_LPFLL_FREQ3 120000000U /* LPFLL trimed clock frequency(120MHz). */
+
+#define SCG_CSR_SCS_VAL ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT)
+#define SCG_SOSCDIV_SOSCDIV1_VAL ((SCG->SOSCDIV & SCG_SOSCDIV_SOSCDIV1_MASK) >> SCG_SOSCDIV_SOSCDIV1_SHIFT)
+#define SCG_SOSCDIV_SOSCDIV2_VAL ((SCG->SOSCDIV & SCG_SOSCDIV_SOSCDIV2_MASK) >> SCG_SOSCDIV_SOSCDIV2_SHIFT)
+#define SCG_SOSCDIV_SOSCDIV3_VAL ((SCG->SOSCDIV & SCG_SOSCDIV_SOSCDIV3_MASK) >> SCG_SOSCDIV_SOSCDIV3_SHIFT)
+#define SCG_SIRCDIV_SIRCDIV1_VAL ((SCG->SIRCDIV & SCG_SIRCDIV_SIRCDIV1_MASK) >> SCG_SIRCDIV_SIRCDIV1_SHIFT)
+#define SCG_SIRCDIV_SIRCDIV2_VAL ((SCG->SIRCDIV & SCG_SIRCDIV_SIRCDIV2_MASK) >> SCG_SIRCDIV_SIRCDIV2_SHIFT)
+#define SCG_SIRCDIV_SIRCDIV3_VAL ((SCG->SIRCDIV & SCG_SIRCDIV_SIRCDIV3_MASK) >> SCG_SIRCDIV_SIRCDIV3_SHIFT)
+#define SCG_FIRCDIV_FIRCDIV1_VAL ((SCG->FIRCDIV & SCG_FIRCDIV_FIRCDIV1_MASK) >> SCG_FIRCDIV_FIRCDIV1_SHIFT)
+#define SCG_FIRCDIV_FIRCDIV2_VAL ((SCG->FIRCDIV & SCG_FIRCDIV_FIRCDIV2_MASK) >> SCG_FIRCDIV_FIRCDIV2_SHIFT)
+#define SCG_FIRCDIV_FIRCDIV3_VAL ((SCG->FIRCDIV & SCG_FIRCDIV_FIRCDIV3_MASK) >> SCG_FIRCDIV_FIRCDIV3_SHIFT)
+
+#define SCG_LPFLLDIV_LPFLLDIV1_VAL ((SCG->LPFLLDIV & SCG_LPFLLDIV_LPFLLDIV1_MASK) >> SCG_LPFLLDIV_LPFLLDIV1_SHIFT)
+#define SCG_LPFLLDIV_LPFLLDIV2_VAL ((SCG->LPFLLDIV & SCG_LPFLLDIV_LPFLLDIV2_MASK) >> SCG_LPFLLDIV_LPFLLDIV2_SHIFT)
+#define SCG_LPFLLDIV_LPFLLDIV3_VAL ((SCG->LPFLLDIV & SCG_LPFLLDIV_LPFLLDIV3_MASK) >> SCG_LPFLLDIV_LPFLLDIV3_SHIFT)
+
+#define SCG_SIRCCFG_RANGE_VAL ((SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) >> SCG_SIRCCFG_RANGE_SHIFT)
+#define SCG_FIRCCFG_RANGE_VAL ((SCG->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT)
+
+#define SCG_LPFLLCFG_FSEL_VAL ((SCG->LPFLLCFG & SCG_LPFLLCFG_FSEL_MASK) >> SCG_LPFLLCFG_FSEL_SHIFT)
+
+/* Get the value of each field in PCC register. */
+#define PCC_PCS_VAL(reg) ((reg & PCC_CLKCFG_PCS_MASK) >> PCC_CLKCFG_PCS_SHIFT)
+#define PCC_FRAC_VAL(reg) ((reg & PCC_CLKCFG_FRAC_MASK) >> PCC_CLKCFG_FRAC_SHIFT)
+#define PCC_PCD_VAL(reg) ((reg & PCC_CLKCFG_PCD_MASK) >> PCC_CLKCFG_PCD_SHIFT)
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* External XTAL0 (OSC0) clock frequency. */
+uint32_t g_xtal0Freq;
+/* External XTAL32K clock frequency. */
+uint32_t g_xtal32Freq;
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+uint32_t CLOCK_GetOsc32kClkFreq(void)
+{
+    assert(g_xtal32Freq);
+    return g_xtal32Freq;
+}
+
+uint32_t CLOCK_GetFlashClkFreq(void)
+{
+    return CLOCK_GetSysClkFreq(kSCG_SysClkSlow);
+}
+
+uint32_t CLOCK_GetBusClkFreq(void)
+{
+    return CLOCK_GetSysClkFreq(kSCG_SysClkSlow);
+}
+
+uint32_t CLOCK_GetPlatClkFreq(void)
+{
+    return CLOCK_GetSysClkFreq(kSCG_SysClkCore);
+}
+
+uint32_t CLOCK_GetCoreSysClkFreq(void)
+{
+    return CLOCK_GetSysClkFreq(kSCG_SysClkCore);
+}
+
+uint32_t CLOCK_GetExtClkFreq(void)
+{
+    return CLOCK_GetSysClkFreq(kSCG_SysClkExt);
+}
+
+uint32_t CLOCK_GetFreq(clock_name_t clockName)
+{
+    uint32_t freq;
+
+    switch (clockName)
+    {
+        /* System layer clock. */
+        case kCLOCK_CoreSysClk:
+        case kCLOCK_PlatClk:
+            freq = CLOCK_GetSysClkFreq(kSCG_SysClkCore);
+            break;
+        case kCLOCK_BusClk:
+            freq = CLOCK_GetSysClkFreq(kSCG_SysClkBus);
+            break;
+        case kCLOCK_FlashClk:
+            freq = CLOCK_GetSysClkFreq(kSCG_SysClkSlow);
+            break;
+        case kCLOCK_ExtClk:
+            freq = CLOCK_GetSysClkFreq(kSCG_SysClkExt);
+            break;
+        /* Original clock source. */
+        case kCLOCK_ScgSysOscClk:
+            freq = CLOCK_GetSysOscFreq();
+            break;
+        case kCLOCK_ScgSircClk:
+            freq = CLOCK_GetSircFreq();
+            break;
+        case kCLOCK_ScgFircClk:
+            freq = CLOCK_GetFircFreq();
+            break;
+        case kCLOCK_ScgLpFllClk:
+            freq = CLOCK_GetLpFllFreq();
+            break;
+
+        /* SOSC div clock. */
+        case kCLOCK_ScgSysOscAsyncDiv1Clk:
+            freq = CLOCK_GetSysOscAsyncFreq(kSCG_AsyncDiv1Clk);
+            break;
+        case kCLOCK_ScgSysOscAsyncDiv2Clk:
+            freq = CLOCK_GetSysOscAsyncFreq(kSCG_AsyncDiv2Clk);
+            break;
+        case kCLOCK_ScgSysOscAsyncDiv3Clk:
+            freq = CLOCK_GetSysOscAsyncFreq(kSCG_AsyncDiv3Clk);
+            break;
+
+        /* SIRC div clock. */
+        case kCLOCK_ScgSircAsyncDiv1Clk:
+            freq = CLOCK_GetSircAsyncFreq(kSCG_AsyncDiv1Clk);
+            break;
+        case kCLOCK_ScgSircAsyncDiv2Clk:
+            freq = CLOCK_GetSircAsyncFreq(kSCG_AsyncDiv2Clk);
+            break;
+        case kCLOCK_ScgSircAsyncDiv3Clk:
+            freq = CLOCK_GetSircAsyncFreq(kSCG_AsyncDiv3Clk);
+            break;
+
+        /* FIRC div clock. */
+        case kCLOCK_ScgFircAsyncDiv1Clk:
+            freq = CLOCK_GetFircAsyncFreq(kSCG_AsyncDiv1Clk);
+            break;
+        case kCLOCK_ScgFircAsyncDiv2Clk:
+            freq = CLOCK_GetFircAsyncFreq(kSCG_AsyncDiv2Clk);
+            break;
+        case kCLOCK_ScgFircAsyncDiv3Clk:
+            freq = CLOCK_GetFircAsyncFreq(kSCG_AsyncDiv3Clk);
+            break;
+
+        /* LPFLL div clock. */
+        case kCLOCK_ScgSysLpFllAsyncDiv1Clk:
+            freq = CLOCK_GetLpFllAsyncFreq(kSCG_AsyncDiv1Clk);
+            break;
+        case kCLOCK_ScgSysLpFllAsyncDiv2Clk:
+            freq = CLOCK_GetLpFllAsyncFreq(kSCG_AsyncDiv2Clk);
+            break;
+        case kCLOCK_ScgSysLpFllAsyncDiv3Clk:
+            freq = CLOCK_GetLpFllAsyncFreq(kSCG_AsyncDiv3Clk);
+            break;
+
+        /* Other clocks. */
+        case kCLOCK_LpoClk:
+            freq = CLOCK_GetLpoClkFreq();
+            break;
+        case kCLOCK_Osc32kClk:
+            freq = CLOCK_GetOsc32kClkFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+    return freq;
+}
+
+uint32_t CLOCK_GetIpFreq(clock_ip_name_t name)
+{
+    uint32_t reg = (*(volatile uint32_t *)name);
+
+    scg_async_clk_t asycClk;
+    uint32_t freq;
+
+    assert(reg & PCC_CLKCFG_PR_MASK);
+
+    switch (name)
+    {
+        case kCLOCK_Lpit0:
+        case kCLOCK_Lpit1:
+            asycClk = kSCG_AsyncDiv3Clk;
+            break;
+        case kCLOCK_Sdhc0:
+        case kCLOCK_Usb0:
+            asycClk = kSCG_AsyncDiv1Clk;
+            break;
+        default:
+            asycClk = kSCG_AsyncDiv2Clk;
+            break;
+    }
+
+    switch (PCC_PCS_VAL(reg))
+    {
+        case kCLOCK_IpSrcSysOscAsync:
+            freq = CLOCK_GetSysOscAsyncFreq(asycClk);
+            break;
+        case kCLOCK_IpSrcSircAsync:
+            freq = CLOCK_GetSircAsyncFreq(asycClk);
+            break;
+        case kCLOCK_IpSrcFircAsync:
+            freq = CLOCK_GetFircAsyncFreq(asycClk);
+            break;
+        case kCLOCK_IpSrcLpFllAsync:
+            freq = CLOCK_GetLpFllAsyncFreq(asycClk);
+            break;
+        default: /* kCLOCK_IpSrcNoneOrExt. */
+            freq = 0U;
+            break;
+    }
+
+    if (0U != (reg & (PCC_CLKCFG_PCD_MASK | PCC_CLKCFG_FRAC_MASK)))
+    {
+        return freq * (PCC_FRAC_VAL(reg) + 1U) / (PCC_PCD_VAL(reg) + 1U);
+    }
+    else
+    {
+        return freq;
+    }
+}
+
+bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq)
+{
+    bool ret = true;
+
+    CLOCK_SetIpSrc(kCLOCK_Usb0, kCLOCK_IpSrcFircAsync);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable clock gate. */
+    CLOCK_EnableClock(kCLOCK_Usb0);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    USBVREG->CTRL |= USBVREG_CTRL_EN_MASK;
+    USB0->CONTROL &= ~USB_CONTROL_DPPULLUPNONOTG_MASK;
+
+    if (kCLOCK_UsbSrcIrc48M == src)
+    {
+        USB0->CLK_RECOVER_IRC_EN = 0x03U;
+        USB0->CLK_RECOVER_CTRL |= USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK;
+        USB0->CLK_RECOVER_INT_EN = 0x00U;
+    }
+    return ret;
+}
+
+uint32_t CLOCK_GetSysClkFreq(scg_sys_clk_t type)
+{
+    uint32_t freq;
+
+    scg_sys_clk_config_t sysClkConfig;
+
+    CLOCK_GetCurSysClkConfig(&sysClkConfig); /* Get the main clock for SoC platform. */
+
+    switch (sysClkConfig.src)
+    {
+        case kSCG_SysClkSrcSysOsc:
+            freq = CLOCK_GetSysOscFreq();
+            break;
+        case kSCG_SysClkSrcSirc:
+            freq = CLOCK_GetSircFreq();
+            break;
+        case kSCG_SysClkSrcFirc:
+            freq = CLOCK_GetFircFreq();
+            break;
+        case kSCG_SysClkSrcRosc:
+            freq = CLOCK_GetRtcOscFreq();
+            break;
+        case kSCG_SysClkSrcLpFll:
+            freq = CLOCK_GetLpFllFreq();
+            break;
+        default:
+            freq = 0U;
+            break;
+    }
+
+    freq /= (sysClkConfig.divCore + 1U); /* divided by the DIVCORE firstly. */
+
+    if (kSCG_SysClkSlow == type)
+    {
+        freq /= (sysClkConfig.divSlow + 1U);
+    }
+    else if (kSCG_SysClkBus == type)
+    {
+        freq /= (sysClkConfig.divBus + 1U);
+    }
+    else if (kSCG_SysClkExt == type)
+    {
+        freq /= (sysClkConfig.divExt + 1U);
+    }
+    else
+    {
+    }
+
+    return freq;
+}
+
+status_t CLOCK_InitSysOsc(const scg_sosc_config_t *config)
+{
+    assert(config);
+    status_t status;
+    uint8_t tmp8;
+
+    /* De-init the SOSC first. */
+    status = CLOCK_DeinitSysOsc();
+
+    if (kStatus_Success != status)
+    {
+        return status;
+    }
+
+    /* Now start to set up OSC clock. */
+    /* Step 1. Setup dividers. */
+    SCG->SOSCDIV =
+        SCG_SOSCDIV_SOSCDIV1(config->div1) | SCG_SOSCDIV_SOSCDIV2(config->div2) | SCG_SOSCDIV_SOSCDIV3(config->div3);
+
+    /* Step 2. Set OSC configuration. */
+
+    /* Step 3. Enable clock. */
+    /* SCG->SOSCCSR = SCG_SOSCCSR_SOSCEN_MASK | (config->enableMode); */
+    tmp8 = config->enableMode;
+    tmp8 |= SCG_SOSCCSR_SOSCEN_MASK;
+    SCG->SOSCCSR = tmp8;
+
+    /* Step 4. Wait for OSC clock to be valid. */
+    while (!(SCG->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK))
+    {
+    }
+
+    /* Step 5. Enabe monitor. */
+    SCG->SOSCCSR |= (uint32_t)config->monitorMode;
+
+    return kStatus_Success;
+}
+
+status_t CLOCK_DeinitSysOsc(void)
+{
+    uint32_t reg = SCG->SOSCCSR;
+
+    /* If clock is used by system, return error. */
+    if (reg & SCG_SOSCCSR_SOSCSEL_MASK)
+    {
+        return kStatus_SCG_Busy;
+    }
+
+    /* If configure register is locked, return error. */
+    if (reg & SCG_SOSCCSR_LK_MASK)
+    {
+        return kStatus_ReadOnly;
+    }
+
+    SCG->SOSCCSR = SCG_SOSCCSR_SOSCERR_MASK;
+
+    return kStatus_Success;
+}
+
+uint32_t CLOCK_GetSysOscFreq(void)
+{
+    if (SCG->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) /* System OSC clock is valid. */
+    {
+        /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */
+        assert(g_xtal0Freq);
+        return g_xtal0Freq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+uint32_t CLOCK_GetSysOscAsyncFreq(scg_async_clk_t type)
+{
+    uint32_t oscFreq = CLOCK_GetSysOscFreq();
+    uint32_t divider = 0U;
+
+    /* Get divider. */
+    if (oscFreq)
+    {
+        switch (type)
+        {
+            case kSCG_AsyncDiv3Clk: /* SOSCDIV3_CLK. */
+                divider = SCG_SOSCDIV_SOSCDIV3_VAL;
+                break;
+            case kSCG_AsyncDiv2Clk: /* SOSCDIV2_CLK. */
+                divider = SCG_SOSCDIV_SOSCDIV2_VAL;
+                break;
+            case kSCG_AsyncDiv1Clk: /* SOSCDIV1_CLK. */
+                divider = SCG_SOSCDIV_SOSCDIV1_VAL;
+                break;
+            default:
+                break;
+        }
+    }
+    if (divider)
+    {
+        return oscFreq >> (divider - 1U);
+    }
+    else /* Output disabled. */
+    {
+        return 0U;
+    }
+}
+
+status_t CLOCK_InitSirc(const scg_sirc_config_t *config)
+{
+    assert(config);
+
+    status_t status;
+
+    /* De-init the SIRC first. */
+    status = CLOCK_DeinitSirc();
+
+    if (kStatus_Success != status)
+    {
+        return status;
+    }
+
+    /* Now start to set up SIRC clock. */
+    /* Step 1. Setup dividers. */
+    SCG->SIRCDIV =
+        SCG_SIRCDIV_SIRCDIV1(config->div1) | SCG_SIRCDIV_SIRCDIV2(config->div2) | SCG_SIRCDIV_SIRCDIV3(config->div3);
+
+    /* Step 2. Set SIRC configuration. */
+    SCG->SIRCCFG = SCG_SIRCCFG_RANGE(config->range);
+
+    /* Step 3. Enable clock. */
+    SCG->SIRCCSR = SCG_SIRCCSR_SIRCEN_MASK | config->enableMode;
+
+    /* Step 4. Wait for SIRC clock to be valid. */
+    while (!(SCG->SIRCCSR & SCG_SIRCCSR_SIRCVLD_MASK))
+    {
+    }
+
+    return kStatus_Success;
+}
+
+status_t CLOCK_DeinitSirc(void)
+{
+    uint32_t reg = SCG->SIRCCSR;
+
+    /* If clock is used by system, return error. */
+    if (reg & SCG_SIRCCSR_SIRCSEL_MASK)
+    {
+        return kStatus_SCG_Busy;
+    }
+
+    /* If configure register is locked, return error. */
+    if (reg & SCG_SIRCCSR_LK_MASK)
+    {
+        return kStatus_ReadOnly;
+    }
+
+    SCG->SIRCCSR = 0U;
+
+    return kStatus_Success;
+}
+
+uint32_t CLOCK_GetSircFreq(void)
+{
+    static const uint32_t sircFreq[] = {SCG_SIRC_LOW_RANGE_FREQ, SCG_SIRC_HIGH_RANGE_FREQ};
+
+    if (SCG->SIRCCSR & SCG_SIRCCSR_SIRCVLD_MASK) /* SIRC is valid. */
+    {
+        return sircFreq[SCG_SIRCCFG_RANGE_VAL];
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+uint32_t CLOCK_GetSircAsyncFreq(scg_async_clk_t type)
+{
+    uint32_t sircFreq = CLOCK_GetSircFreq();
+    uint32_t divider = 0U;
+
+    /* Get divider. */
+    if (sircFreq)
+    {
+        switch (type)
+        {
+            case kSCG_AsyncDiv3Clk: /* SIRCDIV3_CLK. */
+                divider = SCG_SIRCDIV_SIRCDIV3_VAL;
+                break;
+            case kSCG_AsyncDiv2Clk: /* SIRCDIV2_CLK. */
+                divider = SCG_SIRCDIV_SIRCDIV2_VAL;
+                break;
+            case kSCG_AsyncDiv1Clk: /* SIRCDIV2_CLK. */
+                divider = SCG_SIRCDIV_SIRCDIV1_VAL;
+                break;
+            default:
+                break;
+        }
+    }
+    if (divider)
+    {
+        return sircFreq >> (divider - 1U);
+    }
+    else /* Output disabled. */
+    {
+        return 0U;
+    }
+}
+
+status_t CLOCK_InitFirc(const scg_firc_config_t *config)
+{
+    assert(config);
+
+    status_t status;
+
+    /* De-init the FIRC first. */
+    status = CLOCK_DeinitFirc();
+
+    if (kStatus_Success != status)
+    {
+        return status;
+    }
+
+    /* Now start to set up FIRC clock. */
+    /* Step 1. Setup dividers. */
+    SCG->FIRCDIV =
+        SCG_FIRCDIV_FIRCDIV1(config->div1) | SCG_FIRCDIV_FIRCDIV2(config->div2) | SCG_FIRCDIV_FIRCDIV3(config->div3);
+
+    /* Step 2. Set FIRC configuration. */
+    SCG->FIRCCFG = SCG_FIRCCFG_RANGE(config->range);
+
+    /* Step 3. Set trimming configuration. */
+    if (config->trimConfig)
+    {
+        SCG->FIRCTCFG =
+            SCG_FIRCTCFG_TRIMDIV(config->trimConfig->trimDiv) | SCG_FIRCTCFG_TRIMSRC(config->trimConfig->trimSrc);
+
+        /* TODO: Write FIRCSTAT cause bus error: TKT266932. */
+        if (kSCG_FircTrimNonUpdate == config->trimConfig->trimMode)
+        {
+            SCG->FIRCSTAT = SCG_FIRCSTAT_TRIMCOAR(config->trimConfig->trimCoar) |
+                            SCG_FIRCSTAT_TRIMFINE(config->trimConfig->trimFine);
+        }
+
+        /* trim mode. */
+        SCG->FIRCCSR = config->trimConfig->trimMode;
+
+        if (SCG->FIRCCSR & SCG_FIRCCSR_FIRCERR_MASK)
+        {
+            return kStatus_Fail;
+        }
+    }
+
+    /* Step 4. Enable clock. */
+    SCG->FIRCCSR |= (SCG_FIRCCSR_FIRCEN_MASK | SCG_FIRCCSR_FIRCTREN_MASK | config->enableMode);
+
+    /* Step 5. Wait for FIRC clock to be valid. */
+    while (!(SCG->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK))
+    {
+    }
+
+    return kStatus_Success;
+}
+
+status_t CLOCK_DeinitFirc(void)
+{
+    uint32_t reg = SCG->FIRCCSR;
+
+    /* If clock is used by system, return error. */
+    if (reg & SCG_FIRCCSR_FIRCSEL_MASK)
+    {
+        return kStatus_SCG_Busy;
+    }
+
+    /* If configure register is locked, return error. */
+    if (reg & SCG_FIRCCSR_LK_MASK)
+    {
+        return kStatus_ReadOnly;
+    }
+
+    SCG->FIRCCSR = SCG_FIRCCSR_FIRCERR_MASK;
+
+    return kStatus_Success;
+}
+
+uint32_t CLOCK_GetFircFreq(void)
+{
+    static const uint32_t fircFreq[] = {
+        SCG_FIRC_FREQ0, SCG_FIRC_FREQ1, SCG_FIRC_FREQ2, SCG_FIRC_FREQ3,
+    };
+
+    if (SCG->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) /* FIRC is valid. */
+    {
+        return fircFreq[SCG_FIRCCFG_RANGE_VAL];
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+uint32_t CLOCK_GetFircAsyncFreq(scg_async_clk_t type)
+{
+    uint32_t fircFreq = CLOCK_GetFircFreq();
+    uint32_t divider = 0U;
+
+    /* Get divider. */
+    if (fircFreq)
+    {
+        switch (type)
+        {
+            case kSCG_AsyncDiv3Clk: /* FIRCDIV3_CLK. */
+                divider = SCG_FIRCDIV_FIRCDIV3_VAL;
+                break;
+            case kSCG_AsyncDiv2Clk: /* FIRCDIV2_CLK. */
+                divider = SCG_FIRCDIV_FIRCDIV2_VAL;
+                break;
+            case kSCG_AsyncDiv1Clk: /* FIRCDIV1_CLK. */
+                divider = SCG_FIRCDIV_FIRCDIV1_VAL;
+                break;
+            default:
+                break;
+        }
+    }
+    if (divider)
+    {
+        return fircFreq >> (divider - 1U);
+    }
+    else /* Output disabled. */
+    {
+        return 0U;
+    }
+}
+
+uint32_t CLOCK_GetRtcOscFreq(void)
+{
+    if (SCG->ROSCCSR & SCG_ROSCCSR_ROSCVLD_MASK) /* RTC OSC clock is valid. */
+    {
+        /* Please call CLOCK_SetXtal32Freq base on board setting before using RTC OSC clock. */
+        assert(g_xtal32Freq);
+        return g_xtal32Freq;
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+status_t CLOCK_InitLpFll(const scg_lpfll_config_t *config)
+{
+    assert(config);
+
+    status_t status;
+
+    /* De-init the LPFLL first. */
+    status = CLOCK_DeinitLpFll();
+
+    if (kStatus_Success != status)
+    {
+        return status;
+    }
+
+    /* Now start to set up LPFLL clock. */
+    /* Step 1. Setup dividers. */
+    SCG->LPFLLDIV = SCG_LPFLLDIV_LPFLLDIV1(config->div1) | SCG_LPFLLDIV_LPFLLDIV2(config->div2) |
+                    SCG_LPFLLDIV_LPFLLDIV3(config->div3);
+
+    /* Step 2. Set LPFLL configuration. */
+    SCG->LPFLLCFG = SCG_LPFLLCFG_FSEL(config->range);
+
+    /* Step 3. Set trimming configuration. */
+    if (config->trimConfig)
+    {
+        SCG->LPFLLTCFG = SCG_LPFLLTCFG_TRIMDIV(config->trimConfig->trimDiv) |
+                         SCG_LPFLLTCFG_TRIMSRC(config->trimConfig->trimSrc) |
+                         SCG_LPFLLTCFG_LOCKW2LSB(config->trimConfig->lockMode);
+
+        if (kSCG_LpFllTrimNonUpdate == config->trimConfig->trimMode)
+        {
+            SCG->LPFLLSTAT = config->trimConfig->trimValue;
+        }
+
+        /* Trim mode. */
+        SCG->LPFLLCSR = config->trimConfig->trimMode;
+
+        if (SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLERR_MASK)
+        {
+            return kStatus_Fail;
+        }
+    }
+
+    /* Step 4. Enable clock. */
+    SCG->LPFLLCSR |= (SCG_LPFLLCSR_LPFLLEN_MASK | config->enableMode);
+
+    /* Step 5. Wait for LPFLL clock to be valid. */
+    while (!(SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK))
+    {
+    }
+
+    /* Step 6. Wait for LPFLL trim lock. */
+    if ((config->trimConfig) && (kSCG_LpFllTrimUpdate == config->trimConfig->trimMode))
+    {
+        while (!(SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLTRMLOCK_MASK))
+        {
+        }
+    }
+
+    return kStatus_Success;
+}
+
+status_t CLOCK_DeinitLpFll(void)
+{
+    uint32_t reg = SCG->LPFLLCSR;
+
+    /* If clock is used by system, return error. */
+    if (reg & SCG_LPFLLCSR_LPFLLSEL_MASK)
+    {
+        return kStatus_SCG_Busy;
+    }
+
+    /* If configure register is locked, return error. */
+    if (reg & SCG_LPFLLCSR_LK_MASK)
+    {
+        return kStatus_ReadOnly;
+    }
+
+    SCG->LPFLLCSR = SCG_LPFLLCSR_LPFLLERR_MASK;
+
+    return kStatus_Success;
+}
+
+uint32_t CLOCK_GetLpFllFreq(void)
+{
+    static const uint32_t lpfllFreq[] = {
+        SCG_LPFLL_FREQ0, SCG_LPFLL_FREQ1, SCG_LPFLL_FREQ2, SCG_LPFLL_FREQ3,
+    };
+
+    if (SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK) /* LPFLL is valid. */
+    {
+        return lpfllFreq[SCG_LPFLLCFG_FSEL_VAL];
+    }
+    else
+    {
+        return 0U;
+    }
+}
+
+uint32_t CLOCK_GetLpFllAsyncFreq(scg_async_clk_t type)
+{
+    uint32_t lpfllFreq = CLOCK_GetLpFllFreq();
+    uint32_t divider = 0U;
+
+    /* Get divider. */
+    if (lpfllFreq)
+    {
+        switch (type)
+        {
+            case kSCG_AsyncDiv2Clk: /* LPFLLDIV2_CLK. */
+                divider = SCG_LPFLLDIV_LPFLLDIV2_VAL;
+                break;
+            case kSCG_AsyncDiv1Clk: /* LPFLLDIV1_CLK. */
+                divider = SCG_LPFLLDIV_LPFLLDIV1_VAL;
+                break;
+            default:
+                break;
+        }
+    }
+    if (divider)
+    {
+        return lpfllFreq >> (divider - 1U);
+    }
+    else /* Output disabled. */
+    {
+        return 0U;
+    }
+}

FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_common.c

@@ -0,0 +1,117 @@
+/*
+* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016 NXP
+* All rights reserved.
+*
+* 
+* SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+
+#ifndef NDEBUG
+#if (defined(__CC_ARM)) || (defined(__ICCARM__))
+void __aeabi_assert(const char *failedExpr, const char *file, int line)
+{
+    PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line);
+    for (;;)
+    {
+        __BKPT(0);
+    }
+}
+#elif(defined(__GNUC__))
+void __assert_func(const char *file, int line, const char *func, const char *failedExpr)
+{
+    PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, func);
+    for (;;)
+    {
+        __BKPT(0);
+    }
+}
+#endif /* (defined(__CC_ARM)) ||  (defined (__ICCARM__)) */
+#endif /* NDEBUG */
+
+#ifndef __GIC_PRIO_BITS
+#ifndef __riscv
+uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
+{
+/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
+#if defined(__CC_ARM)
+    extern uint32_t Image$$VECTOR_ROM$$Base[];
+    extern uint32_t Image$$VECTOR_RAM$$Base[];
+    extern uint32_t Image$$RW_m_data$$Base[];
+
+#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
+#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
+#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
+#elif defined(__ICCARM__)
+    extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
+    extern uint32_t __VECTOR_TABLE[];
+    extern uint32_t __VECTOR_RAM[];
+#elif defined(__GNUC__)
+    extern uint32_t __VECTOR_TABLE[];
+    extern uint32_t __VECTOR_RAM[];
+    extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
+    uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
+#endif /* defined(__CC_ARM) */
+    uint32_t n;
+    uint32_t ret;
+    uint32_t irqMaskValue;
+
+    irqMaskValue = DisableGlobalIRQ();
+    if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
+    {
+        /* Copy the vector table from ROM to RAM */
+        for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
+        {
+            __VECTOR_RAM[n] = __VECTOR_TABLE[n];
+        }
+        /* Point the VTOR to the position of vector table */
+        SCB->VTOR = (uint32_t)__VECTOR_RAM;
+    }
+
+    ret = __VECTOR_RAM[irq + 16];
+    /* make sure the __VECTOR_RAM is noncachable */
+    __VECTOR_RAM[irq + 16] = irqHandler;
+
+    EnableGlobalIRQ(irqMaskValue);
+
+    return ret;
+}
+#endif
+#endif
+
+#ifndef QN908XC_SERIES
+#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
+
+void EnableDeepSleepIRQ(IRQn_Type interrupt)
+{
+    uint32_t index = 0;
+    uint32_t intNumber = (uint32_t)interrupt;
+    while (intNumber >= 32u)
+    {
+        index++;
+        intNumber -= 32u;
+    }
+
+    SYSCON->STARTERSET[index] = 1u << intNumber;
+    EnableIRQ(interrupt); /* also enable interrupt at NVIC */
+}
+
+void DisableDeepSleepIRQ(IRQn_Type interrupt)
+{
+    uint32_t index = 0;
+    uint32_t intNumber = (uint32_t)interrupt;
+    while (intNumber >= 32u)
+    {
+        index++;
+        intNumber -= 32u;
+    }
+
+    DisableIRQ(interrupt); /* also disable interrupt at NVIC */
+    SYSCON->STARTERCLR[index] = 1u << intNumber;
+}
+#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
+
+#endif /* QN908XC_SERIES */

FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_common.h

@@ -0,0 +1,485 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ * 
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_COMMON_H_
+#define _FSL_COMMON_H_
+
+#include <assert.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
+
+#if defined(__ICCARM__)
+#include <stddef.h>
+#endif
+
+#include "fsl_device_registers.h"
+
+/*!
+ * @addtogroup ksdk_common
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Construct a status code value from a group and code number. */
+#define MAKE_STATUS(group, code) ((((group)*100) + (code)))
+
+/*! @brief Construct the version number for drivers. */
+#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief common driver version 2.0.0. */
+#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/* Debug console type definition. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U     /*!< No debug console.             */
+#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U     /*!< Debug console base on UART.   */
+#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U   /*!< Debug console base on LPUART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U    /*!< Debug console base on LPSCI.  */
+#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U   /*!< Debug console base on USBCDC. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console base on USBCDC. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U    /*!< Debug console base on i.MX UART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U   /*!< Debug console base on LPC_USART. */
+
+/*! @brief Status group numbers. */
+enum _status_groups
+{
+    kStatusGroup_Generic = 0,                 /*!< Group number for generic status codes. */
+    kStatusGroup_FLASH = 1,                   /*!< Group number for FLASH status codes. */
+    kStatusGroup_LPSPI = 4,                   /*!< Group number for LPSPI status codes. */
+    kStatusGroup_FLEXIO_SPI = 5,              /*!< Group number for FLEXIO SPI status codes. */
+    kStatusGroup_DSPI = 6,                    /*!< Group number for DSPI status codes. */
+    kStatusGroup_FLEXIO_UART = 7,             /*!< Group number for FLEXIO UART status codes. */
+    kStatusGroup_FLEXIO_I2C = 8,              /*!< Group number for FLEXIO I2C status codes. */
+    kStatusGroup_LPI2C = 9,                   /*!< Group number for LPI2C status codes. */
+    kStatusGroup_UART = 10,                   /*!< Group number for UART status codes. */
+    kStatusGroup_I2C = 11,                    /*!< Group number for UART status codes. */
+    kStatusGroup_LPSCI = 12,                  /*!< Group number for LPSCI status codes. */
+    kStatusGroup_LPUART = 13,                 /*!< Group number for LPUART status codes. */
+    kStatusGroup_SPI = 14,                    /*!< Group number for SPI status code.*/
+    kStatusGroup_XRDC = 15,                   /*!< Group number for XRDC status code.*/
+    kStatusGroup_SEMA42 = 16,                 /*!< Group number for SEMA42 status code.*/
+    kStatusGroup_SDHC = 17,                   /*!< Group number for SDHC status code */
+    kStatusGroup_SDMMC = 18,                  /*!< Group number for SDMMC status code */
+    kStatusGroup_SAI = 19,                    /*!< Group number for SAI status code */
+    kStatusGroup_MCG = 20,                    /*!< Group number for MCG status codes. */
+    kStatusGroup_SCG = 21,                    /*!< Group number for SCG status codes. */
+    kStatusGroup_SDSPI = 22,                  /*!< Group number for SDSPI status codes. */
+    kStatusGroup_FLEXIO_I2S = 23,             /*!< Group number for FLEXIO I2S status codes */
+    kStatusGroup_FLEXIO_MCULCD = 24,          /*!< Group number for FLEXIO LCD status codes */
+    kStatusGroup_FLASHIAP = 25,               /*!< Group number for FLASHIAP status codes */
+    kStatusGroup_FLEXCOMM_I2C = 26,           /*!< Group number for FLEXCOMM I2C status codes */
+    kStatusGroup_I2S = 27,                    /*!< Group number for I2S status codes */
+    kStatusGroup_IUART = 28,                  /*!< Group number for IUART status codes */
+    kStatusGroup_CSI = 29,                    /*!< Group number for CSI status codes */
+    kStatusGroup_SDRAMC = 35,                 /*!< Group number for SDRAMC status codes. */
+    kStatusGroup_POWER = 39,                  /*!< Group number for POWER status codes. */
+    kStatusGroup_ENET = 40,                   /*!< Group number for ENET status codes. */
+    kStatusGroup_PHY = 41,                    /*!< Group number for PHY status codes. */
+    kStatusGroup_TRGMUX = 42,                 /*!< Group number for TRGMUX status codes. */
+    kStatusGroup_SMARTCARD = 43,              /*!< Group number for SMARTCARD status codes. */
+    kStatusGroup_LMEM = 44,                   /*!< Group number for LMEM status codes. */
+    kStatusGroup_QSPI = 45,                   /*!< Group number for QSPI status codes. */
+    kStatusGroup_DMA = 50,                    /*!< Group number for DMA status codes. */
+    kStatusGroup_EDMA = 51,                   /*!< Group number for EDMA status codes. */
+    kStatusGroup_DMAMGR = 52,                 /*!< Group number for DMAMGR status codes. */
+    kStatusGroup_FLEXCAN = 53,                /*!< Group number for FlexCAN status codes. */
+    kStatusGroup_LTC = 54,                    /*!< Group number for LTC status codes. */
+    kStatusGroup_FLEXIO_CAMERA = 55,          /*!< Group number for FLEXIO CAMERA status codes. */
+    kStatusGroup_LPC_SPI = 56,                /*!< Group number for LPC_SPI status codes. */
+    kStatusGroup_LPC_USART = 57,              /*!< Group number for LPC_USART status codes. */
+    kStatusGroup_DMIC = 58,                   /*!< Group number for DMIC status codes. */
+    kStatusGroup_SDIF = 59,                   /*!< Group number for SDIF status codes.*/
+    kStatusGroup_SPIFI = 60,                  /*!< Group number for SPIFI status codes. */
+    kStatusGroup_OTP = 61,                    /*!< Group number for OTP status codes. */
+    kStatusGroup_MCAN = 62,                   /*!< Group number for MCAN status codes. */
+    kStatusGroup_CAAM = 63,                   /*!< Group number for CAAM status codes. */
+    kStatusGroup_ECSPI = 64,                  /*!< Group number for ECSPI status codes. */
+    kStatusGroup_USDHC = 65,                  /*!< Group number for USDHC status codes.*/
+    kStatusGroup_LPC_I2C = 66,                /*!< Group number for LPC_I2C status codes.*/
+    kStatusGroup_ESAI = 69,                   /*!< Group number for ESAI status codes. */
+    kStatusGroup_FLEXSPI = 70,                /*!< Group number for FLEXSPI status codes. */
+    kStatusGroup_MMDC = 71,                   /*!< Group number for MMDC status codes. */
+    kStatusGroup_MICFIL = 72,                 /*!< Group number for MIC status codes. */
+    kStatusGroup_SDMA = 73,                   /*!< Group number for SDMA status codes. */
+    kStatusGroup_ICS = 74,                    /*!< Group number for ICS status codes. */
+    kStatusGroup_NOTIFIER = 98,               /*!< Group number for NOTIFIER status codes. */
+    kStatusGroup_DebugConsole = 99,           /*!< Group number for debug console status codes. */
+    kStatusGroup_ApplicationRangeStart = 100, /*!< Starting number for application groups. */
+};
+
+/*! @brief Generic status return codes. */
+enum _generic_status
+{
+    kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0),
+    kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1),
+    kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2),
+    kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3),
+    kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4),
+    kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5),
+    kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6),
+};
+
+/*! @brief Type used for all status and error return values. */
+typedef int32_t status_t;
+
+/*
+ * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t
+ * defined in previous of this file.
+ */
+#include "fsl_clock.h"
+
+/*
+ * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral
+ */
+#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
+     (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
+#include "fsl_reset.h"
+#endif
+
+/*! @name Min/max macros */
+/* @{ */
+#if !defined(MIN)
+#define MIN(a, b) ((a) < (b) ? (a) : (b))
+#endif
+
+#if !defined(MAX)
+#define MAX(a, b) ((a) > (b) ? (a) : (b))
+#endif
+/* @} */
+
+/*! @brief Computes the number of elements in an array. */
+#if !defined(ARRAY_SIZE)
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+#endif
+
+/*! @name UINT16_MAX/UINT32_MAX value */
+/* @{ */
+#if !defined(UINT16_MAX)
+#define UINT16_MAX ((uint16_t)-1)
+#endif
+
+#if !defined(UINT32_MAX)
+#define UINT32_MAX ((uint32_t)-1)
+#endif
+/* @} */
+
+/*! @name Timer utilities */
+/* @{ */
+/*! Macro to convert a microsecond period to raw count value */
+#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U)
+/*! Macro to convert a raw count value to microsecond */
+#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz)
+
+/*! Macro to convert a millisecond period to raw count value */
+#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U)
+/*! Macro to convert a raw count value to millisecond */
+#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz)
+/* @} */
+
+/*! @name Alignment variable definition macros */
+/* @{ */
+#if (defined(__ICCARM__))
+/**
+ * Workaround to disable MISRA C message suppress warnings for IAR compiler.
+ * http://supp.iar.com/Support/?note=24725
+ */
+_Pragma("diag_suppress=Pm120")
+#define SDK_PRAGMA(x) _Pragma(#x)
+    _Pragma("diag_error=Pm120")
+/*! Macro to define a variable with alignbytes alignment */
+#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
+/*! Macro to define a variable with L1 d-cache line size alignment */
+#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
+#define SDK_L1DCACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var
+#endif
+/*! Macro to define a variable with L2 cache line size alignment */
+#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
+#define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var
+#endif
+#elif defined(__CC_ARM)
+/*! Macro to define a variable with alignbytes alignment */
+#define SDK_ALIGN(var, alignbytes) __align(alignbytes) var
+/*! Macro to define a variable with L1 d-cache line size alignment */
+#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
+#define SDK_L1DCACHE_ALIGN(var) __align(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var
+#endif
+/*! Macro to define a variable with L2 cache line size alignment */
+#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
+#define SDK_L2CACHE_ALIGN(var) __align(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var
+#endif
+#elif defined(__GNUC__)
+/*! Macro to define a variable with alignbytes alignment */
+#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
+/*! Macro to define a variable with L1 d-cache line size alignment */
+#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
+#define SDK_L1DCACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)))
+#endif
+/*! Macro to define a variable with L2 cache line size alignment */
+#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
+#define SDK_L2CACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)))
+#endif
+#else
+#error Toolchain not supported
+#define SDK_ALIGN(var, alignbytes) var
+#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
+#define SDK_L1DCACHE_ALIGN(var) var
+#endif
+#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
+#define SDK_L2CACHE_ALIGN(var) var
+#endif
+#endif
+
+/*! Macro to change a value to a given size aligned value */
+#define SDK_SIZEALIGN(var, alignbytes) \
+    ((unsigned int)((var) + ((alignbytes)-1)) & (unsigned int)(~(unsigned int)((alignbytes)-1)))
+/* @} */
+
+/*! @name Non-cacheable region definition macros */
+/* @{ */
+#if (defined(__ICCARM__))
+#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
+#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable"
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable"
+#else
+#define AT_NONCACHEABLE_SECTION(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
+#endif
+#elif(defined(__CC_ARM))
+#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
+#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"))) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
+    __attribute__((section("NonCacheable"), zero_init)) __align(alignbytes) var
+#else
+#define AT_NONCACHEABLE_SECTION(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __align(alignbytes) var
+#endif
+#elif(defined(__GNUC__))
+/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"
+ * in your projects to make sure the non-cacheable section variables will be initialized in system startup.
+ */
+#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
+#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"))) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
+    __attribute__((section("NonCacheable"))) var __attribute__((aligned(alignbytes)))
+#else
+#define AT_NONCACHEABLE_SECTION(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
+#endif
+#else
+#error Toolchain not supported.
+#define AT_NONCACHEABLE_SECTION(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var
+#endif
+/* @} */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Enable specific interrupt.
+ *
+ * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt
+ * levels. For example, there are NVIC and intmux. Here the interrupts connected
+ * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
+ * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
+ * to NVIC first then routed to core.
+ *
+ * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts
+ * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
+ *
+ * @param interrupt The IRQ number.
+ * @retval kStatus_Success Interrupt enabled successfully
+ * @retval kStatus_Fail Failed to enable the interrupt
+ */
+static inline status_t EnableIRQ(IRQn_Type interrupt)
+{
+    if (NotAvail_IRQn == interrupt)
+    {
+        return kStatus_Fail;
+    }
+
+#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
+    if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
+    {
+        return kStatus_Fail;
+    }
+#endif
+
+#if defined(FSL_FEATURE_SOC_EVENT_COUNT) && (FSL_FEATURE_SOC_EVENT_COUNT > 0)
+    EVENT_UNIT->INTPTEN |= (uint32_t)(1 << interrupt);
+    /* Read back to make sure write finished. */
+    (void)EVENT_UNIT->INTPTEN;
+#else
+#if defined(__GIC_PRIO_BITS)
+    GIC_EnableIRQ(interrupt);
+#else
+    NVIC_EnableIRQ(interrupt);
+#endif
+#endif
+    return kStatus_Success;
+}
+
+/*!
+ * @brief Disable specific interrupt.
+ *
+ * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt
+ * levels. For example, there are NVIC and intmux. Here the interrupts connected
+ * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
+ * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
+ * to NVIC first then routed to core.
+ *
+ * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts
+ * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
+ *
+ * @param interrupt The IRQ number.
+ * @retval kStatus_Success Interrupt disabled successfully
+ * @retval kStatus_Fail Failed to disable the interrupt
+ */
+static inline status_t DisableIRQ(IRQn_Type interrupt)
+{
+    if (NotAvail_IRQn == interrupt)
+    {
+        return kStatus_Fail;
+    }
+
+#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
+    if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
+    {
+        return kStatus_Fail;
+    }
+#endif
+
+#if defined(FSL_FEATURE_SOC_EVENT_COUNT) && (FSL_FEATURE_SOC_EVENT_COUNT > 0)
+    EVENT_UNIT->INTPTEN &= ~(uint32_t)(1 << interrupt);
+    /* Read back to make sure write finished. */
+    (void)EVENT_UNIT->INTPTEN;
+#else
+#if defined(__GIC_PRIO_BITS)
+    GIC_DisableIRQ(interrupt);
+#else
+    NVIC_DisableIRQ(interrupt);
+#endif
+#endif
+    return kStatus_Success;
+}
+
+/*!
+ * @brief Disable the global IRQ
+ *
+ * Disable the global interrupt and return the current primask register. User is required to provided the primask
+ * register for the EnableGlobalIRQ().
+ *
+ * @return Current primask value.
+ */
+static inline uint32_t DisableGlobalIRQ(void)
+{
+#ifndef __riscv
+#if defined(CPSR_I_Msk)
+    uint32_t cpsr = __get_CPSR() & CPSR_I_Msk;
+
+    __disable_irq();
+
+    return cpsr;
+#else
+    uint32_t regPrimask = __get_PRIMASK();
+
+    __disable_irq();
+
+    return regPrimask;
+#endif
+#else
+    uint32_t mstatus;
+
+    __ASM volatile ("csrrci %0, mstatus, 8" : "=r"(mstatus));
+
+    return mstatus;
+#endif
+}
+
+/*!
+ * @brief Enaable the global IRQ
+ *
+ * Set the primask register with the provided primask value but not just enable the primask. The idea is for the
+ * convinience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to
+ * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.
+ *
+ * @param primask value of primask register to be restored. The primask value is supposed to be provided by the
+ * DisableGlobalIRQ().
+ */
+static inline void EnableGlobalIRQ(uint32_t primask)
+{
+#ifndef __riscv
+#if defined(CPSR_I_Msk)
+    __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask);
+#else
+    __set_PRIMASK(primask);
+#endif
+#else
+    __ASM volatile ("csrw mstatus, %0" : : "r"(primask));
+#endif
+}
+
+/*!
+ * @brief install IRQ handler
+ *
+ * @param irq IRQ number
+ * @param irqHandler IRQ handler address
+ * @return The old IRQ handler address
+ */
+uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
+
+#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
+/*!
+ * @brief Enable specific interrupt for wake-up from deep-sleep mode.
+ *
+ * Enable the interrupt for wake-up from deep sleep mode.
+ * Some interrupts are typically used in sleep mode only and will not occur during
+ * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
+ * those clocks (significantly increasing power consumption in the reduced power mode),
+ * making these wake-ups possible.
+ *
+ * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internally).
+ *
+ * @param interrupt The IRQ number.
+ */
+void EnableDeepSleepIRQ(IRQn_Type interrupt);
+
+/*!
+ * @brief Disable specific interrupt for wake-up from deep-sleep mode.
+ *
+ * Disable the interrupt for wake-up from deep sleep mode.
+ * Some interrupts are typically used in sleep mode only and will not occur during
+ * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
+ * those clocks (significantly increasing power consumption in the reduced power mode),
+ * making these wake-ups possible.
+ *
+ * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internally).
+ *
+ * @param interrupt The IRQ number.
+ */
+void DisableDeepSleepIRQ(IRQn_Type interrupt);
+#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif /* _FSL_COMMON_H_ */

FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_gpio.c

@@ -0,0 +1,196 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ * 
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_gpio.h"
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+static PORT_Type *const s_portBases[] = PORT_BASE_PTRS;
+static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS;
+
+#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT
+
+#if defined(FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL) && FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Array to map FGPIO instance number to clock name. */
+static const clock_ip_name_t s_fgpioClockName[] = FGPIO_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#endif /* FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL */
+
+#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */
+
+/*******************************************************************************
+* Prototypes
+******************************************************************************/
+
+/*!
+* @brief Gets the GPIO instance according to the GPIO base
+*
+* @param base    GPIO peripheral base pointer(PTA, PTB, PTC, etc.)
+* @retval GPIO instance
+*/
+static uint32_t GPIO_GetInstance(GPIO_Type *base);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static uint32_t GPIO_GetInstance(GPIO_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_gpioBases); instance++)
+    {
+        if (s_gpioBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_gpioBases));
+
+    return instance;
+}
+
+void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config)
+{
+    assert(config);
+
+    if (config->pinDirection == kGPIO_DigitalInput)
+    {
+        base->PDDR &= ~(1U << pin);
+    }
+    else
+    {
+        GPIO_WritePinOutput(base, pin, config->outputLogic);
+        base->PDDR |= (1U << pin);
+    }
+}
+
+uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base)
+{
+    uint8_t instance;
+    PORT_Type *portBase;
+    instance = GPIO_GetInstance(base);
+    portBase = s_portBases[instance];
+    return portBase->ISFR;
+}
+
+void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask)
+{
+    uint8_t instance;
+    PORT_Type *portBase;
+    instance = GPIO_GetInstance(base);
+    portBase = s_portBases[instance];
+    portBase->ISFR = mask;
+}
+
+#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER
+void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribute)
+{
+    base->GACR = ((uint32_t)attribute << GPIO_GACR_ACB0_SHIFT) | ((uint32_t)attribute << GPIO_GACR_ACB1_SHIFT) |
+                 ((uint32_t)attribute << GPIO_GACR_ACB2_SHIFT) | ((uint32_t)attribute << GPIO_GACR_ACB3_SHIFT);
+}
+#endif
+
+#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+static FGPIO_Type *const s_fgpioBases[] = FGPIO_BASE_PTRS;
+
+/*******************************************************************************
+* Prototypes
+******************************************************************************/
+/*!
+* @brief Gets the FGPIO instance according to the GPIO base
+*
+* @param base    FGPIO peripheral base pointer(PTA, PTB, PTC, etc.)
+* @retval FGPIO instance
+*/
+static uint32_t FGPIO_GetInstance(FGPIO_Type *base);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static uint32_t FGPIO_GetInstance(FGPIO_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_fgpioBases); instance++)
+    {
+        if (s_fgpioBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_fgpioBases));
+
+    return instance;
+}
+
+#if defined(FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL) && FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL
+void FGPIO_Init(FGPIO_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Ungate FGPIO periphral clock */
+    CLOCK_EnableClock(s_fgpioClockName[FGPIO_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+#endif /* FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL */
+
+void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config)
+{
+    assert(config);
+
+    if (config->pinDirection == kGPIO_DigitalInput)
+    {
+        base->PDDR &= ~(1U << pin);
+    }
+    else
+    {
+        FGPIO_WritePinOutput(base, pin, config->outputLogic);
+        base->PDDR |= (1U << pin);
+    }
+}
+
+uint32_t FGPIO_GetPinsInterruptFlags(FGPIO_Type *base)
+{
+    uint8_t instance;
+    instance = FGPIO_GetInstance(base);
+    PORT_Type *portBase;
+    portBase = s_portBases[instance];
+    return portBase->ISFR;
+}
+
+void FGPIO_ClearPinsInterruptFlags(FGPIO_Type *base, uint32_t mask)
+{
+    uint8_t instance;
+    instance = FGPIO_GetInstance(base);
+    PORT_Type *portBase;
+    portBase = s_portBases[instance];
+    portBase->ISFR = mask;
+}
+
+#if defined(FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER
+void FGPIO_CheckAttributeBytes(FGPIO_Type *base, gpio_checker_attribute_t attribute)
+{
+    base->GACR = (attribute << FGPIO_GACR_ACB0_SHIFT) | (attribute << FGPIO_GACR_ACB1_SHIFT) |
+                 (attribute << FGPIO_GACR_ACB2_SHIFT) | (attribute << FGPIO_GACR_ACB3_SHIFT);
+}
+#endif
+
+#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */

FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_gpio.h

@@ -0,0 +1,427 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ * 
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_GPIO_H_
+#define _FSL_GPIO_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup gpio
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief GPIO driver version 2.2.0. */
+#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
+/*@}*/
+
+/*! @brief GPIO direction definition */
+typedef enum _gpio_pin_direction
+{
+    kGPIO_DigitalInput = 0U,  /*!< Set current pin as digital input*/
+    kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/
+} gpio_pin_direction_t;
+
+#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER
+/*! @brief GPIO checker attribute */
+typedef enum _gpio_checker_attribute
+{
+    kGPIO_UsernonsecureRWUsersecureRWPrivilegedsecureRW =
+        0x00U, /*!< User nonsecure:Read+Write; User Secure:Read+Write; Privileged Secure:Read+Write */
+    kGPIO_UsernonsecureRUsersecureRWPrivilegedsecureRW =
+        0x01U, /*!< User nonsecure:Read;       User Secure:Read+Write; Privileged Secure:Read+Write */
+    kGPIO_UsernonsecureNUsersecureRWPrivilegedsecureRW =
+        0x02U, /*!< User nonsecure:None;       User Secure:Read+Write; Privileged Secure:Read+Write */
+    kGPIO_UsernonsecureRUsersecureRPrivilegedsecureRW =
+        0x03U, /*!< User nonsecure:Read;       User Secure:Read;       Privileged Secure:Read+Write */
+    kGPIO_UsernonsecureNUsersecureRPrivilegedsecureRW =
+        0x04U, /*!< User nonsecure:None;       User Secure:Read;       Privileged Secure:Read+Write */
+    kGPIO_UsernonsecureNUsersecureNPrivilegedsecureRW =
+        0x05U, /*!< User nonsecure:None;       User Secure:None;       Privileged Secure:Read+Write */
+    kGPIO_UsernonsecureNUsersecureNPrivilegedsecureR =
+        0x06U, /*!< User nonsecure:None;       User Secure:None;       Privileged Secure:Read */
+    kGPIO_UsernonsecureNUsersecureNPrivilegedsecureN =
+        0x07U, /*!< User nonsecure:None;       User Secure:None;       Privileged Secure:None */
+    kGPIO_IgnoreAttributeCheck = 0x80U, /*!< Ignores the attribute check */
+} gpio_checker_attribute_t;
+#endif
+
+/*!
+ * @brief The GPIO pin configuration structure.
+ *
+ * Each pin can only be configured as either an output pin or an input pin at a time.
+ * If configured as an input pin, leave the outputConfig unused.
+ * Note that in some use cases, the corresponding port property should be configured in advance
+ *        with the PORT_SetPinConfig().
+ */
+typedef struct _gpio_pin_config
+{
+    gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */
+    /* Output configurations; ignore if configured as an input pin */
+    uint8_t outputLogic; /*!< Set a default output logic, which has no use in input */
+} gpio_pin_config_t;
+
+/*! @} */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @addtogroup gpio_driver
+ * @{
+ */
+
+/*! @name GPIO Configuration */
+/*@{*/
+
+/*!
+ * @brief Initializes a GPIO pin used by the board.
+ *
+ * To initialize the GPIO, define a pin configuration, as either input or output, in the user file.
+ * Then, call the GPIO_PinInit() function.
+ *
+ * This is an example to define an input pin or an output pin configuration.
+ * @code
+ * // Define a digital input pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ *   kGPIO_DigitalInput,
+ *   0,
+ * }
+ * //Define a digital output pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ *   kGPIO_DigitalOutput,
+ *   0,
+ * }
+ * @endcode
+ *
+ * @param base   GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param pin    GPIO port pin number
+ * @param config GPIO pin configuration pointer
+ */
+void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config);
+
+/*@}*/
+
+/*! @name GPIO Output Operations */
+/*@{*/
+
+/*!
+ * @brief Sets the output level of the multiple GPIO pins to the logic 1 or 0.
+ *
+ * @param base    GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param pin     GPIO pin number
+ * @param output  GPIO pin output logic level.
+ *        - 0: corresponding pin output low-logic level.
+ *        - 1: corresponding pin output high-logic level.
+ */
+static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t pin, uint8_t output)
+{
+    if (output == 0U)
+    {
+        base->PCOR = 1U << pin;
+    }
+    else
+    {
+        base->PSOR = 1U << pin;
+    }
+}
+
+/*!
+ * @brief Sets the output level of the multiple GPIO pins to the logic 1.
+ *
+ * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t mask)
+{
+    base->PSOR = mask;
+}
+
+/*!
+ * @brief Sets the output level of the multiple GPIO pins to the logic 0.
+ *
+ * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t mask)
+{
+    base->PCOR = mask;
+}
+
+/*!
+ * @brief Reverses the current output logic of the multiple GPIO pins.
+ *
+ * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_TogglePinsOutput(GPIO_Type *base, uint32_t mask)
+{
+    base->PTOR = mask;
+}
+/*@}*/
+
+/*! @name GPIO Input Operations */
+/*@{*/
+
+/*!
+ * @brief Reads the current input value of the GPIO port.
+ *
+ * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param pin     GPIO pin number
+ * @retval GPIO port input value
+ *        - 0: corresponding pin input low-logic level.
+ *        - 1: corresponding pin input high-logic level.
+ */
+static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t pin)
+{
+    return (((base->PDIR) >> pin) & 0x01U);
+}
+/*@}*/
+
+/*! @name GPIO Interrupt */
+/*@{*/
+
+/*!
+ * @brief Reads the GPIO port interrupt status flag.
+ *
+ * If a pin is configured to generate the DMA request, the corresponding flag
+ * is cleared automatically at the completion of the requested DMA transfer.
+ * Otherwise, the flag remains set until a logic one is written to that flag.
+ * If configured for a level sensitive interrupt that remains asserted, the flag
+ * is set again immediately.
+ *
+ * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @retval The current GPIO port interrupt status flag, for example, 0x00010001 means the
+ *         pin 0 and 17 have the interrupt.
+ */
+uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base);
+
+/*!
+ * @brief Clears multiple GPIO pin interrupt status flags.
+ *
+ * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param mask GPIO pin number macro
+ */
+void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask);
+
+#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER
+/*!
+ * @brief The GPIO module supports a device-specific number of data ports, organized as 32-bit
+ * words. Each 32-bit data port includes a GACR register, which defines the byte-level
+ * attributes required for a successful access to the GPIO programming model. The attribute controls for the 4 data
+ * bytes in the GACR follow a standard little endian
+ * data convention.
+ *
+ * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param mask GPIO pin number macro
+ */
+void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribute);
+#endif
+
+/*@}*/
+/*! @} */
+
+/*!
+ * @addtogroup fgpio_driver
+ * @{
+ */
+
+/*
+ * Introduces the FGPIO feature.
+ *
+ * The FGPIO features are only support on some Kinetis MCUs. The FGPIO registers are aliased to the IOPORT
+ * interface. Accesses via the IOPORT interface occur in parallel with any instruction fetches and
+ * complete in a single cycle. This aliased Fast GPIO memory map is called FGPIO.
+ */
+
+#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT
+
+/*! @name FGPIO Configuration */
+/*@{*/
+
+/*!
+ * @brief Initializes the FGPIO peripheral.
+ *
+ * This function ungates the FGPIO clock.
+ *
+ * @param base   FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ */
+ void FGPIO_Init(FGPIO_Type *base);
+
+/*!
+ * @brief Initializes a FGPIO pin used by the board.
+ *
+ * To initialize the FGPIO driver, define a pin configuration, as either input or output, in the user file.
+ * Then, call the FGPIO_PinInit() function.
+ *
+ * This is an example to define an input pin or an output pin configuration:
+ * @code
+ * // Define a digital input pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ *   kGPIO_DigitalInput,
+ *   0,
+ * }
+ * //Define a digital output pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ *   kGPIO_DigitalOutput,
+ *   0,
+ * }
+ * @endcode
+ *
+ * @param base   FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ * @param pin    FGPIO port pin number
+ * @param config FGPIO pin configuration pointer
+ */
+void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config);
+
+/*@}*/
+
+/*! @name FGPIO Output Operations */
+/*@{*/
+
+/*!
+ * @brief Sets the output level of the multiple FGPIO pins to the logic 1 or 0.
+ *
+ * @param base    FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ * @param pin     FGPIO pin number
+ * @param output  FGPIOpin output logic level.
+ *        - 0: corresponding pin output low-logic level.
+ *        - 1: corresponding pin output high-logic level.
+ */
+static inline void FGPIO_WritePinOutput(FGPIO_Type *base, uint32_t pin, uint8_t output)
+{
+    if (output == 0U)
+    {
+        base->PCOR = 1 << pin;
+    }
+    else
+    {
+        base->PSOR = 1 << pin;
+    }
+}
+
+/*!
+ * @brief Sets the output level of the multiple FGPIO pins to the logic 1.
+ *
+ * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ * @param mask FGPIO pin number macro
+ */
+static inline void FGPIO_SetPinsOutput(FGPIO_Type *base, uint32_t mask)
+{
+    base->PSOR = mask;
+}
+
+/*!
+ * @brief Sets the output level of the multiple FGPIO pins to the logic 0.
+ *
+ * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ * @param mask FGPIO pin number macro
+ */
+static inline void FGPIO_ClearPinsOutput(FGPIO_Type *base, uint32_t mask)
+{
+    base->PCOR = mask;
+}
+
+/*!
+ * @brief Reverses the current output logic of the multiple FGPIO pins.
+ *
+ * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ * @param mask FGPIO pin number macro
+ */
+static inline void FGPIO_TogglePinsOutput(FGPIO_Type *base, uint32_t mask)
+{
+    base->PTOR = mask;
+}
+/*@}*/
+
+/*! @name FGPIO Input Operations */
+/*@{*/
+
+/*!
+ * @brief Reads the current input value of the FGPIO port.
+ *
+ * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ * @param pin  FGPIO pin number
+ * @retval FGPIO port input value
+ *        - 0: corresponding pin input low-logic level.
+ *        - 1: corresponding pin input high-logic level.
+ */
+static inline uint32_t FGPIO_ReadPinInput(FGPIO_Type *base, uint32_t pin)
+{
+    return (((base->PDIR) >> pin) & 0x01U);
+}
+/*@}*/
+
+/*! @name FGPIO Interrupt */
+/*@{*/
+
+/*!
+ * @brief Reads the FGPIO port interrupt status flag.
+ *
+ * If a pin is configured to generate the DMA request, the corresponding flag
+ * is cleared automatically at the completion of the requested DMA transfer.
+ * Otherwise, the flag remains set until a logic one is written to that flag.
+ * If configured for a level-sensitive interrupt that remains asserted, the flag
+ * is set again immediately.
+ *
+ * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ * @retval The current FGPIO port interrupt status flags, for example, 0x00010001 means the
+ *         pin 0 and 17 have the interrupt.
+ */
+uint32_t FGPIO_GetPinsInterruptFlags(FGPIO_Type *base);
+
+/*!
+ * @brief Clears the multiple FGPIO pin interrupt status flag.
+ *
+ * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ * @param mask FGPIO pin number macro
+ */
+void FGPIO_ClearPinsInterruptFlags(FGPIO_Type *base, uint32_t mask);
+
+#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER
+/*!
+ * @brief The FGPIO module supports a device-specific number of data ports, organized as 32-bit
+ * words. Each 32-bit data port includes a GACR register, which defines the byte-level
+ * attributes required for a successful access to the GPIO programming model. The attribute controls for the 4 data
+ * bytes in the GACR follow a standard little endian
+ * data convention.
+ *
+ * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
+ * @param mask FGPIO pin number macro
+ */
+void FGPIO_CheckAttributeBytes(FGPIO_Type *base, gpio_checker_attribute_t attribute);
+#endif
+
+/*@}*/
+
+#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+
+#endif /* _FSL_GPIO_H_*/

FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_lpuart.h

@@ -0,0 +1,842 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ * 
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_LPUART_H_
+#define _FSL_LPUART_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup lpuart_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief LPUART driver version 2.2.3. */
+#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 2, 4))
+/*@}*/
+
+/*! @brief Error codes for the LPUART driver. */
+enum _lpuart_status
+{
+    kStatus_LPUART_TxBusy = MAKE_STATUS(kStatusGroup_LPUART, 0),                  /*!< TX busy */
+    kStatus_LPUART_RxBusy = MAKE_STATUS(kStatusGroup_LPUART, 1),                  /*!< RX busy */
+    kStatus_LPUART_TxIdle = MAKE_STATUS(kStatusGroup_LPUART, 2),                  /*!< LPUART transmitter is idle. */
+    kStatus_LPUART_RxIdle = MAKE_STATUS(kStatusGroup_LPUART, 3),                  /*!< LPUART receiver is idle. */
+    kStatus_LPUART_TxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 4),     /*!< TX FIFO watermark too large  */
+    kStatus_LPUART_RxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 5),     /*!< RX FIFO watermark too large  */
+    kStatus_LPUART_FlagCannotClearManually = MAKE_STATUS(kStatusGroup_LPUART, 6), /*!< Some flag can't manually clear */
+    kStatus_LPUART_Error = MAKE_STATUS(kStatusGroup_LPUART, 7),                   /*!< Error happens on LPUART. */
+    kStatus_LPUART_RxRingBufferOverrun =
+        MAKE_STATUS(kStatusGroup_LPUART, 8), /*!< LPUART RX software ring buffer overrun. */
+    kStatus_LPUART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_LPUART, 9), /*!< LPUART RX receiver overrun. */
+    kStatus_LPUART_NoiseError = MAKE_STATUS(kStatusGroup_LPUART, 10),       /*!< LPUART noise error. */
+    kStatus_LPUART_FramingError = MAKE_STATUS(kStatusGroup_LPUART, 11),     /*!< LPUART framing error. */
+    kStatus_LPUART_ParityError = MAKE_STATUS(kStatusGroup_LPUART, 12),      /*!< LPUART parity error. */
+    kStatus_LPUART_BaudrateNotSupport =
+        MAKE_STATUS(kStatusGroup_LPUART, 13), /*!< Baudrate is not support in current clock source */
+    kStatus_LPUART_IdleLineDetected = MAKE_STATUS(kStatusGroup_LPUART, 14), /*!< IDLE flag. */
+};
+
+/*! @brief LPUART parity mode. */
+typedef enum _lpuart_parity_mode
+{
+    kLPUART_ParityDisabled = 0x0U, /*!< Parity disabled */
+    kLPUART_ParityEven = 0x2U,     /*!< Parity enabled, type even, bit setting: PE|PT = 10 */
+    kLPUART_ParityOdd = 0x3U,      /*!< Parity enabled, type odd,  bit setting: PE|PT = 11 */
+} lpuart_parity_mode_t;
+
+/*! @brief LPUART data bits count. */
+typedef enum _lpuart_data_bits
+{
+    kLPUART_EightDataBits = 0x0U, /*!< Eight data bit */
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+    kLPUART_SevenDataBits = 0x1U, /*!< Seven data bit */
+#endif
+} lpuart_data_bits_t;
+
+/*! @brief LPUART stop bit count. */
+typedef enum _lpuart_stop_bit_count
+{
+    kLPUART_OneStopBit = 0U, /*!< One stop bit */
+    kLPUART_TwoStopBit = 1U, /*!< Two stop bits */
+} lpuart_stop_bit_count_t;
+
+#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT
+/*! @brief LPUART transmit CTS source. */
+typedef enum _lpuart_transmit_cts_source
+{
+    kLPUART_CtsSourcePin = 0U,         /*!< CTS resource is the LPUART_CTS pin. */
+    kLPUART_CtsSourceMatchResult = 1U, /*!< CTS resource is the match result. */
+} lpuart_transmit_cts_source_t;
+
+/*! @brief LPUART transmit CTS configure. */
+typedef enum _lpuart_transmit_cts_config
+{
+    kLPUART_CtsSampleAtStart = 0U, /*!< CTS input is sampled at the start of each character. */
+    kLPUART_CtsSampleAtIdle = 1U,  /*!< CTS input is sampled when the transmitter is idle */
+} lpuart_transmit_cts_config_t;
+#endif
+
+/*! @brief LPUART idle flag type defines when the receiver starts counting. */
+typedef enum _lpuart_idle_type_select
+{
+    kLPUART_IdleTypeStartBit = 0U, /*!< Start counting after a valid start bit. */
+    kLPUART_IdleTypeStopBit = 1U,  /*!< Start conuting after a stop bit. */
+} lpuart_idle_type_select_t;
+
+/*! @brief LPUART idle detected configuration.
+ *  This structure defines the number of idle characters that must be received before
+ *  the IDLE flag is set.
+ */
+typedef enum _lpuart_idle_config
+{
+    kLPUART_IdleCharacter1 = 0U,   /*!< the number of idle characters. */
+    kLPUART_IdleCharacter2 = 1U,   /*!< the number of idle characters. */
+    kLPUART_IdleCharacter4 = 2U,   /*!< the number of idle characters. */
+    kLPUART_IdleCharacter8 = 3U,   /*!< the number of idle characters. */
+    kLPUART_IdleCharacter16 = 4U,  /*!< the number of idle characters. */
+    kLPUART_IdleCharacter32 = 5U,  /*!< the number of idle characters. */
+    kLPUART_IdleCharacter64 = 6U,  /*!< the number of idle characters. */
+    kLPUART_IdleCharacter128 = 7U, /*!< the number of idle characters. */
+} lpuart_idle_config_t;
+
+/*!
+ * @brief LPUART interrupt configuration structure, default settings all disabled.
+ *
+ * This structure contains the settings for all LPUART interrupt configurations.
+ */
+enum _lpuart_interrupt_enable
+{
+#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
+    kLPUART_LinBreakInterruptEnable = (LPUART_BAUD_LBKDIE_MASK >> 8), /*!< LIN break detect. */
+#endif
+    kLPUART_RxActiveEdgeInterruptEnable = (LPUART_BAUD_RXEDGIE_MASK >> 8), /*!< Receive Active Edge. */
+    kLPUART_TxDataRegEmptyInterruptEnable = (LPUART_CTRL_TIE_MASK),        /*!< Transmit data register empty. */
+    kLPUART_TransmissionCompleteInterruptEnable = (LPUART_CTRL_TCIE_MASK), /*!< Transmission complete. */
+    kLPUART_RxDataRegFullInterruptEnable = (LPUART_CTRL_RIE_MASK),         /*!< Receiver data register full. */
+    kLPUART_IdleLineInterruptEnable = (LPUART_CTRL_ILIE_MASK),             /*!< Idle line. */
+    kLPUART_RxOverrunInterruptEnable = (LPUART_CTRL_ORIE_MASK),            /*!< Receiver Overrun. */
+    kLPUART_NoiseErrorInterruptEnable = (LPUART_CTRL_NEIE_MASK),           /*!< Noise error flag. */
+    kLPUART_FramingErrorInterruptEnable = (LPUART_CTRL_FEIE_MASK),         /*!< Framing error flag. */
+    kLPUART_ParityErrorInterruptEnable = (LPUART_CTRL_PEIE_MASK),          /*!< Parity error flag. */
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+    kLPUART_TxFifoOverflowInterruptEnable = (LPUART_FIFO_TXOFE_MASK >> 8),  /*!< Transmit FIFO Overflow. */
+    kLPUART_RxFifoUnderflowInterruptEnable = (LPUART_FIFO_RXUFE_MASK >> 8), /*!< Receive FIFO Underflow. */
+#endif
+};
+
+/*!
+ * @brief LPUART status flags.
+ *
+ * This provides constants for the LPUART status flags for use in the LPUART functions.
+ */
+enum _lpuart_flags
+{
+    kLPUART_TxDataRegEmptyFlag =
+        (LPUART_STAT_TDRE_MASK), /*!< Transmit data register empty flag, sets when transmit buffer is empty */
+    kLPUART_TransmissionCompleteFlag =
+        (LPUART_STAT_TC_MASK), /*!< Transmission complete flag, sets when transmission activity complete */
+    kLPUART_RxDataRegFullFlag =
+        (LPUART_STAT_RDRF_MASK), /*!< Receive data register full flag, sets when the receive data buffer is full */
+    kLPUART_IdleLineFlag = (LPUART_STAT_IDLE_MASK), /*!< Idle line detect flag, sets when idle line detected */
+    kLPUART_RxOverrunFlag = (LPUART_STAT_OR_MASK),  /*!< Receive Overrun, sets when new data is received before data is
+                                                       read from receive register */
+    kLPUART_NoiseErrorFlag = (LPUART_STAT_NF_MASK), /*!< Receive takes 3 samples of each received bit.  If any of these
+                                                       samples differ, noise flag sets */
+    kLPUART_FramingErrorFlag =
+        (LPUART_STAT_FE_MASK), /*!< Frame error flag, sets if logic 0 was detected where stop bit expected */
+    kLPUART_ParityErrorFlag = (LPUART_STAT_PF_MASK), /*!< If parity enabled, sets upon parity error detection */
+#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
+    kLPUART_LinBreakFlag = (LPUART_STAT_LBKDIF_MASK), /*!< LIN break detect interrupt flag, sets when LIN break char
+                                                         detected and LIN circuit enabled */
+#endif
+    kLPUART_RxActiveEdgeFlag =
+        (LPUART_STAT_RXEDGIF_MASK), /*!< Receive pin active edge interrupt flag, sets when active edge detected */
+    kLPUART_RxActiveFlag =
+        (LPUART_STAT_RAF_MASK), /*!< Receiver Active Flag (RAF), sets at beginning of valid start bit */
+#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
+    kLPUART_DataMatch1Flag = LPUART_STAT_MA1F_MASK, /*!< The next character to be read from LPUART_DATA matches MA1*/
+    kLPUART_DataMatch2Flag = LPUART_STAT_MA2F_MASK, /*!< The next character to be read from LPUART_DATA matches MA2*/
+#endif
+#if defined(FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS) && FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS
+    kLPUART_NoiseErrorInRxDataRegFlag =
+        (LPUART_DATA_NOISY_MASK >> 10), /*!< NOISY bit, sets if noise detected in current data word */
+    kLPUART_ParityErrorInRxDataRegFlag =
+        (LPUART_DATA_PARITYE_MASK >> 10), /*!< PARITYE bit, sets if noise detected in current data word */
+#endif
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+    kLPUART_TxFifoEmptyFlag = (LPUART_FIFO_TXEMPT_MASK >> 16), /*!< TXEMPT bit, sets if transmit buffer is empty */
+    kLPUART_RxFifoEmptyFlag = (LPUART_FIFO_RXEMPT_MASK >> 16), /*!< RXEMPT bit, sets if receive buffer is empty */
+    kLPUART_TxFifoOverflowFlag =
+        (LPUART_FIFO_TXOF_MASK >> 16), /*!< TXOF bit, sets if transmit buffer overflow occurred */
+    kLPUART_RxFifoUnderflowFlag =
+        (LPUART_FIFO_RXUF_MASK >> 16), /*!< RXUF bit, sets if receive buffer underflow occurred */
+#endif
+};
+
+/*! @brief LPUART configuration structure. */
+typedef struct _lpuart_config
+{
+    uint32_t baudRate_Bps;            /*!< LPUART baud rate  */
+    lpuart_parity_mode_t parityMode;  /*!< Parity mode, disabled (default), even, odd */
+    lpuart_data_bits_t dataBitsCount; /*!< Data bits count, eight (default), seven */
+    bool isMsb;                       /*!< Data bits order, LSB (default), MSB */
+#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT
+    lpuart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits  */
+#endif
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+    uint8_t txFifoWatermark; /*!< TX FIFO watermark */
+    uint8_t rxFifoWatermark; /*!< RX FIFO watermark */
+#endif
+#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT
+    bool enableRxRTS;                         /*!< RX RTS enable */
+    bool enableTxCTS;                         /*!< TX CTS enable */
+    lpuart_transmit_cts_source_t txCtsSource; /*!< TX CTS source */
+    lpuart_transmit_cts_config_t txCtsConfig; /*!< TX CTS configure */
+#endif
+    lpuart_idle_type_select_t rxIdleType; /*!< RX IDLE type. */
+    lpuart_idle_config_t rxIdleConfig;    /*!< RX IDLE configuration. */
+    bool enableTx;                        /*!< Enable TX */
+    bool enableRx;                        /*!< Enable RX */
+} lpuart_config_t;
+
+/*! @brief LPUART transfer structure. */
+typedef struct _lpuart_transfer
+{
+    uint8_t *data;   /*!< The buffer of data to be transfer.*/
+    size_t dataSize; /*!< The byte count to be transfer. */
+} lpuart_transfer_t;
+
+/* Forward declaration of the handle typedef. */
+typedef struct _lpuart_handle lpuart_handle_t;
+
+/*! @brief LPUART transfer callback function. */
+typedef void (*lpuart_transfer_callback_t)(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *userData);
+
+/*! @brief LPUART handle structure. */
+struct _lpuart_handle
+{
+    uint8_t *volatile txData;   /*!< Address of remaining data to send. */
+    volatile size_t txDataSize; /*!< Size of the remaining data to send. */
+    size_t txDataSizeAll;       /*!< Size of the data to send out. */
+    uint8_t *volatile rxData;   /*!< Address of remaining data to receive. */
+    volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */
+    size_t rxDataSizeAll;       /*!< Size of the data to receive. */
+
+    uint8_t *rxRingBuffer;              /*!< Start address of the receiver ring buffer. */
+    size_t rxRingBufferSize;            /*!< Size of the ring buffer. */
+    volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */
+    volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */
+
+    lpuart_transfer_callback_t callback; /*!< Callback function. */
+    void *userData;                      /*!< LPUART callback function parameter.*/
+
+    volatile uint8_t txState; /*!< TX transfer state. */
+    volatile uint8_t rxState; /*!< RX transfer state. */
+
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+    bool isSevenDataBits; /*!< Seven data bits flag. */
+#endif
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+
+#if defined(FSL_FEATURE_LPUART_HAS_GLOBAL) && FSL_FEATURE_LPUART_HAS_GLOBAL
+
+/*!
+ * @name Software Reset
+ * @{
+ */
+
+/*!
+ * @brief Resets the LPUART using software.
+ *
+ * This function resets all internal logic and registers except the Global Register.
+ * Remains set until cleared by software.
+ *
+ * @param base LPUART peripheral base address.
+ */
+static inline void LPUART_SoftwareReset(LPUART_Type *base)
+{
+    base->GLOBAL |= LPUART_GLOBAL_RST_MASK;
+    base->GLOBAL &= ~LPUART_GLOBAL_RST_MASK;
+}
+/* @} */
+#endif /*FSL_FEATURE_LPUART_HAS_GLOBAL*/
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes an LPUART instance with the user configuration structure and the peripheral clock.
+ *
+ * This function configures the LPUART module with user-defined settings. Call the LPUART_GetDefaultConfig() function
+ * to configure the configuration structure and get the default configuration.
+ * The example below shows how to use this API to configure the LPUART.
+ * @code
+ *  lpuart_config_t lpuartConfig;
+ *  lpuartConfig.baudRate_Bps = 115200U;
+ *  lpuartConfig.parityMode = kLPUART_ParityDisabled;
+ *  lpuartConfig.dataBitsCount = kLPUART_EightDataBits;
+ *  lpuartConfig.isMsb = false;
+ *  lpuartConfig.stopBitCount = kLPUART_OneStopBit;
+ *  lpuartConfig.txFifoWatermark = 0;
+ *  lpuartConfig.rxFifoWatermark = 1;
+ *  LPUART_Init(LPUART1, &lpuartConfig, 20000000U);
+ * @endcode
+ *
+ * @param base LPUART peripheral base address.
+ * @param config Pointer to a user-defined configuration structure.
+ * @param srcClock_Hz LPUART clock source frequency in HZ.
+ * @retval kStatus_LPUART_BaudrateNotSupport Baudrate is not support in current clock source.
+ * @retval kStatus_Success LPUART initialize succeed
+ */
+status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz);
+
+/*!
+ * @brief Deinitializes a LPUART instance.
+ *
+ * This function waits for transmit to complete, disables TX and RX, and disables the LPUART clock.
+ *
+ * @param base LPUART peripheral base address.
+ */
+void LPUART_Deinit(LPUART_Type *base);
+
+/*!
+ * @brief Gets the default configuration structure.
+ *
+ * This function initializes the LPUART configuration structure to a default value. The default
+ * values are:
+ *   lpuartConfig->baudRate_Bps = 115200U;
+ *   lpuartConfig->parityMode = kLPUART_ParityDisabled;
+ *   lpuartConfig->dataBitsCount = kLPUART_EightDataBits;
+ *   lpuartConfig->isMsb = false;
+ *   lpuartConfig->stopBitCount = kLPUART_OneStopBit;
+ *   lpuartConfig->txFifoWatermark = 0;
+ *   lpuartConfig->rxFifoWatermark = 1;
+ *   lpuartConfig->rxIdleType = kLPUART_IdleTypeStartBit;
+ *   lpuartConfig->rxIdleConfig = kLPUART_IdleCharacter1;
+ *   lpuartConfig->enableTx = false;
+ *   lpuartConfig->enableRx = false;
+ *
+ * @param config Pointer to a configuration structure.
+ */
+void LPUART_GetDefaultConfig(lpuart_config_t *config);
+
+/*!
+ * @brief Sets the LPUART instance baudrate.
+ *
+ * This function configures the LPUART module baudrate. This function is used to update
+ * the LPUART module baudrate after the LPUART module is initialized by the LPUART_Init.
+ * @code
+ *  LPUART_SetBaudRate(LPUART1, 115200U, 20000000U);
+ * @endcode
+ *
+ * @param base LPUART peripheral base address.
+ * @param baudRate_Bps LPUART baudrate to be set.
+ * @param srcClock_Hz LPUART clock source frequency in HZ.
+ * @retval kStatus_LPUART_BaudrateNotSupport Baudrate is not supported in the current clock source.
+ * @retval kStatus_Success Set baudrate succeeded.
+ */
+status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz);
+
+/* @} */
+
+/*!
+ * @name Status
+ * @{
+ */
+
+/*!
+ * @brief Gets LPUART status flags.
+ *
+ * This function gets all LPUART status flags. The flags are returned as the logical
+ * OR value of the enumerators @ref _lpuart_flags. To check for a specific status,
+ * compare the return value with enumerators in the @ref _lpuart_flags.
+ * For example, to check whether the TX is empty:
+ * @code
+ *     if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(LPUART1))
+ *     {
+ *         ...
+ *     }
+ * @endcode
+ *
+ * @param base LPUART peripheral base address.
+ * @return LPUART status flags which are ORed by the enumerators in the _lpuart_flags.
+ */
+uint32_t LPUART_GetStatusFlags(LPUART_Type *base);
+
+/*!
+ * @brief Clears status flags with a provided mask.
+ *
+ * This function clears LPUART status flags with a provided mask. Automatically cleared flags
+ * can't be cleared by this function.
+ * Flags that can only cleared or set by hardware are:
+ *    kLPUART_TxDataRegEmptyFlag, kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag,
+ *    kLPUART_RxActiveFlag, kLPUART_NoiseErrorInRxDataRegFlag, kLPUART_ParityErrorInRxDataRegFlag,
+ *    kLPUART_TxFifoEmptyFlag,kLPUART_RxFifoEmptyFlag
+ * Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects.
+ *
+ * @param base LPUART peripheral base address.
+ * @param mask the status flags to be cleared. The user can use the enumerators in the
+ *  _lpuart_status_flag_t to do the OR operation and get the mask.
+ * @return 0 succeed, others failed.
+ * @retval kStatus_LPUART_FlagCannotClearManually The flag can't be cleared by this function but
+ *         it is cleared automatically by hardware.
+ * @retval kStatus_Success Status in the mask are cleared.
+ */
+status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask);
+
+/* @} */
+
+/*!
+ * @name Interrupts
+ * @{
+ */
+
+/*!
+ * @brief Enables LPUART interrupts according to a provided mask.
+ *
+ * This function enables the LPUART interrupts according to a provided mask. The mask
+ * is a logical OR of enumeration members. See the @ref _lpuart_interrupt_enable.
+ * This examples shows how to enable TX empty interrupt and RX full interrupt:
+ * @code
+ *     LPUART_EnableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable);
+ * @endcode
+ *
+ * @param base LPUART peripheral base address.
+ * @param mask The interrupts to enable. Logical OR of @ref _uart_interrupt_enable.
+ */
+void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask);
+
+/*!
+ * @brief Disables  LPUART interrupts according to a provided mask.
+ *
+ * This function disables the LPUART interrupts according to a provided mask. The mask
+ * is a logical OR of enumeration members. See @ref _lpuart_interrupt_enable.
+ * This example shows how to disable the TX empty interrupt and RX full interrupt:
+ * @code
+ *     LPUART_DisableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable);
+ * @endcode
+ *
+ * @param base LPUART peripheral base address.
+ * @param mask The interrupts to disable. Logical OR of @ref _lpuart_interrupt_enable.
+ */
+void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask);
+
+/*!
+ * @brief Gets enabled LPUART interrupts.
+ *
+ * This function gets the enabled LPUART interrupts. The enabled interrupts are returned
+ * as the logical OR value of the enumerators @ref _lpuart_interrupt_enable. To check
+ * a specific interrupt enable status, compare the return value with enumerators
+ * in @ref _lpuart_interrupt_enable.
+ * For example, to check whether the TX empty interrupt is enabled:
+ * @code
+ *     uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(LPUART1);
+ *
+ *     if (kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts)
+ *     {
+ *         ...
+ *     }
+ * @endcode
+ *
+ * @param base LPUART peripheral base address.
+ * @return LPUART interrupt flags which are logical OR of the enumerators in @ref _lpuart_interrupt_enable.
+ */
+uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base);
+
+#if defined(FSL_FEATURE_LPUART_HAS_DMA_ENABLE) && FSL_FEATURE_LPUART_HAS_DMA_ENABLE
+/*!
+ * @brief Gets the LPUART data register address.
+ *
+ * This function returns the LPUART data register address, which is mainly used by the DMA/eDMA.
+ *
+ * @param base LPUART peripheral base address.
+ * @return LPUART data register addresses which are used both by the transmitter and receiver.
+ */
+static inline uint32_t LPUART_GetDataRegisterAddress(LPUART_Type *base)
+{
+    return (uint32_t) & (base->DATA);
+}
+
+/*!
+ * @brief Enables or disables the LPUART transmitter DMA request.
+ *
+ * This function enables or disables the transmit data register empty flag, STAT[TDRE], to generate DMA requests.
+ *
+ * @param base LPUART peripheral base address.
+ * @param enable True to enable, false to disable.
+ */
+static inline void LPUART_EnableTxDMA(LPUART_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->BAUD |= LPUART_BAUD_TDMAE_MASK;
+        base->CTRL |= LPUART_CTRL_TIE_MASK;
+    }
+    else
+    {
+        base->BAUD &= ~LPUART_BAUD_TDMAE_MASK;
+        base->CTRL &= ~LPUART_CTRL_TIE_MASK;
+    }
+}
+
+/*!
+ * @brief Enables or disables the LPUART receiver DMA.
+ *
+ * This function enables or disables the receiver data register full flag, STAT[RDRF], to generate DMA requests.
+ *
+ * @param base LPUART peripheral base address.
+ * @param enable True to enable, false to disable.
+ */
+static inline void LPUART_EnableRxDMA(LPUART_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->BAUD |= LPUART_BAUD_RDMAE_MASK;
+        base->CTRL |= LPUART_CTRL_RIE_MASK;
+    }
+    else
+    {
+        base->BAUD &= ~LPUART_BAUD_RDMAE_MASK;
+        base->CTRL &= ~LPUART_CTRL_RIE_MASK;
+    }
+}
+
+/* @} */
+#endif /* FSL_FEATURE_LPUART_HAS_DMA_ENABLE */
+
+/*!
+ * @name Bus Operations
+ * @{
+ */
+
+/*!
+ * @brief Enables or disables the LPUART transmitter.
+ *
+ * This function enables or disables the LPUART transmitter.
+ *
+ * @param base LPUART peripheral base address.
+ * @param enable True to enable, false to disable.
+ */
+static inline void LPUART_EnableTx(LPUART_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CTRL |= LPUART_CTRL_TE_MASK;
+    }
+    else
+    {
+        base->CTRL &= ~LPUART_CTRL_TE_MASK;
+    }
+}
+
+/*!
+ * @brief Enables or disables the LPUART receiver.
+ *
+ * This function enables or disables the LPUART receiver.
+ *
+ * @param base LPUART peripheral base address.
+ * @param enable True to enable, false to disable.
+ */
+static inline void LPUART_EnableRx(LPUART_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CTRL |= LPUART_CTRL_RE_MASK;
+    }
+    else
+    {
+        base->CTRL &= ~LPUART_CTRL_RE_MASK;
+    }
+}
+
+/*!
+ * @brief Writes to the transmitter register.
+ *
+ * This function writes data to the transmitter register directly. The upper layer must
+ * ensure that the TX register is empty or that the TX FIFO has room before calling this function.
+ *
+ * @param base LPUART peripheral base address.
+ * @param data Data write to the TX register.
+ */
+static inline void LPUART_WriteByte(LPUART_Type *base, uint8_t data)
+{
+    base->DATA = data;
+}
+
+/*!
+ * @brief Reads the receiver register.
+ *
+ * This function reads data from the receiver register directly. The upper layer must
+ * ensure that the receiver register is full or that the RX FIFO has data before calling this function.
+ *
+ * @param base LPUART peripheral base address.
+ * @return Data read from data register.
+ */
+static inline uint8_t LPUART_ReadByte(LPUART_Type *base)
+{
+#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
+    uint32_t ctrl = base->CTRL;
+    bool isSevenDataBits =
+        ((ctrl & LPUART_CTRL_M7_MASK) ||
+         ((!(ctrl & LPUART_CTRL_M7_MASK)) && (!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK)));
+
+    if (isSevenDataBits)
+    {
+        return (base->DATA & 0x7F);
+    }
+    else
+    {
+        return base->DATA;
+    }
+#else
+    return base->DATA;
+#endif
+}
+
+/*!
+ * @brief Writes to the transmitter register using a blocking method.
+ *
+ * This function polls the transmitter register, waits for the register to be empty or  for TX FIFO to have
+ * room, and writes data to the transmitter buffer.
+ *
+ * @note This function does not check whether all data has been sent out to the bus.
+ * Before disabling the transmitter, check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is
+ * finished.
+ *
+ * @param base LPUART peripheral base address.
+ * @param data Start address of the data to write.
+ * @param length Size of the data to write.
+ */
+void LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length);
+
+/*!
+* @brief Reads the receiver data register using a blocking method.
+ *
+ * This function polls the receiver register, waits for the receiver register full or receiver FIFO
+ * has data, and reads data from the TX register.
+ *
+ * @param base LPUART peripheral base address.
+ * @param data Start address of the buffer to store the received data.
+ * @param length Size of the buffer.
+ * @retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data.
+ * @retval kStatus_LPUART_NoiseError Noise error happened while receiving data.
+ * @retval kStatus_LPUART_FramingError Framing error happened while receiving data.
+ * @retval kStatus_LPUART_ParityError Parity error happened while receiving data.
+ * @retval kStatus_Success Successfully received all data.
+ */
+status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length);
+
+/* @} */
+
+/*!
+ * @name Transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the LPUART handle.
+ *
+ * This function initializes the LPUART handle, which can be used for other LPUART
+ * transactional APIs. Usually, for a specified LPUART instance,
+ * call this API once to get the initialized handle.
+ *
+ * The LPUART driver supports the "background" receiving, which means that user can set up
+ * an RX ring buffer optionally. Data received is stored into the ring buffer even when the
+ * user doesn't call the LPUART_TransferReceiveNonBlocking() API. If there is already data received
+ * in the ring buffer, the user can get the received data from the ring buffer directly.
+ * The ring buffer is disabled if passing NULL as @p ringBuffer.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle LPUART handle pointer.
+ * @param callback Callback function.
+ * @param userData User data.
+ */
+void LPUART_TransferCreateHandle(LPUART_Type *base,
+                                 lpuart_handle_t *handle,
+                                 lpuart_transfer_callback_t callback,
+                                 void *userData);
+/*!
+ * @brief Transmits a buffer of data using the interrupt method.
+ *
+ * This function send data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data written to the transmitter register. When
+ * all data is written to the TX register in the ISR, the LPUART driver calls the callback
+ * function and passes the @ref kStatus_LPUART_TxIdle as status parameter.
+ *
+ * @note The kStatus_LPUART_TxIdle is passed to the upper layer when all data are written
+ * to the TX register. However, there is no check to ensure that all the data sent out. Before disabling the TX,
+ * check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is finished.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle LPUART handle pointer.
+ * @param xfer LPUART transfer structure, see #lpuart_transfer_t.
+ * @retval kStatus_Success Successfully start the data transmission.
+ * @retval kStatus_LPUART_TxBusy Previous transmission still not finished, data not all written to the TX register.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer);
+
+/*!
+ * @brief Sets up the RX ring buffer.
+ *
+ * This function sets up the RX ring buffer to a specific UART handle.
+ *
+ * When the RX ring buffer is used, data received is stored into the ring buffer even when
+ * the user doesn't call the UART_TransferReceiveNonBlocking() API. If there is already data received
+ * in the ring buffer, the user can get the received data from the ring buffer directly.
+ *
+ * @note When using RX ring buffer, one byte is reserved for internal use. In other
+ * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle LPUART handle pointer.
+ * @param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer.
+ * @param ringBufferSize size of the ring buffer.
+ */
+void LPUART_TransferStartRingBuffer(LPUART_Type *base,
+                                    lpuart_handle_t *handle,
+                                    uint8_t *ringBuffer,
+                                    size_t ringBufferSize);
+
+/*!
+ * @brief Aborts the background transfer and uninstalls the ring buffer.
+ *
+ * This function aborts the background transfer and uninstalls the ring buffer.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle LPUART handle pointer.
+ */
+void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle);
+
+/*!
+ * @brief Aborts the interrupt-driven data transmit.
+ *
+ * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out
+ * how many bytes are not sent out.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle LPUART handle pointer.
+ */
+void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle);
+
+/*!
+ * @brief Gets the number of bytes that have been written to the LPUART transmitter register.
+ *
+ * This function gets the number of bytes that have been written to LPUART TX
+ * register by an interrupt method.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle LPUART handle pointer.
+ * @param count Send bytes count.
+ * @retval kStatus_NoTransferInProgress No send in progress.
+ * @retval kStatus_InvalidArgument Parameter is invalid.
+ * @retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count);
+
+/*!
+ * @brief Receives a buffer of data using the interrupt method.
+ *
+ * This function receives data using an interrupt method. This is a non-blocking function
+ * which returns without waiting to ensure that all data are received.
+ * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and
+ * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer.
+ * After copying, if the data in the ring buffer is not enough for read, the receive
+ * request is saved by the LPUART driver. When the new data arrives, the receive request
+ * is serviced first. When all data is received, the LPUART driver notifies the upper layer
+ * through a callback function and passes a status parameter @ref kStatus_UART_RxIdle.
+ * For example, the upper layer needs 10 bytes but there are only 5 bytes in ring buffer.
+ * The 5 bytes are copied to xfer->data, which returns with the
+ * parameter @p receivedBytes set to 5. For the remaining 5 bytes, the newly arrived data is
+ * saved from xfer->data[5]. When 5 bytes are received, the LPUART driver notifies the upper layer.
+ * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt
+ * to receive data to xfer->data. When all data is received, the upper layer is notified.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle LPUART handle pointer.
+ * @param xfer LPUART transfer structure, see #uart_transfer_t.
+ * @param receivedBytes Bytes received from the ring buffer directly.
+ * @retval kStatus_Success Successfully queue the transfer into the transmit queue.
+ * @retval kStatus_LPUART_RxBusy Previous receive request is not finished.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base,
+                                           lpuart_handle_t *handle,
+                                           lpuart_transfer_t *xfer,
+                                           size_t *receivedBytes);
+
+/*!
+ * @brief Aborts the interrupt-driven data receiving.
+ *
+ * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out
+ * how many bytes not received yet.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle LPUART handle pointer.
+ */
+void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle);
+
+/*!
+ * @brief Gets the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle LPUART handle pointer.
+ * @param count Receive bytes count.
+ * @retval kStatus_NoTransferInProgress No receive in progress.
+ * @retval kStatus_InvalidArgument Parameter is invalid.
+ * @retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count);
+
+/*!
+ * @brief LPUART IRQ handle function.
+ *
+ * This function handles the LPUART transmit and receive IRQ request.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle LPUART handle pointer.
+ */
+void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle);
+
+/*!
+ * @brief LPUART Error IRQ handle function.
+ *
+ * This function handles the LPUART error IRQ request.
+ *
+ * @param base LPUART peripheral base address.
+ * @param handle LPUART handle pointer.
+ */
+void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, lpuart_handle_t *handle);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_LPUART_H_ */

FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_msmc.c

@@ -0,0 +1,290 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ * 
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_msmc.h"
+
+#if defined(__riscv)
+#define CONFIG_NORMAL_SLEEP EVENT_UNIT->SLPCTRL = (EVENT_UNIT->SLPCTRL & ~0x03) | (1 << 0)
+#define CONFIG_DEEP_SLEEP EVENT_UNIT->SLPCTRL |= 0x03;
+#else
+#define CONFIG_NORMAL_SLEEP SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk
+#define CONFIG_DEEP_SLEEP SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk
+#endif
+
+status_t SMC_SetPowerModeRun(SMC_Type *base)
+{
+    uint32_t reg;
+
+    reg = base->PMCTRL;
+    /* configure Normal RUN mode */
+    reg &= ~SMC_PMCTRL_RUNM_MASK;
+    reg |= (kSMC_RunNormal << SMC_PMCTRL_RUNM_SHIFT);
+    base->PMCTRL = reg;
+
+    return kStatus_Success;
+}
+
+status_t SMC_SetPowerModeHsrun(SMC_Type *base)
+{
+    uint32_t reg;
+
+    reg = base->PMCTRL;
+    /* configure High Speed RUN mode */
+    reg &= ~SMC_PMCTRL_RUNM_MASK;
+    reg |= (kSMC_Hsrun << SMC_PMCTRL_RUNM_SHIFT);
+    base->PMCTRL = reg;
+
+    return kStatus_Success;
+}
+
+status_t SMC_SetPowerModeWait(SMC_Type *base)
+{
+    /* configure Normal Wait mode */
+    CONFIG_NORMAL_SLEEP;
+
+    __DSB();
+    __WFI();
+    __ISB();
+
+    return kStatus_Success;
+}
+
+status_t SMC_SetPowerModeStop(SMC_Type *base, smc_partial_stop_option_t option)
+{
+    uint32_t reg;
+
+    /* configure the Partial Stop mode in Noraml Stop mode */
+    reg = base->PMCTRL;
+    reg &= ~(SMC_PMCTRL_PSTOPO_MASK | SMC_PMCTRL_STOPM_MASK);
+    reg |= ((uint32_t)option << SMC_PMCTRL_PSTOPO_SHIFT) | (kSMC_StopNormal << SMC_PMCTRL_STOPM_SHIFT);
+    base->PMCTRL = reg;
+
+    /* Set the SLEEPDEEP bit to enable deep sleep mode (stop mode) */
+    CONFIG_DEEP_SLEEP;
+
+    /* read back to make sure the configuration valid before entering stop mode */
+    (void)base->PMCTRL;
+    __DSB();
+    __WFI();
+    __ISB();
+
+#if (defined(FSL_FEATURE_SMC_HAS_PMCTRL_STOPA) && FSL_FEATURE_SMC_HAS_PMCTRL_STOPA)
+    /* check whether the power mode enter Stop mode succeed */
+    if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)
+    {
+        return kStatus_SMC_StopAbort;
+    }
+    else
+    {
+        return kStatus_Success;
+    }
+#else
+    return kStatus_Success;
+#endif /* FSL_FEATURE_SMC_HAS_PMCTRL_STOPA */
+}
+
+status_t SMC_SetPowerModeVlpr(SMC_Type *base)
+{
+    uint32_t reg;
+
+    reg = base->PMCTRL;
+    /* configure VLPR mode */
+    reg &= ~SMC_PMCTRL_RUNM_MASK;
+    reg |= (kSMC_RunVlpr << SMC_PMCTRL_RUNM_SHIFT);
+    base->PMCTRL = reg;
+
+    return kStatus_Success;
+}
+
+status_t SMC_SetPowerModeVlpw(SMC_Type *base)
+{
+    /* configure VLPW mode */
+    /* Clear the SLEEPDEEP bit to disable deep sleep mode */
+    CONFIG_NORMAL_SLEEP;
+
+    __DSB();
+    __WFI();
+    __ISB();
+
+    return kStatus_Success;
+}
+
+status_t SMC_SetPowerModeVlps(SMC_Type *base)
+{
+    uint32_t reg;
+
+    /* configure VLPS mode */
+    reg = base->PMCTRL;
+    reg &= ~SMC_PMCTRL_STOPM_MASK;
+    reg |= (kSMC_StopVlps << SMC_PMCTRL_STOPM_SHIFT);
+    base->PMCTRL = reg;
+
+    /* Set the SLEEPDEEP bit to enable deep sleep mode */
+    CONFIG_DEEP_SLEEP;
+
+    /* read back to make sure the configuration valid before enter stop mode */
+    (void)base->PMCTRL;
+    __DSB();
+    __WFI();
+    __ISB();
+
+#if (defined(FSL_FEATURE_SMC_HAS_PMCTRL_STOPA) && FSL_FEATURE_SMC_HAS_PMCTRL_STOPA)
+    /* check whether the power mode enter Stop mode succeed */
+    if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)
+    {
+        return kStatus_SMC_StopAbort;
+    }
+    else
+    {
+        return kStatus_Success;
+    }
+#else
+    return kStatus_Success;
+#endif /* FSL_FEATURE_SMC_HAS_PMCTRL_STOPA */
+}
+
+status_t SMC_SetPowerModeLls(SMC_Type *base)
+{
+    uint32_t reg;
+
+    /* configure to LLS mode */
+    reg = base->PMCTRL;
+    reg &= ~SMC_PMCTRL_STOPM_MASK;
+    reg |= (kSMC_StopLls << SMC_PMCTRL_STOPM_SHIFT);
+    base->PMCTRL = reg;
+
+    /* Set the SLEEPDEEP bit to enable deep sleep mode */
+    CONFIG_DEEP_SLEEP;
+
+    /* read back to make sure the configuration valid before entering stop mode */
+    (void)base->PMCTRL;
+    __DSB();
+    __WFI();
+    __ISB();
+
+#if (defined(FSL_FEATURE_SMC_HAS_PMCTRL_STOPA) && FSL_FEATURE_SMC_HAS_PMCTRL_STOPA)
+    /* check whether the power mode enter Stop mode succeed */
+    if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)
+    {
+        return kStatus_SMC_StopAbort;
+    }
+    else
+    {
+        return kStatus_Success;
+    }
+#else
+    return kStatus_Success;
+#endif /* FSL_FEATURE_SMC_HAS_PMCTRL_STOPA */
+}
+
+#if (defined(FSL_FEATURE_SMC_HAS_SUB_STOP_MODE) && FSL_FEATURE_SMC_HAS_SUB_STOP_MODE)
+
+#if (defined(FSL_FEATURE_SMC_HAS_STOP_SUBMODE0) && FSL_FEATURE_SMC_HAS_STOP_SUBMODE0)
+status_t SMC_SetPowerModeVlls0(SMC_Type *base)
+{
+    uint32_t reg;
+
+    /* configure to VLLS mode */
+    reg = base->PMCTRL;
+    reg &= ~SMC_PMCTRL_STOPM_MASK;
+    reg |= (kSMC_StopVlls0 << SMC_PMCTRL_STOPM_SHIFT);
+    base->PMCTRL = reg;
+
+    /* Set the SLEEPDEEP bit to enable deep sleep mode */
+    CONFIG_DEEP_SLEEP;
+
+    /* read back to make sure the configuration valid before enter stop mode */
+    (void)base->PMCTRL;
+    __DSB();
+    __WFI();
+    __ISB();
+
+    return kStatus_Success;
+}
+#endif /* FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 */
+
+#if (defined(FSL_FEATURE_SMC_HAS_STOP_SUBMODE2) && FSL_FEATURE_SMC_HAS_STOP_SUBMODE2)
+status_t SMC_SetPowerModeVlls2(SMC_Type *base)
+{
+    uint32_t reg;
+
+    /* configure to VLLS mode */
+    reg = base->PMCTRL;
+    reg &= ~SMC_PMCTRL_STOPM_MASK;
+    reg |= (kSMC_StopVlls2 << SMC_PMCTRL_STOPM_SHIFT);
+    base->PMCTRL = reg;
+
+    /* Set the SLEEPDEEP bit to enable deep sleep mode */
+    CONFIG_DEEP_SLEEP;
+
+    /* read back to make sure the configuration valid before enter stop mode */
+    (void)base->PMCTRL;
+    __DSB();
+    __WFI();
+    __ISB();
+
+    return kStatus_Success;
+}
+#endif /* FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 */
+
+#else /* FSL_FEATURE_SMC_HAS_SUB_STOP_MODE */
+status_t SMC_SetPowerModeVlls(SMC_Type *base)
+{
+    uint32_t reg;
+
+    /* configure to VLLS mode */
+    reg = base->PMCTRL;
+    reg &= ~SMC_PMCTRL_STOPM_MASK;
+    reg |= (kSMC_StopVlls << SMC_PMCTRL_STOPM_SHIFT);
+    base->PMCTRL = reg;
+
+#if defined(__riscv)
+    EVENT->SCR = (EVENT->SCR & ~0x03) | (1 << 1);
+#else
+    /* Set the SLEEPDEEP bit to enable deep sleep mode */
+    CONFIG_DEEP_SLEEP;
+#endif
+
+    /* read back to make sure the configuration valid before enter stop mode */
+    (void)base->PMCTRL;
+    __DSB();
+    __WFI();
+    __ISB();
+
+#if (defined(FSL_FEATURE_SMC_HAS_PMCTRL_STOPA) && FSL_FEATURE_SMC_HAS_PMCTRL_STOPA)
+    /* check whether the power mode enter Stop mode succeed */
+    if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)
+    {
+        return kStatus_SMC_StopAbort;
+    }
+    else
+    {
+        return kStatus_Success;
+    }
+#else
+    return kStatus_Success;
+#endif /* FSL_FEATURE_SMC_HAS_PMCTRL_STOPA */
+}
+#endif /* FSL_FEATURE_SMC_HAS_SUB_STOP_MODE */
+
+void SMC_ConfigureResetPinFilter(SMC_Type *base, const smc_reset_pin_filter_config_t *config)
+{
+    assert(config);
+
+    uint32_t reg;
+
+    reg = SMC_RPC_FILTCFG(config->slowClockFilterCount) | SMC_RPC_FILTEN(config->enableFilter);
+#if (defined(FSL_FEATURE_SMC_HAS_RPC_LPOFEN) && FSL_FEATURE_SMC_HAS_RPC_LPOFEN)
+    if (config->enableLpoFilter)
+    {
+        reg |= SMC_RPC_LPOFEN_MASK;
+    }
+#endif /* FSL_FEATURE_SMC_HAS_RPC_LPOFEN */
+
+    base->RPC = reg;
+}

FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_msmc.h

@@ -0,0 +1,701 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ * 
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_MSMC_H_
+#define _FSL_MSMC_H_
+
+#include "fsl_common.h"
+
+/*! @addtogroup msmc */
+/*! @{*/
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief MSMC driver version 2.1.0. */
+#define FSL_MSMC_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
+/*@}*/
+
+/*!
+ * @brief Power Modes Protection
+ */
+typedef enum _smc_power_mode_protection
+{
+    kSMC_AllowPowerModeVlls = SMC_PMPROT_AVLLS_MASK,   /*!< Allow Very-Low-Leakage Stop Mode. */
+    kSMC_AllowPowerModeLls = SMC_PMPROT_ALLS_MASK,     /*!< Allow Low-Leakage Stop Mode.      */
+    kSMC_AllowPowerModeVlp = SMC_PMPROT_AVLP_MASK,     /*!< Allow Very-Low-Power Mode.        */
+    kSMC_AllowPowerModeHsrun = SMC_PMPROT_AHSRUN_MASK, /*!< Allow High Speed Run mode.        */
+    kSMC_AllowPowerModeAll = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK |
+                             SMC_PMPROT_AHSRUN_MASK /*!< Allow all power mode.              */
+} smc_power_mode_protection_t;
+
+/*!
+ * @brief Power Modes in PMSTAT
+ */
+typedef enum _smc_power_state
+{
+    kSMC_PowerStateRun = 1U,        /*!< 0000_0001 - Current power mode is RUN   */
+    kSMC_PowerStateStop = 1U << 1U, /*!< 0000_0010 - Current power mode is any STOP mode  */
+    kSMC_PowerStateVlpr = 1U << 2U, /*!< 0000_0100 - Current power mode is VLPR  */
+    kSMC_PowerStateHsrun = 1U << 7U /*!< 1000_0000 - Current power mode is HSRUN */
+} smc_power_state_t;
+
+/*!
+ * @brief Power Stop Entry Status in PMSTAT
+ */
+typedef enum _smc_power_stop_entry_status
+{
+    kSMC_PowerStopEntryAlt0 = 1U,      /*!< Indicates a Stop mode entry since this field was last cleared. */
+    kSMC_PowerStopEntryAlt1 = 1U << 1, /*!< Indicates the system bus masters acknowledged the Stop mode entry. */
+    kSMC_PowerStopEntryAlt2 = 1U << 2, /*!< Indicates the system clock peripherals acknowledged the Stop mode entry. */
+    kSMC_PowerStopEntryAlt3 = 1U << 3, /*!< Indicates the bus clock peripherals acknowledged the Stop mode entry. */
+    kSMC_PowerStopEntryAlt4 = 1U << 4, /*!< Indicates the slow clock peripherals acknowledged the Stop mode entry. */
+    kSMC_PowerStopEntryAlt5 = 1U << 5, /*!< Indicates Stop mode entry completed. */
+} smc_power_stop_entry_status_t;
+
+/*!
+ * @brief Run mode definition
+ */
+typedef enum _smc_run_mode
+{
+    kSMC_RunNormal = 0U, /*!< normal RUN mode.             */
+    kSMC_RunVlpr = 2U,   /*!< Very-Low-Power RUN mode.     */
+    kSMC_Hsrun = 3U      /*!< High Speed Run mode (HSRUN). */
+} smc_run_mode_t;
+
+/*!
+ * @brief Stop mode definition
+ */
+typedef enum _smc_stop_mode
+{
+    kSMC_StopNormal = 0U, /*!< Normal STOP mode.           */
+    kSMC_StopVlps = 2U,   /*!< Very-Low-Power STOP mode.   */
+    kSMC_StopLls = 3U,    /*!< Low-Leakage Stop mode.      */
+#if (defined(FSL_FEATURE_SMC_HAS_SUB_STOP_MODE) && FSL_FEATURE_SMC_HAS_SUB_STOP_MODE)
+#if (defined(FSL_FEATURE_SMC_HAS_STOP_SUBMODE2) && FSL_FEATURE_SMC_HAS_STOP_SUBMODE2)
+    kSMC_StopVlls2 = 4U, /*!< Very-Low-Leakage Stop mode, VLPS2/3. */
+#endif                   /* FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 */
+#if (defined(FSL_FEATURE_SMC_HAS_STOP_SUBMODE0) && FSL_FEATURE_SMC_HAS_STOP_SUBMODE0)
+    kSMC_StopVlls0 = 6U, /*!< Very-Low-Leakage Stop mode, VLPS0/1. */
+#endif                   /* FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 */
+#else
+    kSMC_StopVlls = 4U, /*!< Very-Low-Leakage Stop mode. */
+#endif /* FSL_FEATURE_SMC_HAS_SUB_STOP_MODE */
+} smc_stop_mode_t;
+
+/*!
+ * @brief Partial STOP option
+ */
+typedef enum _smc_partial_stop_mode
+{
+    kSMC_PartialStop = 0U,  /*!< STOP - Normal Stop mode*/
+    kSMC_PartialStop1 = 1U, /*!< Partial Stop with both system and bus clocks disabled*/
+    kSMC_PartialStop2 = 2U, /*!< Partial Stop with system clock disabled and bus clock enabled*/
+    kSMC_PartialStop3 = 3U, /*!< Partial Stop with system clock enabled and bus clock disabled*/
+} smc_partial_stop_option_t;
+
+/*!
+ * @brief SMC configuration status
+ */
+enum _smc_status
+{
+    kStatus_SMC_StopAbort = MAKE_STATUS(kStatusGroup_POWER, 0), /*!< Entering Stop mode is abort*/
+};
+
+/*!
+ * @brief System Reset Source Name definitions
+ */
+typedef enum _smc_reset_source
+{
+    kSMC_SourceWakeup = SMC_SRS_WAKEUP_MASK, /*!< Very low-leakage wakeup reset */
+    kSMC_SourcePor = SMC_SRS_POR_MASK,       /*!< Power on reset */
+    kSMC_SourceLvd = SMC_SRS_LVD_MASK,       /*!< Low-voltage detect reset */
+    kSMC_SourceHvd = SMC_SRS_HVD_MASK,       /*!< High-voltage detect reset */
+    kSMC_SourceWarm = SMC_SRS_WARM_MASK,     /*!< Warm reset. Warm Reset flag will assert if any of the system reset
+                                                 sources in this register assert (SRS[31:8]) */
+    kSMC_SourceFatal = SMC_SRS_FATAL_MASK,   /*!< Fatal reset */
+    kSMC_SourceCore =
+        SMC_SRS_CORE_MASK, /*!< Software reset that only reset the core, NOT a sticky system reset source. */
+    kSMC_SourcePin = SMC_SRS_PIN_MASK,         /*!< RESET_B pin reset. */
+    kSMC_SourceMdm = SMC_SRS_MDM_MASK,         /*!< MDM reset. */
+    kSMC_SourceRstAck = SMC_SRS_RSTACK_MASK,   /*!< Reset Controller timeout reset. */
+    kSMC_SourceStopAck = SMC_SRS_STOPACK_MASK, /*!< Stop timeout reset */
+    kSMC_SourceScg = SMC_SRS_SCG_MASK,         /*!< SCG loss of lock or loss of clock */
+    kSMC_SourceWdog = SMC_SRS_WDOG_MASK,       /*!< Watchdog reset */
+    kSMC_SourceSoftware = SMC_SRS_SW_MASK,     /*!< Software reset */
+    kSMC_SourceLockup = SMC_SRS_LOCKUP_MASK,   /*!< Lockup reset. Core lockup or exception. */
+    kSMC_SourceJtag = SMC_SRS_JTAG_MASK,       /*!< JTAG system reset */
+#if (defined(FSL_FEATURE_SMC_HAS_SRS_SECVIO) && FSL_FEATURE_SMC_HAS_SRS_SECVIO)
+    kSMC_SourceSecVio = SMC_SRS_SECVIO_MASK, /*!< Security violation reset */
+#endif                                       /* FSL_FEATURE_SMC_HAS_SRS_SECVIO */
+#if (defined(FSL_FEATURE_SMC_HAS_SRS_TAMPER) && FSL_FEATURE_SMC_HAS_SRS_TAMPER)
+    kSMC_SourceTamper = SMC_SRS_TAMPER_MASK, /*!< Tamper reset */
+#endif                                       /* FSL_FEATURE_SMC_HAS_SRS_TAMPER */
+#if (defined(FSL_FEATURE_SMC_HAS_SRS_CORE0) && FSL_FEATURE_SMC_HAS_SRS_CORE0)
+    kSMC_SourceCore0 = SMC_SRS_CORE0_MASK, /*!< Core0 System Reset. */
+#endif                                     /* FSL_FEATURE_SMC_HAS_SRS_CORE0 */
+#if (defined(FSL_FEATURE_SMC_HAS_SRS_CORE1) && FSL_FEATURE_SMC_HAS_SRS_CORE1)
+    kSMC_SourceCore1 = SMC_SRS_CORE1_MASK, /*!< Core1 System Reset. */
+#endif                                     /* FSL_FEATURE_SMC_HAS_SRS_CORE1 */
+    /* Source All. */
+    kSMC_SourceAll = SMC_SRS_WAKEUP_MASK | SMC_SRS_POR_MASK | SMC_SRS_LVD_MASK | SMC_SRS_HVD_MASK | SMC_SRS_WARM_MASK |
+                     SMC_SRS_FATAL_MASK | SMC_SRS_CORE_MASK | SMC_SRS_PIN_MASK | SMC_SRS_MDM_MASK |
+                     SMC_SRS_RSTACK_MASK | SMC_SRS_STOPACK_MASK | SMC_SRS_SCG_MASK | SMC_SRS_WDOG_MASK |
+                     SMC_SRS_SW_MASK | SMC_SRS_LOCKUP_MASK | SMC_SRS_JTAG_MASK
+#if (defined(FSL_FEATURE_SMC_HAS_SRS_SECVIO) && FSL_FEATURE_SMC_HAS_SRS_SECVIO)
+                     |
+                     SMC_SRS_SECVIO_MASK
+#endif /* FSL_FEATURE_SMC_HAS_SRS_SECVIO */
+#if (defined(FSL_FEATURE_SMC_HAS_SRS_TAMPER) && FSL_FEATURE_SMC_HAS_SRS_TAMPER)
+                     |
+                     SMC_SRS_TAMPER_MASK
+#endif /* FSL_FEATURE_SMC_HAS_SRS_TAMPER */
+#if (defined(FSL_FEATURE_SMC_HAS_SRS_CORE0) && FSL_FEATURE_SMC_HAS_SRS_CORE0)
+                     |
+                     SMC_SRS_CORE0_MASK
+#endif /* FSL_FEATURE_SMC_HAS_SRS_CORE0 */
+#if (defined(FSL_FEATURE_SMC_HAS_SRS_CORE1) && FSL_FEATURE_SMC_HAS_SRS_CORE1)
+                     |
+                     SMC_SRS_CORE1_MASK
+#endif /* FSL_FEATURE_SMC_HAS_SRS_CORE1 */
+    ,
+} smc_reset_source_t;
+
+/*!
+ * @brief System reset interrupt enable bit definitions.
+ */
+typedef enum _smc_interrupt_enable
+{
+    kSMC_IntNone = 0U,                       /*!< No interrupt enabled.       */
+    kSMC_IntPin = SMC_SRIE_PIN_MASK,         /*!< Pin reset interrupt.        */
+    kSMC_IntMdm = SMC_SRIE_MDM_MASK,         /*!< MDM reset interrupt.        */
+    kSMC_IntStopAck = SMC_SRIE_STOPACK_MASK, /*!< Stop timeout reset interrupt.  */
+    kSMC_IntWdog = SMC_SRIE_WDOG_MASK,       /*!< Watchdog interrupt.         */
+    kSMC_IntSoftware = SMC_SRIE_SW_MASK,     /*!< Software reset interrupts.  */
+    kSMC_IntLockup = SMC_SRIE_LOCKUP_MASK,   /*!< Lock up interrupt.          */
+#if (defined(FSL_FEATURE_SMC_HAS_CSRE_CORE0) && FSL_FEATURE_SMC_HAS_CSRE_CORE0)
+    kSMC_IntCore0 = SMC_SRIE_CORE0_MASK, /*! Core 0 interrupts. */
+#endif                                   /* FSL_FEATURE_SMC_HAS_CSRE_CORE0 */
+#if (defined(FSL_FEATURE_SMC_HAS_CSRE_CORE1) && FSL_FEATURE_SMC_HAS_CSRE_CORE1)
+    kSMC_IntCore1 = SMC_SRIE_CORE1_MASK, /*! Core 1 interrupts. */
+#endif                                   /* FSL_FEATURE_SMC_HAS_CSRE_CORE1 */
+    kSMC_IntAll = SMC_SRIE_PIN_MASK |    /*!< All system reset interrupts.      */
+                  SMC_SRIE_MDM_MASK |
+                  SMC_SRIE_STOPACK_MASK | SMC_SRIE_WDOG_MASK | SMC_SRIE_SW_MASK | SMC_SRIE_LOCKUP_MASK
+#if (defined(FSL_FEATURE_SMC_HAS_CSRE_CORE0) && FSL_FEATURE_SMC_HAS_CSRE_CORE0)
+                  |
+                  SMC_SRIE_CORE0_MASK
+#endif /* FSL_FEATURE_SMC_HAS_CSRE_CORE0 */
+#if (defined(FSL_FEATURE_SMC_HAS_CSRE_CORE1) && FSL_FEATURE_SMC_HAS_CSRE_CORE1)
+                  |
+                  SMC_SRIE_CORE1_MASK
+#endif /* FSL_FEATURE_SMC_HAS_CSRE_CORE1 */
+} smc_interrupt_enable_t;
+
+/*!
+ * @brief Reset pin filter configuration
+ */
+typedef struct _smc_reset_pin_filter_config
+{
+    uint8_t slowClockFilterCount; /*!< Reset pin bus clock filter width from 1 to 32 slow clock cycles.  */
+    bool enableFilter;            /*!< Reset pin filter enable/disable. */
+#if (defined(FSL_FEATURE_SMC_HAS_RPC_LPOFEN) && FSL_FEATURE_SMC_HAS_RPC_LPOFEN)
+    bool enableLpoFilter; /*!< LPO clock reset pin filter enabled in all modes. */
+#endif                    /* FSL_FEATURE_SMC_HAS_RPC_LPOFEN */
+} smc_reset_pin_filter_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*! @name System mode controller APIs*/
+/*@{*/
+
+/*!
+ * @brief Configures all power mode protection settings.
+ *
+ * This function  configures the power mode protection settings for
+ * supported power modes in the specified chip family. The available power modes
+ * are defined in the smc_power_mode_protection_t. This should be done at an early
+ * system level initialization stage. See the reference manual for details.
+ * This register can only write once after the power reset.
+ *
+ * The allowed modes are passed as bit map, for example, to allow LLS and VLLS,
+ * use SMC_SetPowerModeProtection(kSMC_AllowPowerModeLls | kSMC_AllowPowerModeVlls).
+ * To allow all modes, use SMC_SetPowerModeProtection(kSMC_AllowPowerModeAll).
+ *
+ * @param allowedModes Bitmap of the allowed power modes.
+ */
+static inline void SMC_SetPowerModeProtection(SMC_Type *base, uint8_t allowedModes)
+{
+    base->PMPROT = allowedModes;
+}
+
+/*!
+ * @brief Gets the current power mode status.
+ *
+ * This function  returns the current power mode stat. Once application
+ * switches the power mode, it should always check the stat to check whether it
+ * runs into the specified mode or not. An application  should  check
+ * this mode before switching to a different mode. The system  requires that
+ * only certain modes can switch to other specific modes. See the
+ * reference manual for details and the smc_power_state_t for information about
+ * the power stat.
+ *
+ * @param base SMC peripheral base address.
+ * @return Current power mode status.
+ */
+static inline smc_power_state_t SMC_GetPowerModeState(SMC_Type *base)
+{
+    return (smc_power_state_t)((base->PMSTAT & SMC_PMSTAT_PMSTAT_MASK) >> SMC_PMSTAT_PMSTAT_SHIFT);
+}
+
+#if (defined(FSL_FEATURE_SMC_HAS_PMSTAT_STOPSTAT) && FSL_FEATURE_SMC_HAS_PMSTAT_STOPSTAT)
+/*!
+ * @brief Gets the result of the previous stop mode entry.
+ *
+ * This function  returns the result of the previous stop mode entry.
+ *
+ * @param base SMC peripheral base address.
+ * @return Current power stop entry status.
+ */
+static inline smc_power_stop_entry_status_t SMC_GetStopEntryStatus(SMC_Type *base)
+{
+    return (smc_power_stop_entry_status_t)((base->PMSTAT & SMC_PMSTAT_STOPSTAT_MASK) >> SMC_PMSTAT_STOPSTAT_SHIFT);
+}
+
+/*!
+ * @brief Clears all the result of the previous stop mode entry.
+ *
+ * This function clears all the result of the previous stop mode entry.
+ *
+ * @param base SMC peripheral base address.
+ * @return Current power stop entry status.
+ */
+static inline void SMC_ClearStopEntryStatus(SMC_Type *base)
+{
+    /* Only write 0x01 to clear this field, all other writes are ignored. */
+    base->PMSTAT = (base->PMSTAT & ~SMC_PMSTAT_STOPSTAT_MASK) | SMC_PMSTAT_STOPSTAT(0x01);
+}
+
+#endif /* FSL_FEATURE_SMC_HAS_PMSTAT_STOPSTAT */
+
+/*!
+ * @brief Prepare to enter stop modes
+ *
+ * This function should be called before entering STOP/VLPS/LLS/VLLS modes.
+ */
+static inline void SMC_PreEnterStopModes(void)
+{
+    __disable_irq();
+    __ISB();
+}
+
+/*!
+ * @brief Recovering after wake up from stop modes
+ *
+ * This function should be called after wake up from STOP/VLPS/LLS/VLLS modes.
+ * It is used together with @ref SMC_PreEnterStopModes.
+ */
+static inline void SMC_PostExitStopModes(void)
+{
+    __enable_irq();
+    __ISB();
+}
+
+/*!
+ * @brief Prepare to enter wait modes
+ *
+ * This function should be called before entering WAIT/VLPW modes..
+ */
+static inline void SMC_PreEnterWaitModes(void)
+{
+    __disable_irq();
+    __ISB();
+}
+
+/*!
+ * @brief Recovering after wake up from stop modes
+ *
+ * This function should be called after wake up from WAIT/VLPW modes.
+ * It is used together with @ref SMC_PreEnterWaitModes.
+ */
+static inline void SMC_PostExitWaitModes(void)
+{
+    __enable_irq();
+    __ISB();
+}
+
+/*!
+ * @brief Configure the system to RUN power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeRun(SMC_Type *base);
+
+/*!
+ * @brief Configure the system to HSRUN power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeHsrun(SMC_Type *base);
+
+/*!
+ * @brief Configure the system to WAIT power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeWait(SMC_Type *base);
+
+/*!
+ * @brief Configure the system to Stop power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @param  option Partial Stop mode option.
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeStop(SMC_Type *base, smc_partial_stop_option_t option);
+
+/*!
+ * @brief Configure the system to VLPR power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeVlpr(SMC_Type *base);
+
+/*!
+ * @brief Configure the system to VLPW power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeVlpw(SMC_Type *base);
+
+/*!
+ * @brief Configure the system to VLPS power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeVlps(SMC_Type *base);
+/*!
+ * @brief Configure the system to LLS power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeLls(SMC_Type *base);
+
+#if (defined(FSL_FEATURE_SMC_HAS_SUB_STOP_MODE) && FSL_FEATURE_SMC_HAS_SUB_STOP_MODE)
+#if (defined(FSL_FEATURE_SMC_HAS_STOP_SUBMODE0) && FSL_FEATURE_SMC_HAS_STOP_SUBMODE0)
+/*!
+ * @brief Configure the system to VLLS0 power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeVlls0(SMC_Type *base);
+#endif /* FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 */
+#if (defined(FSL_FEATURE_SMC_HAS_STOP_SUBMODE2) && FSL_FEATURE_SMC_HAS_STOP_SUBMODE2)
+/*!
+ * @brief Configure the system to VLLS2 power mode.
+ *
+ * @param base SMC peripheral base address.
+ * @return SMC configuration error code.
+ */
+status_t SMC_SetPowerModeVlls2(SMC_Type *base);
+#endif /* FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 */
+#else
+                        /*!
+                         * @brief Configure the system to VLLS power mode.
+                         *
+                         * @param base SMC peripheral base address.
+                         * @return SMC configuration error code.
+                         */
+status_t SMC_SetPowerModeVlls(SMC_Type *base);
+#endif /* FSL_FEATURE_SMC_HAS_SUB_STOP_MODE */
+
+/*!
+ * @brief Gets the reset source status which caused a previous reset.
+ *
+ * This function gets the current reset source status. Use source masks
+ * defined in the smc_reset_source_t to get the desired source status.
+ *
+ * Example:
+   @code
+   uint32_t resetStatus;
+
+   // To get all reset source statuses.
+   resetStatus = SMC_GetPreviousResetSources(SMC0) & kSMC_SourceAll;
+
+   // To test whether the MCU is reset using Watchdog.
+   resetStatus = SMC_GetPreviousResetSources(SMC0) & kSMC_SourceWdog;
+
+   // To test multiple reset sources.
+   resetStatus = SMC_GetPreviousResetSources(SMC0) & (kSMC_SourceWdog | kSMC_SourcePin);
+   @endcode
+ *
+ * @param base SMC peripheral base address.
+ * @return All reset source status bit map.
+ */
+static inline uint32_t SMC_GetPreviousResetSources(SMC_Type *base)
+{
+    return base->SRS;
+}
+
+/*!
+ * @brief Gets the sticky reset source status.
+ *
+ * This function gets the current reset source status that has not been cleared
+ * by software for some specific source.
+ *
+ * Example:
+   @code
+   uint32_t resetStatus;
+
+   // To get all reset source statuses.
+   resetStatus = SMC_GetStickyResetSources(SMC0) & kSMC_SourceAll;
+
+   // To test whether the MCU is reset using Watchdog.
+   resetStatus = SMC_GetStickyResetSources(SMC0) & kSMC_SourceWdog;
+
+   // To test multiple reset sources.
+   resetStatus = SMC_GetStickyResetSources(SMC0) & (kSMC_SourceWdog | kSMC_SourcePin);
+   @endcode
+ *
+ * @param base SMC peripheral base address.
+ * @return All reset source status bit map.
+ */
+static inline uint32_t SMC_GetStickyResetSources(SMC_Type *base)
+{
+    return base->SSRS;
+}
+
+/*!
+ * @brief Clears the sticky reset source status.
+ *
+ * This function clears the sticky system reset flags indicated by source masks.
+ *
+ * Example:
+   @code
+   // Clears multiple reset sources.
+   SMC_ClearStickyResetSources(SMC0, (kSMC_SourceWdog | kSMC_SourcePin));
+   @endcode
+ *
+ * @param base SMC peripheral base address.
+ * @param sourceMasks reset source status bit map
+ */
+static inline void SMC_ClearStickyResetSources(SMC_Type *base, uint32_t sourceMasks)
+{
+    base->SSRS = sourceMasks;
+}
+
+/*!
+ * @brief Configures the reset pin filter.
+ *
+ * This function sets the reset pin filter including the enablement/disablement and filter width.
+ *
+ * @param base SMC peripheral base address.
+ * @param config Pointer to the configuration structure.
+ */
+void SMC_ConfigureResetPinFilter(SMC_Type *base, const smc_reset_pin_filter_config_t *config);
+
+/*!
+ * @brief Sets the system reset interrupt configuration.
+ *
+ * For a graceful shut down, the MSMC supports delaying the assertion of the system
+ * reset for a period of time when the reset interrupt is generated. This function
+ * can be used to enable the interrupt.
+ * The interrupts are passed in as bit mask. See smc_interrupt_enable_t for details.
+ * For example, to delay a reset after the WDOG timeout or PIN reset occurs, configure as follows:
+ * SMC_SetSystemResetInterruptConfig(SMC0, (kSMC_IntWdog | kSMC_IntPin));
+ *
+ * @param base SMC peripheral base address.
+ * @param intMask   Bit mask of the system reset interrupts to enable. See
+ *                  smc_interrupt_enable_t for details.
+ */
+static inline void SMC_SetSystemResetInterruptConfig(SMC_Type *base, uint32_t intMask)
+{
+    base->SRIE = intMask;
+}
+
+/*!
+ * @brief Gets the source status of the system reset interrupt.
+ *
+ * This function gets the source status of the reset interrupt. Use source masks
+ * defined in the smc_interrupt_enable_t to get the desired source status.
+ *
+ * Example:
+   @code
+   uint32_t interruptStatus;
+
+   // To get all reset interrupt source statuses.
+   interruptStatus = SMC_GetResetInterruptSourcesStatus(SMC0) & kSMC_IntAll;
+
+   // To test whether the reset interrupt of Watchdog is pending.
+   interruptStatus = SMC_GetResetInterruptSourcesStatus(SMC0) & kSMC_IntWdog;
+
+   // To test multiple reset interrupt sources.
+   interruptStatus = SMC_GetResetInterruptSourcesStatus(SMC0) & (kSMC_IntWdog | kSMC_IntPin);
+   @endcode
+ *
+ * @param base SMC peripheral base address.
+ * @return All reset interrupt source status bit map.
+ */
+static inline uint32_t SMC_GetResetInterruptSourcesStatus(SMC_Type *base)
+{
+    return base->SRIF;
+}
+
+/*!
+ * @brief Clears the source status of the system reset interrupt.
+ *
+ * This function clears the source status of the reset interrupt. Use source masks
+ * defined in the smc_interrupt_enable_t to get the desired source status.
+ *
+ * Example:
+   @code
+   uint32_t interruptStatus;
+
+   // To clear all reset interrupt source statuses.
+   MMC_ClearResetInterruptSourcesStatus(SMC0, kSMC_IntAll);
+
+   // To clear the reset interrupt of Watchdog.
+   SMC_ClearResetInterruptSourcesStatus(SMC0, kSMC_IntWdog);
+
+   // To clear multiple reset interrupt sources status.
+   SMC_ClearResetInterruptSourcesStatus(SMC0, (kSMC_IntWdog | kSMC_IntPin));
+   @endcode
+ *
+ * @param base SMC peripheral base address.
+ * @param All reset interrupt source status bit map to clear.
+ */
+static inline void SMC_ClearResetInterruptSourcesStatus(SMC_Type *base, uint32_t intMask)
+{
+    base->SRIF = intMask;
+}
+
+#if (defined(FSL_FEATURE_SMC_HAS_CSRE) && FSL_FEATURE_SMC_HAS_CSRE)
+/*!
+ * @brief Sets the core software reset feature configuration.
+ *
+ * The MSMC supports delaying the assertion of the system reset for a period of time while a core
+ * software reset is generated. This allows software to recover without reseting the entire system.
+ * This function can be used to enable/disable the core software reset feature.
+ * The interrupts are passed in as bit mask. See smc_interrupt_enable_t for details.
+ * For example, to delay a system after the WDOG timeout or PIN core software reset occurs, configure as follows:
+ * SMC_SetCoreSoftwareResetConfig(SMC0, (kSMC_IntWdog | kSMC_IntPin));
+ *
+ * @param base SMC peripheral base address.
+ * @param intMask   Bit mask of the core software reset to enable. See
+ *                  smc_interrupt_enable_t for details.
+ */
+static inline void SMC_SetCoreSoftwareResetConfig(SMC_Type *base, uint32_t intMask)
+{
+    base->CSRE = intMask;
+}
+#endif /* FSL_FEATURE_SMC_HAS_CSRE */
+
+/*!
+ * @brief Gets the boot option configuration.
+ *
+ * This function gets the boot option configuration of MSMC.
+ *
+ * @param base SMC peripheral base address.
+ * @return The boot option configuration. 1 means boot option enabled. 0 means not.
+ */
+static inline uint32_t SMC_GetBootOptionConfig(SMC_Type *base)
+{
+    return base->MR;
+}
+
+#if (defined(FSL_FEATURE_SMC_HAS_FM) && FSL_FEATURE_SMC_HAS_FM)
+/*!
+ * @brief Sets the force boot option configuration.
+ *
+ * This function sets the focus boot option configuration of MSMC. It can force the corresponding
+ * boot option config to assert on next system reset.
+ *
+ * @param base SMC peripheral base address.
+ * @param val The boot option configuration for next system reset. 1 - boot option enabled. 0 - not.
+ */
+static inline void SMC_SetForceBootOptionConfig(SMC_Type *base, uint32_t val)
+{
+    base->FM = val;
+}
+
+#if (defined(FSL_FEATURE_SMC_HAS_SRAMLPR) && FSL_FEATURE_SMC_HAS_SRAMLPR)
+/*!
+ * @brief Enables the conresponding SRAM array in low power retention mode.
+ *
+ * This function enables the conresponding SRAM array in low power retention mode. By default, the SRAM low pwer is
+ * disabled, and only in RUN mode.
+ *
+ * @param base SMC peripheral base address.
+ * @param arrayIdx Index of responding SRAM array.
+ * @param enable Enable the SRAM array in low power retention mode.
+ */
+static inline void SMC_SRAMEnableLowPowerMode(SMC_Type *base, uint32_t arrayIdx, bool enable)
+{
+    if (enable)
+    {
+        base->SRAMLPR |= (1U << arrayIdx); /* Set to be placed in RUN modes. */
+    }
+    else
+    {
+        base->SRAMLPR &= ~(1U << arrayIdx); /* Clear to be placed in low power retention mode. */
+    }
+}
+#endif /* FSL_FEATURE_SMC_HAS_SRAMLPR */
+
+#if (defined(FSL_FEATURE_SMC_HAS_SRAMDSR) && FSL_FEATURE_SMC_HAS_SRAMDSR)
+/*!
+ * @brief Enables the conresponding SRAM array in STOP mode.
+ *
+ * This function enables the conresponding SRAM array in STOP modes. By default, the SRAM is retained in STOP modes.
+ * When disabled, the corresponding SRAM array is powered off in STOP modes.
+ *
+ * @param base SMC peripheral base address.
+ * @param arrayIdx Index of responding SRAM array.
+ * @param enable Enable the SRAM array in STOP modes.
+ */
+static inline void SMC_SRAMEnableDeepSleepMode(SMC_Type *base, uint32_t arrayIdx, bool enable)
+{
+    if (enable)
+    {
+        base->SRAMDSR &= ~(1U << arrayIdx); /* Clear to be retained in STOP modes. */
+    }
+    else
+    {
+        base->SRAMDSR |= (1U << arrayIdx); /* Set to be powered off in STOP modes. */
+    }
+}
+#endif /* FSL_FEATURE_SMC_HAS_SRAMDSR */
+
+#endif /* FSL_FEATURE_SMC_HAS_FM */
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* _FSL_MSMC_H_ */

FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/drivers/fsl_port.h

@@ -0,0 +1,464 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ * 
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_PORT_H_
+#define _FSL_PORT_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup port
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! Version 2.0.2. */
+#define FSL_PORT_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+#if defined(FSL_FEATURE_PORT_HAS_PULL_ENABLE) && FSL_FEATURE_PORT_HAS_PULL_ENABLE
+/*! @brief Internal resistor pull feature selection */
+enum _port_pull
+{
+    kPORT_PullDisable = 0U, /*!< Internal pull-up/down resistor is disabled. */
+    kPORT_PullDown = 2U,    /*!< Internal pull-down resistor is enabled. */
+    kPORT_PullUp = 3U,      /*!< Internal pull-up resistor is enabled. */
+};
+#endif /* FSL_FEATURE_PORT_HAS_PULL_ENABLE */
+
+#if defined(FSL_FEATURE_PORT_HAS_SLEW_RATE) && FSL_FEATURE_PORT_HAS_SLEW_RATE
+/*! @brief Slew rate selection */
+enum _port_slew_rate
+{
+    kPORT_FastSlewRate = 0U, /*!< Fast slew rate is configured. */
+    kPORT_SlowSlewRate = 1U, /*!< Slow slew rate is configured. */
+};
+#endif /* FSL_FEATURE_PORT_HAS_SLEW_RATE */
+
+#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN
+/*! @brief Open Drain feature enable/disable */
+enum _port_open_drain_enable
+{
+    kPORT_OpenDrainDisable = 0U, /*!< Open drain output is disabled. */
+    kPORT_OpenDrainEnable = 1U,  /*!< Open drain output is enabled. */
+};
+#endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */
+
+#if defined(FSL_FEATURE_PORT_HAS_PASSIVE_FILTER) && FSL_FEATURE_PORT_HAS_PASSIVE_FILTER
+/*! @brief Passive filter feature enable/disable */
+enum _port_passive_filter_enable
+{
+    kPORT_PassiveFilterDisable = 0U, /*!< Passive input filter is disabled. */
+    kPORT_PassiveFilterEnable = 1U,  /*!< Passive input filter is enabled. */
+};
+#endif
+
+#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH
+/*! @brief Configures the drive strength. */
+enum _port_drive_strength
+{
+    kPORT_LowDriveStrength = 0U,  /*!< Low-drive strength is configured. */
+    kPORT_HighDriveStrength = 1U, /*!< High-drive strength is configured. */
+};
+#endif /* FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH */
+
+#if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK
+/*! @brief Unlock/lock the pin control register field[15:0] */
+enum _port_lock_register
+{
+    kPORT_UnlockRegister = 0U, /*!< Pin Control Register fields [15:0] are not locked. */
+    kPORT_LockRegister = 1U,   /*!< Pin Control Register fields [15:0] are locked. */
+};
+#endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */
+
+#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
+/*! @brief Pin mux selection */
+typedef enum _port_mux
+{
+    kPORT_PinDisabledOrAnalog = 0U, /*!< Corresponding pin is disabled, but is used as an analog pin. */
+    kPORT_MuxAsGpio = 1U,           /*!< Corresponding pin is configured as GPIO. */
+    kPORT_MuxAlt2 = 2U,             /*!< Chip-specific */
+    kPORT_MuxAlt3 = 3U,             /*!< Chip-specific */
+    kPORT_MuxAlt4 = 4U,             /*!< Chip-specific */
+    kPORT_MuxAlt5 = 5U,             /*!< Chip-specific */
+    kPORT_MuxAlt6 = 6U,             /*!< Chip-specific */
+    kPORT_MuxAlt7 = 7U,             /*!< Chip-specific */
+    kPORT_MuxAlt8 = 8U,             /*!< Chip-specific */
+    kPORT_MuxAlt9 = 9U,             /*!< Chip-specific */
+    kPORT_MuxAlt10 = 10U,           /*!< Chip-specific */
+    kPORT_MuxAlt11 = 11U,           /*!< Chip-specific */
+    kPORT_MuxAlt12 = 12U,           /*!< Chip-specific */
+    kPORT_MuxAlt13 = 13U,           /*!< Chip-specific */
+    kPORT_MuxAlt14 = 14U,           /*!< Chip-specific */
+    kPORT_MuxAlt15 = 15U,           /*!< Chip-specific */
+} port_mux_t;
+#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */
+
+/*! @brief Configures the interrupt generation condition. */
+typedef enum _port_interrupt
+{
+    kPORT_InterruptOrDMADisabled = 0x0U, /*!< Interrupt/DMA request is disabled. */
+#if defined(FSL_FEATURE_PORT_HAS_DMA_REQUEST) && FSL_FEATURE_PORT_HAS_DMA_REQUEST
+    kPORT_DMARisingEdge = 0x1U,  /*!< DMA request on rising edge. */
+    kPORT_DMAFallingEdge = 0x2U, /*!< DMA request on falling edge. */
+    kPORT_DMAEitherEdge = 0x3U,  /*!< DMA request on either edge. */
+#endif
+#if defined(FSL_FEATURE_PORT_HAS_IRQC_FLAG) && FSL_FEATURE_PORT_HAS_IRQC_FLAG
+    kPORT_FlagRisingEdge = 0x05U,  /*!< Flag sets on rising edge. */
+    kPORT_FlagFallingEdge = 0x06U, /*!< Flag sets on falling edge. */
+    kPORT_FlagEitherEdge = 0x07U,  /*!< Flag sets on either edge. */
+#endif
+    kPORT_InterruptLogicZero = 0x8U,   /*!< Interrupt when logic zero. */
+    kPORT_InterruptRisingEdge = 0x9U,  /*!< Interrupt on rising edge. */
+    kPORT_InterruptFallingEdge = 0xAU, /*!< Interrupt on falling edge. */
+    kPORT_InterruptEitherEdge = 0xBU,  /*!< Interrupt on either edge. */
+    kPORT_InterruptLogicOne = 0xCU,    /*!< Interrupt when logic one. */
+#if defined(FSL_FEATURE_PORT_HAS_IRQC_TRIGGER) && FSL_FEATURE_PORT_HAS_IRQC_TRIGGER
+    kPORT_ActiveHighTriggerOutputEnable = 0xDU, /*!< Enable active high-trigger output. */
+    kPORT_ActiveLowTriggerOutputEnable = 0xEU,  /*!< Enable active low-trigger output. */
+#endif
+} port_interrupt_t;
+
+#if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
+/*! @brief Digital filter clock source selection */
+typedef enum _port_digital_filter_clock_source
+{
+    kPORT_BusClock = 0U, /*!< Digital filters are clocked by the bus clock. */
+    kPORT_LpoClock = 1U, /*!< Digital filters are clocked by the 1 kHz LPO clock. */
+} port_digital_filter_clock_source_t;
+
+/*! @brief PORT digital filter feature configuration definition */
+typedef struct _port_digital_filter_config
+{
+    uint32_t digitalFilterWidth;                    /*!< Set digital filter width */
+    port_digital_filter_clock_source_t clockSource; /*!< Set digital filter clockSource */
+} port_digital_filter_config_t;
+#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */
+
+#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
+/*! @brief PORT pin configuration structure */
+typedef struct _port_pin_config
+{
+#if defined(FSL_FEATURE_PORT_HAS_PULL_ENABLE) && FSL_FEATURE_PORT_HAS_PULL_ENABLE
+    uint16_t pullSelect : 2; /*!< No-pull/pull-down/pull-up select */
+#else
+    uint16_t : 2;
+#endif /* FSL_FEATURE_PORT_HAS_PULL_ENABLE */
+
+#if defined(FSL_FEATURE_PORT_HAS_SLEW_RATE) && FSL_FEATURE_PORT_HAS_SLEW_RATE
+    uint16_t slewRate : 1; /*!< Fast/slow slew rate Configure */
+#else
+    uint16_t : 1;
+#endif /* FSL_FEATURE_PORT_HAS_SLEW_RATE */
+
+    uint16_t : 1;
+
+#if defined(FSL_FEATURE_PORT_HAS_PASSIVE_FILTER) && FSL_FEATURE_PORT_HAS_PASSIVE_FILTER
+    uint16_t passiveFilterEnable : 1; /*!< Passive filter enable/disable */
+#else
+    uint16_t : 1;
+#endif /* FSL_FEATURE_PORT_HAS_PASSIVE_FILTER */
+
+#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN
+    uint16_t openDrainEnable : 1; /*!< Open drain enable/disable */
+#else
+    uint16_t : 1;
+#endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */
+
+#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH
+    uint16_t driveStrength : 1; /*!< Fast/slow drive strength configure */
+#else
+    uint16_t : 1;
+#endif
+
+    uint16_t : 1;
+
+#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && (FSL_FEATURE_PORT_PCR_MUX_WIDTH == 3)
+    uint16_t mux : 3; /*!< Pin mux Configure */
+    uint16_t : 4;
+#elif defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && (FSL_FEATURE_PORT_PCR_MUX_WIDTH == 4)
+    uint16_t mux : 4; /*!< Pin mux Configure */
+    uint16_t : 3;
+#else
+    uint16_t : 7,
+#endif
+
+#if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK
+    uint16_t lockRegister : 1; /*!< Lock/unlock the PCR field[15:0] */
+#else
+    uint16_t : 1;
+#endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */
+} port_pin_config_t;
+#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */
+
+/*******************************************************************************
+* API
+******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the port PCR register.
+ *
+ * This is an example to define an input pin or output pin PCR configuration.
+ * @code
+ * // Define a digital input pin PCR configuration
+ * port_pin_config_t config = {
+ *      kPORT_PullUp,
+ *      kPORT_FastSlewRate,
+ *      kPORT_PassiveFilterDisable,
+ *      kPORT_OpenDrainDisable,
+ *      kPORT_LowDriveStrength,
+ *      kPORT_MuxAsGpio,
+ *      kPORT_UnLockRegister,
+ * };
+ * @endcode
+ *
+ * @param base   PORT peripheral base pointer.
+ * @param pin    PORT pin number.
+ * @param config PORT PCR register configuration structure.
+ */
+static inline void PORT_SetPinConfig(PORT_Type *base, uint32_t pin, const port_pin_config_t *config)
+{
+    assert(config);
+    uint32_t addr = (uint32_t)&base->PCR[pin];
+    *(volatile uint16_t *)(addr) = *((const uint16_t *)config);
+}
+
+/*!
+ * @brief Sets the port PCR register for multiple pins.
+ *
+ * This is an example to define input pins or output pins PCR configuration.
+ * @code
+ * // Define a digital input pin PCR configuration
+ * port_pin_config_t config = {
+ *      kPORT_PullUp ,
+ *      kPORT_PullEnable,
+ *      kPORT_FastSlewRate,
+ *      kPORT_PassiveFilterDisable,
+ *      kPORT_OpenDrainDisable,
+ *      kPORT_LowDriveStrength,
+ *      kPORT_MuxAsGpio,
+ *      kPORT_UnlockRegister,
+ * };
+ * @endcode
+ *
+ * @param base   PORT peripheral base pointer.
+ * @param mask   PORT pin number macro.
+ * @param config PORT PCR register configuration structure.
+ */
+static inline void PORT_SetMultiplePinsConfig(PORT_Type *base, uint32_t mask, const port_pin_config_t *config)
+{
+    assert(config);
+
+    uint16_t pcrl = *((const uint16_t *)config);
+
+    if (mask & 0xffffU)
+    {
+        base->GPCLR = ((mask & 0xffffU) << 16) | pcrl;
+    }
+    if (mask >> 16)
+    {
+        base->GPCHR = (mask & 0xffff0000U) | pcrl;
+    }
+}
+
+#if defined(FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG) && FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG
+/*!
+ * @brief Sets the port interrupt configuration in PCR register for multiple pins.
+ *
+ * @param base   PORT peripheral base pointer.
+ * @param mask   PORT pin number macro.
+ * @param config  PORT pin interrupt configuration.
+ *        - #kPORT_InterruptOrDMADisabled: Interrupt/DMA request disabled.
+ *        - #kPORT_DMARisingEdge : DMA request on rising edge(if the DMA requests exit).
+ *        - #kPORT_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit).
+ *        - #kPORT_DMAEitherEdge : DMA request on either edge(if the DMA requests exit).
+ *        - #kPORT_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit).
+ *        - #kPORT_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit).
+ *        - #kPORT_FlagEitherEdge : Flag sets on either edge(if the Flag states exit).
+ *        - #kPORT_InterruptLogicZero  : Interrupt when logic zero.
+ *        - #kPORT_InterruptRisingEdge : Interrupt on rising edge.
+ *        - #kPORT_InterruptFallingEdge: Interrupt on falling edge.
+ *        - #kPORT_InterruptEitherEdge : Interrupt on either edge.
+ *        - #kPORT_InterruptLogicOne   : Interrupt when logic one.
+ *        - #kPORT_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit).
+ *        - #kPORT_ActiveLowTriggerOutputEnable  : Enable active low-trigger output (if the trigger states exit)..
+ */
+static inline void PORT_SetMultipleInterruptPinsConfig(PORT_Type *base, uint32_t mask, port_interrupt_t config)
+{
+    assert(config);
+
+    if (mask & 0xffffU)
+    {
+        base->GICLR = (config << 16) | (mask & 0xffffU);
+    }
+    if (mask >> 16)
+    {
+        base->GICHR = (config << 16) | (mask & 0xffff0000U);
+    }
+}
+#endif
+
+/*!
+ * @brief Configures the pin muxing.
+ *
+ * @param base  PORT peripheral base pointer.
+ * @param pin   PORT pin number.
+ * @param mux   pin muxing slot selection.
+ *        - #kPORT_PinDisabledOrAnalog: Pin disabled or work in analog function.
+ *        - #kPORT_MuxAsGpio          : Set as GPIO.
+ *        - #kPORT_MuxAlt2            : chip-specific.
+ *        - #kPORT_MuxAlt3            : chip-specific.
+ *        - #kPORT_MuxAlt4            : chip-specific.
+ *        - #kPORT_MuxAlt5            : chip-specific.
+ *        - #kPORT_MuxAlt6            : chip-specific.
+ *        - #kPORT_MuxAlt7            : chip-specific.
+ * @Note : This function is NOT recommended to use together with the PORT_SetPinsConfig, because
+ *         the PORT_SetPinsConfig need to configure the pin mux anyway (Otherwise the pin mux is
+ *         reset to zero : kPORT_PinDisabledOrAnalog).
+ *        This function is recommended to use to reset the pin mux
+ *
+ */
+static inline void PORT_SetPinMux(PORT_Type *base, uint32_t pin, port_mux_t mux)
+{
+    base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(mux);
+}
+#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */
+
+#if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
+
+/*!
+ * @brief Enables the digital filter in one port, each bit of the 32-bit register represents one pin.
+ *
+ * @param base  PORT peripheral base pointer.
+ * @param mask  PORT pin number macro.
+ */
+static inline void PORT_EnablePinsDigitalFilter(PORT_Type *base, uint32_t mask, bool enable)
+{
+    if (enable == true)
+    {
+        base->DFER |= mask;
+    }
+    else
+    {
+        base->DFER &= ~mask;
+    }
+}
+
+/*!
+ * @brief Sets the digital filter in one port, each bit of the 32-bit register represents one pin.
+ *
+ * @param base   PORT peripheral base pointer.
+ * @param config PORT digital filter configuration structure.
+ */
+static inline void PORT_SetDigitalFilterConfig(PORT_Type *base, const port_digital_filter_config_t *config)
+{
+    assert(config);
+
+    base->DFCR = PORT_DFCR_CS(config->clockSource);
+    base->DFWR = PORT_DFWR_FILT(config->digitalFilterWidth);
+}
+
+#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */
+
+/*@}*/
+
+/*! @name Interrupt */
+/*@{*/
+
+/*!
+ * @brief Configures the port pin interrupt/DMA request.
+ *
+ * @param base    PORT peripheral base pointer.
+ * @param pin     PORT pin number.
+ * @param config  PORT pin interrupt configuration.
+ *        - #kPORT_InterruptOrDMADisabled: Interrupt/DMA request disabled.
+ *        - #kPORT_DMARisingEdge : DMA request on rising edge(if the DMA requests exit).
+ *        - #kPORT_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit).
+ *        - #kPORT_DMAEitherEdge : DMA request on either edge(if the DMA requests exit).
+ *        - #kPORT_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit).
+ *        - #kPORT_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit).
+ *        - #kPORT_FlagEitherEdge : Flag sets on either edge(if the Flag states exit).
+ *        - #kPORT_InterruptLogicZero  : Interrupt when logic zero.
+ *        - #kPORT_InterruptRisingEdge : Interrupt on rising edge.
+ *        - #kPORT_InterruptFallingEdge: Interrupt on falling edge.
+ *        - #kPORT_InterruptEitherEdge : Interrupt on either edge.
+ *        - #kPORT_InterruptLogicOne   : Interrupt when logic one.
+ *        - #kPORT_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit).
+ *        - #kPORT_ActiveLowTriggerOutputEnable  : Enable active low-trigger output (if the trigger states exit).
+ */
+static inline void PORT_SetPinInterruptConfig(PORT_Type *base, uint32_t pin, port_interrupt_t config)
+{
+    base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_IRQC_MASK) | PORT_PCR_IRQC(config);
+}
+
+#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH
+/*!
+ * @brief Configures the port pin drive strength.
+ *
+ * @param base    PORT peripheral base pointer.
+ * @param pin     PORT pin number.
+ * @param config  PORT pin drive strength
+ *        - #kPORT_LowDriveStrength = 0U - Low-drive strength is configured.
+ *        - #kPORT_HighDriveStrength = 1U - High-drive strength is configured.
+ */
+static inline void PORT_SetPinDriveStrength(PORT_Type* base, uint32_t pin, uint8_t strength)
+{
+    base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_DSE_MASK) |  PORT_PCR_DSE(strength);
+}
+#endif
+
+/*!
+ * @brief Reads the whole port status flag.
+ *
+ * If a pin is configured to generate the DMA request,  the corresponding flag
+ * is cleared automatically at the completion of the requested DMA transfer.
+ * Otherwise, the flag remains set until a logic one is written to that flag.
+ * If configured for a level sensitive interrupt that remains asserted, the flag
+ * is set again immediately.
+ *
+ * @param base PORT peripheral base pointer.
+ * @return Current port interrupt status flags, for example, 0x00010001 means the
+ *         pin 0 and 16 have the interrupt.
+ */
+static inline uint32_t PORT_GetPinsInterruptFlags(PORT_Type *base)
+{
+    return base->ISFR;
+}
+
+/*!
+ * @brief Clears the multiple pin interrupt status flag.
+ *
+ * @param base PORT peripheral base pointer.
+ * @param mask PORT pin number macro.
+ */
+static inline void PORT_ClearPinsInterruptFlags(PORT_Type *base, uint32_t mask)
+{
+    base->ISFR = mask;
+}
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_PORT_H_ */

FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/fsl_device_registers.h

@@ -0,0 +1,62 @@
+/*
+ * Copyright 2014-2016 Freescale Semiconductor, Inc.
+ * Copyright 2016-2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __FSL_DEVICE_REGISTERS_H__
+#define __FSL_DEVICE_REGISTERS_H__
+
+/*
+ * Include the cpu specific register header files.
+ *
+ * The CPU macro should be declared in the project or makefile.
+ */
+#if defined(CPU_RV32M1_cm0plus)
+
+#define RV32M1_cm0plus_SERIES
+
+/* CMSIS-style register definitions */
+#include "RV32M1_cm0plus.h"
+/* CPU specific feature definitions */
+#include "RV32M1_cm0plus_features.h"
+
+#elif defined(CPU_RV32M1_cm4)
+
+#define RV32M1_cm4_SERIES
+
+/* CMSIS-style register definitions */
+#include "RV32M1_cm4.h"
+/* CPU specific feature definitions */
+#include "RV32M1_cm4_features.h"
+
+#elif defined(CPU_RV32M1_zero_riscy)
+
+#define RV32M1_zero_riscy_SERIES
+
+/* CMSIS-style register definitions */
+#include "RV32M1_zero_riscy.h"
+/* CPU specific feature definitions */
+#include "RV32M1_zero_riscy_features.h"
+
+#elif defined(CPU_RV32M1_ri5cy)
+
+#define RV32M1_ri5cy_SERIES
+
+/* CMSIS-style register definitions */
+#include "RV32M1_ri5cy.h"
+/* CPU specific feature definitions */
+#include "RV32M1_ri5cy_features.h"
+
+#else
+    #error "No valid CPU defined!"
+#endif
+
+#endif /* __FSL_DEVICE_REGISTERS_H__ */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/

FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/gcc/startup_RV32M1_ri5cy.S

@@ -0,0 +1,228 @@
+/* ------------------------------------------------------------------------- */
+/*  @file:    startup_RV32M1_ri5cy.s                                         */
+/*  @purpose: RI5CY Core Device Startup File                                 */
+/*            RV32M1_ri5cy                                                   */
+/*  @version: 1.0                                                            */
+/*  @date:    2018-10-2                                                      */
+/*  @build:   b180926                                                        */
+/* ------------------------------------------------------------------------- */
+/*                                                                           */
+/* Copyright 1997-2016 Freescale Semiconductor, Inc.                         */
+/* Copyright 2016-2018 NXP                                                   */
+/* All rights reserved.                                                      */
+/*                                                                           */
+/* SPDX-License-Identifier: BSD-3-Clause                                     */
+
+
+// Copyright 2017 ETH Zurich and University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the "License"); you may not use this file except in
+// compliance with the License.  You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+
+.extern freertos_risc_v_trap_handler
+
+#define EXCEPTION_STACK_SIZE 0x58
+
+    .text
+    .section .vectors, "ax"
+    .option norvc;
+
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+    jal x0, freertos_risc_v_trap_handler
+
+    // reset vector
+    jal x0, Reset_Handler
+
+    // Illegal instrution exception
+    jal x0, IllegalInstruction_Handler
+
+    // ecall handler
+    jal x0, freertos_risc_v_trap_handler
+
+    // LSU error
+    jal x0, LSU_Handler
+
+    .section .startup
+
+/* Reset Handler */
+Reset_Handler:
+
+    # Disable global interrupt. */
+    csrci mstatus, 8
+
+    # initialize stack pointer
+    la sp, __StackTop
+
+    # initialize global pointer
+    la gp, __global_pointer
+
+#ifndef __NO_SYSTEM_INIT
+    jal SystemInit
+#endif
+
+    call __libc_init_array
+
+    # Enable global interrupt. */
+    csrsi mstatus, 8
+
+    jal main
+    ebreak
+
+    .size Reset_Handler, . - Reset_Handler
+
+    .global _init
+    .global _fini
+_init:
+_fini:
+    ret
+
+  // saves all caller-saved registers (except return address)
+store_regs:
+    sw  x3, 0x00(x2)  // gp
+    sw  x4, 0x04(x2)  // tp
+    sw  x5, 0x08(x2)  // t0
+    sw  x6, 0x0c(x2)  // t1
+    sw  x7, 0x10(x2)  // t2
+    sw x10, 0x14(x2)  // a0
+    sw x11, 0x18(x2)  // a1
+    sw x12, 0x1c(x2)  // a2
+    sw x13, 0x20(x2)  // a3
+    sw x14, 0x24(x2)  // a4
+    sw x15, 0x28(x2)  // a5
+    sw x16, 0x2c(x2)  // a6
+    sw x17, 0x30(x2)  // a7
+
+    csrr a0, 0x7B0
+    csrr a1, 0x7B1
+    csrr a2, 0x7B2
+    sw a0, 0x34(x2)  // lpstart[0]
+    sw a1, 0x38(x2)  // lpend[0]
+    sw a2, 0x3c(x2)  // lpcount[0]
+    csrr a0, 0x7B4
+    csrr a1, 0x7B5
+    csrr a2, 0x7B6
+    sw a0, 0x40(x2)  // lpstart[1]
+    sw a1, 0x44(x2)  // lpend[1]
+    sw a2, 0x48(x2)  // lpcount[1]
+
+    csrr a0, 0x341
+    sw a0, 0x4c(x2)  // mepc
+    csrr a1, 0x300
+    sw a1, 0x50(x2)  // mstatus
+    jalr x0, x1
+
+    // load back registers from stack
+end_except:
+    lw a1, 0x50(x2)  // mstatus
+    csrrw x0, 0x300, a1
+    lw a0, 0x4c(x2)  // mepc
+    csrrw x0, 0x341, a0
+
+    lw a0, 0x40(x2)  // lpstart[1]
+    lw a1, 0x44(x2)  // lpend[1]
+    lw a2, 0x48(x2)  // lpcount[1]
+    csrrw x0, 0x7B4, a0
+    csrrw x0, 0x7B5, a1
+    csrrw x0, 0x7B6, a2
+    lw a0, 0x34(x2)  // lpstart[0]
+    lw a1, 0x38(x2)  // lpend[0]
+    lw a2, 0x3c(x2)  // lpcount[0]
+    csrrw x0, 0x7B0, a0
+    csrrw x0, 0x7B1, a1
+    csrrw x0, 0x7B2, a2
+
+    lw  x3, 0x00(x2)  // gp
+    lw  x4, 0x04(x2)  // tp
+    lw  x5, 0x08(x2)  // t0
+    lw  x6, 0x0c(x2)  // t1
+    lw  x7, 0x10(x2)  // t2
+    lw x10, 0x14(x2)  // a0
+    lw x11, 0x18(x2)  // a1
+    lw x12, 0x1c(x2)  // a2
+    lw x13, 0x20(x2)  // a3
+    lw x14, 0x24(x2)  // a4
+    lw x15, 0x28(x2)  // a5
+    lw x16, 0x2c(x2)  // a6
+    lw x17, 0x30(x2)  // a7
+
+    lw  x1, 0x54(x2)
+    addi x2, x2, EXCEPTION_STACK_SIZE
+    mret
+
+    .weak IRQ_Handler
+    .type IRQ_Handler, %function
+IRQ_Handler:
+    addi x2, x2, -EXCEPTION_STACK_SIZE
+    sw x1, 0x54(x2)
+    jal x1, store_regs
+    la x1, end_except
+    csrr a0, mcause
+    jal x0, SystemIrqHandler
+    .size IRQ_Handler, . - IRQ_Handler
+
+    .macro define_exception_entry entry_name handler_name
+    .weak \entry_name
+\entry_name:
+    addi x2, x2, -EXCEPTION_STACK_SIZE
+    sw x1, 0x54(x2)
+    jal x1, store_regs
+    la x1, end_except
+    jal x0, \handler_name
+    .endm
+
+define_exception_entry IllegalInstruction_Handler IllegalInstruction_HandlerFunc
+define_exception_entry Ecall_Handler Ecall_HandlerFunc
+define_exception_entry LSU_Handler LSU_HandlerFunc
+
+    .weak IllegalInstruction_HandlerFunc
+    .type IllegalInstruction_HandlerFunc, %function
+IllegalInstruction_HandlerFunc:
+    j .
+    .size IllegalInstruction_HandlerFunc, . - IllegalInstruction_HandlerFunc
+
+    .weak Ecall_HandlerFunc
+    .type Ecall_HandlerFunc, %function
+Ecall_HandlerFunc:
+    j .
+    .size Ecall_HandlerFunc, . - Ecall_HandlerFunc
+
+    .weak LSU_HandlerFunc
+    .type LSU_HandlerFunc, %function
+LSU_HandlerFunc:
+    j .
+    .size LSU_HandlerFunc, . - LSU_HandlerFunc

FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/gcc/startup_RV32M1_zero_riscy.S

@@ -0,0 +1,225 @@
+/* ------------------------------------------------------------------------- */
+/*  @file:    startup_RV32M1_zero_riscy.s                                    */
+/*  @purpose: ZERO_RISCY Core Device Startup File                            */
+/*            RV32M1_zero_riscy                                              */
+/*  @version: 1.0                                                            */
+/*  @date:    2018-10-2                                                      */
+/*  @build:   b180926                                                        */
+/* ------------------------------------------------------------------------- */
+/*                                                                           */
+/* Copyright 1997-2016 Freescale Semiconductor, Inc.                         */
+/* Copyright 2016-2018 NXP                                                   */
+/* All rights reserved.                                                      */
+/*                                                                           */
+/* SPDX-License-Identifier: BSD-3-Clause                                     */
+
+// Copyright 2017 ETH Zurich and University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the "License"); you may not use this file except in
+// compliance with the License.  You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+
+#define EXCEPTION_STACK_SIZE 0x58
+
+    .text
+    .section .vectors, "ax"
+    .option norvc;
+
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+    jal x0, IRQ_Handler
+
+    // reset vector
+    jal x0, Reset_Handler
+
+    // Illegal instrution exception
+    jal x0, IllegalInstruction_Handler
+
+    // ecall handler
+    jal x0, Ecall_Handler
+
+    // LSU error
+    jal x0, LSU_Handler
+
+    .section .startup
+
+/* Reset Handler */
+Reset_Handler:
+
+    # Disable global interrupt. */
+    csrci mstatus, 8
+
+    # initialize stack pointer
+    la sp, __StackTop
+
+    # initialize global pointer
+    la gp, __global_pointer
+
+#ifndef __NO_SYSTEM_INIT
+    jal SystemInit
+#endif
+
+    call __libc_init_array
+
+    # Enable global interrupt. */
+    csrsi mstatus, 8
+
+    jal main
+    ebreak
+
+    .size Reset_Handler, . - Reset_Handler
+
+    .global _init
+    .global _fini
+_init:
+_fini:
+    ret
+
+  // saves all caller-saved registers (except return address)
+store_regs:
+    sw  x3, 0x00(x2)  // gp
+    sw  x4, 0x04(x2)  // tp
+    sw  x5, 0x08(x2)  // t0
+    sw  x6, 0x0c(x2)  // t1
+    sw  x7, 0x10(x2)  // t2
+    sw x10, 0x14(x2)  // a0
+    sw x11, 0x18(x2)  // a1
+    sw x12, 0x1c(x2)  // a2
+    sw x13, 0x20(x2)  // a3
+    sw x14, 0x24(x2)  // a4
+    sw x15, 0x28(x2)  // a5
+    sw x16, 0x2c(x2)  // a6
+    sw x17, 0x30(x2)  // a7
+
+    csrr a0, 0x7B0
+    csrr a1, 0x7B1
+    csrr a2, 0x7B2
+    sw a0, 0x34(x2)  // lpstart[0]
+    sw a1, 0x38(x2)  // lpend[0]
+    sw a2, 0x3c(x2)  // lpcount[0]
+    csrr a0, 0x7B4
+    csrr a1, 0x7B5
+    csrr a2, 0x7B6
+    sw a0, 0x40(x2)  // lpstart[1]
+    sw a1, 0x44(x2)  // lpend[1]
+    sw a2, 0x48(x2)  // lpcount[1]
+
+    csrr a0, 0x341
+    sw a0, 0x4c(x2)  // mepc
+    csrr a1, 0x300
+    sw a1, 0x50(x2)  // mstatus
+    jalr x0, x1
+
+    // load back registers from stack
+end_except:
+    lw a1, 0x50(x2)  // mstatus
+    csrrw x0, 0x300, a1
+    lw a0, 0x4c(x2)  // mepc
+    csrrw x0, 0x341, a0
+
+    lw a0, 0x40(x2)  // lpstart[1]
+    lw a1, 0x44(x2)  // lpend[1]
+    lw a2, 0x48(x2)  // lpcount[1]
+    csrrw x0, 0x7B4, a0
+    csrrw x0, 0x7B5, a1
+    csrrw x0, 0x7B6, a2
+    lw a0, 0x34(x2)  // lpstart[0]
+    lw a1, 0x38(x2)  // lpend[0]
+    lw a2, 0x3c(x2)  // lpcount[0]
+    csrrw x0, 0x7B0, a0
+    csrrw x0, 0x7B1, a1
+    csrrw x0, 0x7B2, a2
+
+    lw  x3, 0x00(x2)  // gp
+    lw  x4, 0x04(x2)  // tp
+    lw  x5, 0x08(x2)  // t0
+    lw  x6, 0x0c(x2)  // t1
+    lw  x7, 0x10(x2)  // t2
+    lw x10, 0x14(x2)  // a0
+    lw x11, 0x18(x2)  // a1
+    lw x12, 0x1c(x2)  // a2
+    lw x13, 0x20(x2)  // a3
+    lw x14, 0x24(x2)  // a4
+    lw x15, 0x28(x2)  // a5
+    lw x16, 0x2c(x2)  // a6
+    lw x17, 0x30(x2)  // a7
+
+    lw  x1, 0x54(x2)
+    addi x2, x2, EXCEPTION_STACK_SIZE
+    mret
+
+    .weak IRQ_Handler
+    .type IRQ_Handler, %function
+IRQ_Handler:
+    addi x2, x2, -EXCEPTION_STACK_SIZE
+    sw x1, 0x54(x2)
+    jal x1, store_regs
+    la x1, end_except
+    csrr a0, mcause
+    jal x0, SystemIrqHandler
+    .size IRQ_Handler, . - IRQ_Handler
+
+    .macro define_exception_entry entry_name handler_name
+    .weak \entry_name
+\entry_name:
+    addi x2, x2, -EXCEPTION_STACK_SIZE
+    sw x1, 0x54(x2)
+    jal x1, store_regs
+    la x1, end_except
+    jal x0, \handler_name
+    .endm
+
+define_exception_entry IllegalInstruction_Handler IllegalInstruction_HandlerFunc
+define_exception_entry Ecall_Handler Ecall_HandlerFunc
+define_exception_entry LSU_Handler LSU_HandlerFunc
+
+    .weak IllegalInstruction_HandlerFunc
+    .type IllegalInstruction_HandlerFunc, %function
+IllegalInstruction_HandlerFunc:
+    j .
+    .size IllegalInstruction_HandlerFunc, . - IllegalInstruction_HandlerFunc
+
+    .weak Ecall_HandlerFunc
+    .type Ecall_HandlerFunc, %function
+Ecall_HandlerFunc:
+    j .
+    .size Ecall_HandlerFunc, . - Ecall_HandlerFunc
+
+    .weak LSU_HandlerFunc
+    .type LSU_HandlerFunc, %function
+LSU_HandlerFunc:
+    j .
+    .size LSU_HandlerFunc, . - LSU_HandlerFunc

FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/system_RV32M1_ri5cy.c

@@ -0,0 +1,556 @@
+/*
+** ###################################################################
+**     Processors:          RV32M1_ri5cy
+**                          RV32M1_ri5cy
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**                          MCUXpresso Compiler
+**
+**     Reference manual:    RV32M1 Series Reference Manual, Rev. 1 , 8/10/2018
+**     Version:             rev. 1.0, 2018-10-02
+**     Build:               b180926
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2018 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2018-10-02)
+**         Initial version.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file RV32M1_ri5cy
+ * @version 1.0
+ * @date 2018-10-02
+ * @brief Device specific configuration file for RV32M1_ri5cy
+ *        (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "fsl_device_registers.h"
+#include "fsl_common.h"
+
+typedef void (*irq_handler_t)(void);
+
+extern void DMA0_0_4_8_12_DriverIRQHandler(void);
+extern void DMA0_1_5_9_13_DriverIRQHandler(void);
+extern void DMA0_2_6_10_14_DriverIRQHandler(void);
+extern void DMA0_3_7_11_15_DriverIRQHandler(void);
+extern void DMA0_Error_IRQHandler(void);
+extern void CMC0_IRQHandler(void);
+extern void EWM_IRQHandler(void);
+extern void FTFE_Command_Complete_IRQHandler(void);
+extern void FTFE_Read_Collision_IRQHandler(void);
+extern void LLWU0_IRQHandler(void);
+extern void MUA_IRQHandler(void);
+extern void SPM_IRQHandler(void);
+extern void WDOG0_IRQHandler(void);
+extern void SCG_IRQHandler(void);
+extern void LPIT0_IRQHandler(void);
+extern void RTC_IRQHandler(void);
+extern void LPTMR0_IRQHandler(void);
+extern void LPTMR1_IRQHandler(void);
+extern void TPM0_IRQHandler(void);
+extern void TPM1_IRQHandler(void);
+extern void TPM2_IRQHandler(void);
+extern void EMVSIM0_IRQHandler(void);
+extern void FLEXIO0_DriverIRQHandler(void);
+extern void LPI2C0_DriverIRQHandler(void);
+extern void LPI2C1_DriverIRQHandler(void);
+extern void LPI2C2_DriverIRQHandler(void);
+extern void I2S0_DriverIRQHandler(void);
+extern void USDHC0_DriverIRQHandler(void);
+extern void LPSPI0_DriverIRQHandler(void);
+extern void LPSPI1_DriverIRQHandler(void);
+extern void LPSPI2_DriverIRQHandler(void);
+extern void LPUART0_DriverIRQHandler(void);
+extern void LPUART1_DriverIRQHandler(void);
+extern void LPUART2_DriverIRQHandler(void);
+extern void USB0_IRQHandler(void);
+extern void PORTA_IRQHandler(void);
+extern void PORTB_IRQHandler(void);
+extern void PORTC_IRQHandler(void);
+extern void PORTD_IRQHandler(void);
+extern void ADC0_IRQHandler(void);
+extern void LPCMP0_IRQHandler(void);
+extern void LPDAC0_IRQHandler(void);
+extern void CAU3_Task_Complete_IRQHandler(void);
+extern void CAU3_Security_Violation_IRQHandler(void);
+extern void TRNG_IRQHandler(void);
+extern void LPIT1_IRQHandler(void);
+extern void LPTMR2_IRQHandler(void);
+extern void TPM3_IRQHandler(void);
+extern void LPI2C3_DriverIRQHandler(void);
+extern void LPSPI3_DriverIRQHandler(void);
+extern void LPUART3_DriverIRQHandler(void);
+extern void PORTE_IRQHandler(void);
+extern void LPCMP1_IRQHandler(void);
+extern void RF0_0_IRQHandler(void);
+extern void RF0_1_IRQHandler(void);
+extern void INTMUX0_0_DriverIRQHandler(void);
+extern void INTMUX0_1_DriverIRQHandler(void);
+extern void INTMUX0_2_DriverIRQHandler(void);
+extern void INTMUX0_3_DriverIRQHandler(void);
+extern void INTMUX0_4_DriverIRQHandler(void);
+extern void INTMUX0_5_DriverIRQHandler(void);
+extern void INTMUX0_6_DriverIRQHandler(void);
+extern void INTMUX0_7_DriverIRQHandler(void);
+extern void INTMUX0_8_DriverIRQHandler(void);
+extern void DMA0_0_4_8_12_IRQHandler(void);
+extern void DMA0_1_5_9_13_IRQHandler(void);
+extern void DMA0_2_6_10_14_IRQHandler(void);
+extern void DMA0_3_7_11_15_IRQHandler(void);
+extern void FLEXIO0_IRQHandler(void);
+extern void LPI2C0_IRQHandler(void);
+extern void LPI2C1_IRQHandler(void);
+extern void LPI2C2_IRQHandler(void);
+extern void I2S0_IRQHandler(void);
+extern void USDHC0_IRQHandler(void);
+extern void LPSPI0_IRQHandler(void);
+extern void LPSPI1_IRQHandler(void);
+extern void LPSPI2_IRQHandler(void);
+extern void LPUART0_IRQHandler(void);
+extern void LPUART1_IRQHandler(void);
+extern void LPUART2_IRQHandler(void);
+extern void LPI2C3_IRQHandler(void);
+extern void LPSPI3_IRQHandler(void);
+extern void LPUART3_IRQHandler(void);
+extern void INTMUX0_0_IRQHandler(void);
+extern void INTMUX0_1_IRQHandler(void);
+extern void INTMUX0_2_IRQHandler(void);
+extern void INTMUX0_3_IRQHandler(void);
+extern void INTMUX0_4_IRQHandler(void);
+extern void INTMUX0_5_IRQHandler(void);
+extern void INTMUX0_6_IRQHandler(void);
+extern void INTMUX0_7_IRQHandler(void);
+
+/* ----------------------------------------------------------------------------
+   -- Core clock
+   ---------------------------------------------------------------------------- */
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+extern uint32_t __etext;
+extern uint32_t __data_start__;
+extern uint32_t __data_end__;
+
+extern uint32_t __bss_start__;
+extern uint32_t __bss_end__;
+
+static void copy_section(uint32_t * p_load, uint32_t * p_vma, uint32_t * p_vma_end)
+{
+    while(p_vma <= p_vma_end)
+    {
+        *p_vma = *p_load;
+        ++p_load;
+        ++p_vma;
+    }
+}
+
+static void zero_section(uint32_t * start, uint32_t * end)
+{
+    uint32_t * p_zero = start;
+
+    while(p_zero <= end)
+    {
+        *p_zero = 0;
+        ++p_zero;
+    }
+}
+
+#define DEFINE_IRQ_HANDLER(irq_handler, driver_irq_handler) \
+    void __attribute__((weak)) irq_handler(void) { driver_irq_handler();}
+
+#define DEFINE_DEFAULT_IRQ_HANDLER(irq_handler) void irq_handler() __attribute__((weak, alias("DefaultIRQHandler")))
+
+DEFINE_DEFAULT_IRQ_HANDLER(DMA0_0_4_8_12_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(DMA0_1_5_9_13_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(DMA0_2_6_10_14_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(DMA0_3_7_11_15_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(DMA0_Error_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(CMC0_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(EWM_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(FTFE_Command_Complete_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(FTFE_Read_Collision_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LLWU0_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(MUA_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(SPM_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(WDOG0_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(SCG_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPIT0_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(RTC_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPTMR0_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPTMR1_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(TPM0_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(TPM1_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(TPM2_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(EMVSIM0_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(FLEXIO0_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPI2C0_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPI2C1_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPI2C2_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(I2S0_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(USDHC0_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPSPI0_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPSPI1_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPSPI2_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPUART0_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPUART1_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPUART2_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(USB0_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(PORTA_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(PORTB_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(PORTC_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(PORTD_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(ADC0_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPCMP0_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPDAC0_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(CAU3_Task_Complete_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(CAU3_Security_Violation_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(TRNG_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPIT1_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPTMR2_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(TPM3_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPI2C3_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPSPI3_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPUART3_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(PORTE_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPCMP1_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(RF0_0_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(RF0_1_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_0_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_1_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_2_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_3_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_4_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_5_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_6_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_7_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_8_DriverIRQHandler);
+
+DEFINE_IRQ_HANDLER(DMA0_0_4_8_12_IRQHandler, DMA0_0_4_8_12_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(DMA0_1_5_9_13_IRQHandler, DMA0_1_5_9_13_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(DMA0_2_6_10_14_IRQHandler, DMA0_2_6_10_14_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(DMA0_3_7_11_15_IRQHandler, DMA0_3_7_11_15_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(FLEXIO0_IRQHandler, FLEXIO0_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(LPI2C0_IRQHandler, LPI2C0_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(LPI2C1_IRQHandler, LPI2C1_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(LPI2C2_IRQHandler, LPI2C2_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(I2S0_IRQHandler, I2S0_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(USDHC0_IRQHandler, USDHC0_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(LPSPI0_IRQHandler, LPSPI0_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(LPSPI1_IRQHandler, LPSPI1_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(LPSPI2_IRQHandler, LPSPI2_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(LPUART0_IRQHandler, LPUART0_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(LPUART1_IRQHandler, LPUART1_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(LPUART2_IRQHandler, LPUART2_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(LPI2C3_IRQHandler, LPI2C3_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(LPSPI3_IRQHandler, LPSPI3_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(LPUART3_IRQHandler, LPUART3_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(INTMUX0_0_IRQHandler, INTMUX0_0_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(INTMUX0_1_IRQHandler, INTMUX0_1_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(INTMUX0_2_IRQHandler, INTMUX0_2_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(INTMUX0_3_IRQHandler, INTMUX0_3_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(INTMUX0_4_IRQHandler, INTMUX0_4_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(INTMUX0_5_IRQHandler, INTMUX0_5_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(INTMUX0_6_IRQHandler, INTMUX0_6_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(INTMUX0_7_IRQHandler, INTMUX0_7_DriverIRQHandler);
+
+__attribute__((section("user_vectors"))) const irq_handler_t isrTable[] =
+{
+    DMA0_0_4_8_12_IRQHandler,
+    DMA0_1_5_9_13_IRQHandler,
+    DMA0_2_6_10_14_IRQHandler,
+    DMA0_3_7_11_15_IRQHandler,
+    DMA0_Error_IRQHandler,
+    CMC0_IRQHandler,
+    MUA_IRQHandler,
+    USB0_IRQHandler,
+    USDHC0_IRQHandler,
+    I2S0_IRQHandler,
+    FLEXIO0_IRQHandler,
+    EMVSIM0_IRQHandler,
+    LPIT0_IRQHandler,
+    LPSPI0_IRQHandler,
+    LPSPI1_IRQHandler,
+    LPI2C0_IRQHandler,
+    LPI2C1_IRQHandler,
+    LPUART0_IRQHandler,
+    PORTA_IRQHandler,
+    TPM0_IRQHandler,
+    LPDAC0_IRQHandler,
+    ADC0_IRQHandler,
+    LPCMP0_IRQHandler,
+    RTC_IRQHandler,
+    INTMUX0_0_IRQHandler,
+    INTMUX0_1_IRQHandler,
+    INTMUX0_2_IRQHandler,
+    INTMUX0_3_IRQHandler,
+    INTMUX0_4_IRQHandler,
+    INTMUX0_5_IRQHandler,
+    INTMUX0_6_IRQHandler,
+    INTMUX0_7_IRQHandler,
+    EWM_IRQHandler,
+    FTFE_Command_Complete_IRQHandler,
+    FTFE_Read_Collision_IRQHandler,
+    LLWU0_IRQHandler,
+    SPM_IRQHandler,
+    WDOG0_IRQHandler,
+    SCG_IRQHandler,
+    LPTMR0_IRQHandler,
+    LPTMR1_IRQHandler,
+    TPM1_IRQHandler,
+    TPM2_IRQHandler,
+    LPI2C2_IRQHandler,
+    LPSPI2_IRQHandler,
+    LPUART1_IRQHandler,
+    LPUART2_IRQHandler,
+    PORTB_IRQHandler,
+    PORTC_IRQHandler,
+    PORTD_IRQHandler,
+    CAU3_Task_Complete_IRQHandler,
+    CAU3_Security_Violation_IRQHandler,
+    TRNG_IRQHandler,
+    LPIT1_IRQHandler,
+    LPTMR2_IRQHandler,
+    TPM3_IRQHandler,
+    LPI2C3_IRQHandler,
+    LPSPI3_IRQHandler,
+    LPUART3_IRQHandler,
+    PORTE_IRQHandler,
+    LPCMP1_IRQHandler,
+    RF0_0_IRQHandler,
+    RF0_1_IRQHandler,
+};
+
+extern uint32_t __VECTOR_TABLE[];
+
+static uint32_t irqNesting = 0;
+
+static void DefaultIRQHandler(void)
+{
+    for (;;)
+    {
+    }
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemInit()
+   ---------------------------------------------------------------------------- */
+
+void SystemInit (void) {
+#if (DISABLE_WDOG)
+  WDOG0->CNT = 0xD928C520U;
+  WDOG0->TOVAL = 0xFFFF;
+  WDOG0->CS = (uint32_t) ((WDOG0->CS) & ~WDOG_CS_EN_MASK) | WDOG_CS_UPDATE_MASK;
+#endif /* (DISABLE_WDOG) */
+
+  SystemInitHook();
+
+  copy_section(&__etext, &__data_start__, &__data_end__);
+  zero_section(&__bss_start__, &__bss_end__);
+
+  /* Setup the vector table address. */
+  irqNesting = 0;
+
+  __ASM volatile("csrw 0x305, %0" :: "r"((uint32_t)__VECTOR_TABLE)); /* MTVEC */
+  __ASM volatile("csrw 0x005, %0" :: "r"((uint32_t)__VECTOR_TABLE)); /* UTVEC */
+
+  /* Clear all pending flags. */
+  EVENT_UNIT->INTPTPENDCLEAR = 0xFFFFFFFF;
+  EVENT_UNIT->EVTPENDCLEAR = 0xFFFFFFFF;
+  /* Set all interrupt as secure interrupt. */
+  EVENT_UNIT->INTPTSECURE = 0xFFFFFFFF;
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemCoreClockUpdate()
+   ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate (void) {
+
+  uint32_t SCGOUTClock;                                 /* Variable to store output clock frequency of the SCG module */
+  uint16_t Divider;
+  Divider = ((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1;
+
+  switch ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) {
+    case 0x1:
+      /* System OSC */
+      SCGOUTClock = CPU_XTAL_CLK_HZ;
+      break;
+    case 0x2:
+      /* Slow IRC */
+      SCGOUTClock = (((SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) >> SCG_SIRCCFG_RANGE_SHIFT) ? 8000000 : 2000000);
+      break;
+    case 0x3:
+      /* Fast IRC */
+      SCGOUTClock = 48000000 + ((SCG->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT) * 4000000;
+      break;
+    case 0x5:
+      /* Low Power FLL */
+      SCGOUTClock = 48000000 + ((SCG->LPFLLCFG & SCG_LPFLLCFG_FSEL_MASK) >> SCG_LPFLLCFG_FSEL_SHIFT) * 24000000;
+      break;
+    default:
+      return;
+  }
+  SystemCoreClock = (SCGOUTClock / Divider);
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemInitHook()
+   ---------------------------------------------------------------------------- */
+
+__attribute__ ((weak)) void SystemInitHook (void) {
+  /* Void implementation of the weak function. */
+}
+
+#if defined(__IAR_SYSTEMS_ICC__)
+#pragma weak SystemIrqHandler
+void SystemIrqHandler(uint32_t mcause) {
+#elif defined(__GNUC__)
+__attribute__((weak)) void SystemIrqHandler(uint32_t mcause) {
+#else
+  #error Not supported compiler type
+#endif
+    uint32_t intNum;
+
+    if (mcause & 0x80000000) /* For external interrupt. */
+    {
+        intNum = mcause & 0x1FUL;
+
+        irqNesting++;
+
+        /* Clear pending flag in EVENT unit .*/
+        EVENT_UNIT->INTPTPENDCLEAR = (1U << intNum);
+
+        /* Read back to make sure write finished. */
+        (void)(EVENT_UNIT->INTPTPENDCLEAR);
+
+        __enable_irq();      /* Support nesting interrupt */
+
+        /* Now call the real irq handler for intNum */
+        isrTable[intNum]();
+
+        __disable_irq();
+
+        irqNesting--;
+    }
+}
+
+/* Use LIPT0 channel 0 for systick. */
+#define SYSTICK_LPIT LPIT0
+#define SYSTICK_LPIT_CH 0
+#define SYSTICK_LPIT_IRQn LPIT0_IRQn
+
+/* Leverage LPIT0 to provide Systick */
+void SystemSetupSystick(uint32_t tickRateHz, uint32_t intPriority)
+{
+    /* Init pit module */
+    CLOCK_EnableClock(kCLOCK_Lpit0);
+
+    /* Reset the timer channels and registers except the MCR register */
+    SYSTICK_LPIT->MCR |= LPIT_MCR_SW_RST_MASK;
+    SYSTICK_LPIT->MCR &= ~LPIT_MCR_SW_RST_MASK;
+
+    /* Setup timer operation in debug and doze modes and enable the module */
+    SYSTICK_LPIT->MCR = LPIT_MCR_DBG_EN_MASK | LPIT_MCR_DOZE_EN_MASK | LPIT_MCR_M_CEN_MASK;
+
+    /* Set timer period for channel 0 */
+    SYSTICK_LPIT->CHANNEL[SYSTICK_LPIT_CH].TVAL = (CLOCK_GetIpFreq(kCLOCK_Lpit0) / tickRateHz) - 1;
+
+    /* Enable timer interrupts for channel 0 */
+    SYSTICK_LPIT->MIER |= (1U << SYSTICK_LPIT_CH);
+
+    /* Set interrupt priority. */
+    EVENT_SetIRQPriority(SYSTICK_LPIT_IRQn, intPriority);
+
+    /* Enable interrupt at the EVENT unit */
+    EnableIRQ(SYSTICK_LPIT_IRQn);
+
+    /* Start channel 0 */
+    SYSTICK_LPIT->SETTEN |= (LPIT_SETTEN_SET_T_EN_0_MASK << SYSTICK_LPIT_CH);
+}
+
+uint32_t SystemGetIRQNestingLevel(void)
+{
+    return irqNesting;
+}
+
+void SystemClearSystickFlag(void)
+{
+    /* Channel 0. */
+    SYSTICK_LPIT->MSR = (1U << SYSTICK_LPIT_CH);
+}
+
+void EVENT_SetIRQPriority(IRQn_Type IRQn, uint8_t intPriority)
+{
+    uint8_t regIdx;
+    uint8_t regOffset;
+
+    if ((IRQn < 32) && (intPriority < 8))
+    {
+        /*
+         * 4 priority control registers, each register controls 8 interrupts.
+         * Bit 0-2: interrupt 0
+         * Bit 4-7: interrupt 1
+         * ...
+         * Bit 28-30: interrupt 7
+         */
+        regIdx = IRQn >> 3U;
+        regOffset = (IRQn & 0x07U) * 4U;
+
+        EVENT_UNIT->INTPTPRI[regIdx] = (EVENT_UNIT->INTPTPRI[regIdx] & ~(0x0F << regOffset)) | (intPriority << regOffset);
+    }
+}
+
+uint8_t EVENT_GetIRQPriority(IRQn_Type IRQn)
+{
+    uint8_t regIdx;
+    uint8_t regOffset;
+    int32_t intPriority;
+
+    if ((IRQn < 32))
+    {
+        /*
+         * 4 priority control registers, each register controls 8 interrupts.
+         * Bit 0-2: interrupt 0
+         * Bit 4-7: interrupt 1
+         * ...
+         * Bit 28-30: interrupt 7
+         */
+        regIdx = IRQn >> 3U;
+        regOffset = (IRQn & 0x07U) << 2U;
+
+        intPriority = (EVENT_UNIT->INTPTPRI[regIdx] >> regOffset) & 0xF;
+        return (uint8_t)intPriority;
+    }
+    return 0;
+}
+
+bool SystemInISR(void)
+{
+    return ((EVENT_UNIT->INTPTENACTIVE) != 0);;
+}
+
+void EVENT_SystemReset(void)
+{
+    EVENT_UNIT->SLPCTRL |= EVENT_SLPCTRL_SYSRSTREQST_MASK;
+}

FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/system_RV32M1_ri5cy.h

@@ -0,0 +1,182 @@
+/*
+** ###################################################################
+**     Processors:          RV32M1_ri5cy
+**                          RV32M1_ri5cy
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**                          MCUXpresso Compiler
+**
+**     Reference manual:    RV32M1 Series Reference Manual, Rev. 1 , 8/10/2018
+**     Version:             rev. 1.0, 2018-10-02
+**     Build:               b180926
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2018 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2018-10-02)
+**         Initial version.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file RV32M1_ri5cy
+ * @version 1.0
+ * @date 2018-10-02
+ * @brief Device specific configuration file for RV32M1_ri5cy (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef _SYSTEM_RV32M1_ri5cy_H_
+#define _SYSTEM_RV32M1_ri5cy_H_             /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <stdbool.h>
+
+
+#ifndef DISABLE_WDOG
+  #define DISABLE_WDOG  1
+#endif
+
+/* Define clock source values */
+#define CPU_XTAL_CLK_HZ                 8000000u            /* Value of the external crystal or oscillator clock frequency in Hz */
+
+/* Low power mode enable */
+/* SMC_PMPROT: AHSRUN=1, AVLP=1,ALLS=1,AVLLS=0x3 */
+#define SYSTEM_SMC_PMPROT_VALUE        0xABu               /* SMC_PMPROT */
+#define SYSTEM_SMC_PMCTRL_VALUE        0x0u                /* SMC_PMCTRL */
+
+#define DEFAULT_SYSTEM_CLOCK           48000000u           /* Default System clock value */
+
+
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit (void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate (void);
+
+/**
+ * @brief SystemInit function hook.
+ *
+ * This weak function allows to call specific initialization code during the
+ * SystemInit() execution.This can be used when an application specific code needs
+ * to be called as close to the reset entry as possible (for example the Multicore
+ * Manager MCMGR_EarlyInit() function call).
+ * NOTE: No global r/w variables can be used in this hook function because the
+ * initialization of these variables happens after this function.
+ */
+void SystemInitHook (void);
+
+/**
+ * @brief System IRQ handler which dispatches specific IRQ to corresponding registered handler.
+ *
+ * It is called from IRQ exception context and dispatches to registered handler according to
+ * MCAUSE interrupt number.
+ *
+ * @param mcause IRQ acknowledge value read from MCAUSE
+ */
+void SystemIrqHandler(uint32_t mcause);
+
+/**
+ * @brief Get IRQ nesting level of current context.
+ *
+ * If the return value is 0, then the context is not ISR, otherwise the context is ISR.
+ *
+ * @return IRQ nesting level
+ */
+uint32_t SystemGetIRQNestingLevel (void);
+
+/**
+ * @brief Setup systick for RTOS system.
+ *
+ * @param tickRateHz Tick number per second
+ * @param intPriority IRQ interrupt priority (the smaller, the higher priority)
+ */
+void SystemSetupSystick (uint32_t tickRateHz, uint32_t intPriority);
+
+/**
+ * @brief Clear systick flag status so that next tick interrupt may occur.
+ */
+void SystemClearSystickFlag (void);
+
+/**
+ * @brief Sysem is in ISR or not.
+ */
+bool SystemInISR(void);
+
+#define SysTick_Handler LPIT0_IRQHandler
+
+/**
+ * @brief Set interrupt priority in Event unit.
+ */
+void EVENT_SetIRQPriority(IRQn_Type IRQn, uint8_t intPriority);
+
+/**
+ * @brief Get interrupt priority in Event unit.
+ */
+uint8_t EVENT_GetIRQPriority(IRQn_Type IRQn);
+
+/**
+ * @brief Reset the system.
+ */
+void EVENT_SystemReset(void);
+
+#define NVIC_SystemReset EVENT_SystemReset
+
+/* Priority setting macro remap. */
+#define NVIC_SetPriority EVENT_SetIRQPriority
+
+/* Priority getting macro remap. */
+#define NVIC_GetPriority EVENT_GetIRQPriority
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SYSTEM_RV32M1_ri5cy_H_ */

FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/system_RV32M1_zero_riscy.c

@@ -0,0 +1,535 @@
+/*
+** ###################################################################
+**     Processors:          RV32M1_zero_riscy
+**                          RV32M1_zero_riscy
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**                          MCUXpresso Compiler
+**
+**     Reference manual:    RV32M1 Series Reference Manual, Rev. 1 , 8/10/2018
+**     Version:             rev. 1.0, 2018-10-02
+**     Build:               b180926
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2018 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2018-10-02)
+**         Initial version.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file RV32M1_zero_riscy
+ * @version 1.0
+ * @date 2018-10-02
+ * @brief Device specific configuration file for RV32M1_zero_riscy
+ *        (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "fsl_device_registers.h"
+#include "fsl_common.h"
+
+typedef void (*irq_handler_t)(void);
+
+extern void CTI1_IRQHandler(void);
+extern void DMA1_04_DriverIRQHandler(void);
+extern void DMA1_15_DriverIRQHandler(void);
+extern void DMA1_26_DriverIRQHandler(void);
+extern void DMA1_37_DriverIRQHandler(void);
+extern void DMA1_Error_DriverIRQHandler(void);
+extern void CMC1_IRQHandler(void);
+extern void LLWU1_IRQHandler(void);
+extern void MUB_IRQHandler(void);
+extern void WDOG1_IRQHandler(void);
+extern void CAU3_Task_Complete_IRQHandler(void);
+extern void CAU3_Security_Violation_IRQHandler(void);
+extern void TRNG_IRQHandler(void);
+extern void LPIT1_IRQHandler(void);
+extern void LPTMR2_IRQHandler(void);
+extern void TPM3_IRQHandler(void);
+extern void LPI2C3_DriverIRQHandler(void);
+extern void RF0_0_IRQHandler(void);
+extern void RF0_1_IRQHandler(void);
+extern void LPSPI3_DriverIRQHandler(void);
+extern void LPUART3_DriverIRQHandler(void);
+extern void PORTE_IRQHandler(void);
+extern void LPCMP1_IRQHandler(void);
+extern void RTC_IRQHandler(void);
+extern void INTMUX1_0_DriverIRQHandler(void);
+extern void INTMUX1_1_DriverIRQHandler(void);
+extern void INTMUX1_2_DriverIRQHandler(void);
+extern void INTMUX1_3_DriverIRQHandler(void);
+extern void INTMUX1_4_DriverIRQHandler(void);
+extern void INTMUX1_5_DriverIRQHandler(void);
+extern void INTMUX1_6_DriverIRQHandler(void);
+extern void INTMUX1_7_DriverIRQHandler(void);
+extern void EWM_IRQHandler(void);
+extern void FTFE_Command_Complete_IRQHandler(void);
+extern void FTFE_Read_Collision_IRQHandler(void);
+extern void SPM_IRQHandler(void);
+extern void SCG_IRQHandler(void);
+extern void LPIT0_IRQHandler(void);
+extern void LPTMR0_IRQHandler(void);
+extern void LPTMR1_IRQHandler(void);
+extern void TPM0_IRQHandler(void);
+extern void TPM1_IRQHandler(void);
+extern void TPM2_IRQHandler(void);
+extern void EMVSIM0_IRQHandler(void);
+extern void FLEXIO0_DriverIRQHandler(void);
+extern void LPI2C0_DriverIRQHandler(void);
+extern void LPI2C1_DriverIRQHandler(void);
+extern void LPI2C2_DriverIRQHandler(void);
+extern void I2S0_DriverIRQHandler(void);
+extern void USDHC0_DriverIRQHandler(void);
+extern void LPSPI0_DriverIRQHandler(void);
+extern void LPSPI1_DriverIRQHandler(void);
+extern void LPSPI2_DriverIRQHandler(void);
+extern void LPUART0_DriverIRQHandler(void);
+extern void LPUART1_DriverIRQHandler(void);
+extern void LPUART2_DriverIRQHandler(void);
+extern void USB0_IRQHandler(void);
+extern void PORTA_IRQHandler(void);
+extern void PORTB_IRQHandler(void);
+extern void PORTC_IRQHandler(void);
+extern void PORTD_IRQHandler(void);
+extern void ADC0_IRQHandler(void);
+extern void LPCMP0_IRQHandler(void);
+extern void LPDAC0_IRQHandler(void);
+extern void DMA1_15_IRQHandler(void);
+extern void DMA1_26_IRQHandler(void);
+extern void DMA1_37_IRQHandler(void);
+extern void DMA1_Error_IRQHandler(void);
+extern void LPI2C3_IRQHandler(void);
+extern void LPSPI3_IRQHandler(void);
+extern void LPUART3_IRQHandler(void);
+extern void INTMUX1_0_IRQHandler(void);
+extern void INTMUX1_1_IRQHandler(void);
+extern void INTMUX1_2_IRQHandler(void);
+extern void INTMUX1_3_IRQHandler(void);
+extern void INTMUX1_4_IRQHandler(void);
+extern void INTMUX1_5_IRQHandler(void);
+extern void INTMUX1_6_IRQHandler(void);
+extern void INTMUX1_7_IRQHandler(void);
+extern void FLEXIO0_IRQHandler(void);
+extern void LPI2C0_IRQHandler(void);
+extern void LPI2C1_IRQHandler(void);
+extern void LPI2C2_IRQHandler(void);
+extern void I2S0_IRQHandler(void);
+extern void USDHC0_IRQHandler(void);
+extern void LPSPI0_IRQHandler(void);
+extern void LPSPI1_IRQHandler(void);
+extern void LPSPI2_IRQHandler(void);
+extern void LPUART0_IRQHandler(void);
+extern void LPUART1_IRQHandler(void);
+extern void LPUART2_IRQHandler(void);
+
+/* ----------------------------------------------------------------------------
+   -- Core clock
+   ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+extern uint32_t __etext;
+extern uint32_t __data_start__;
+extern uint32_t __data_end__;
+
+extern uint32_t __bss_start__;
+extern uint32_t __bss_end__;
+
+static void copy_section(uint32_t * p_load, uint32_t * p_vma, uint32_t * p_vma_end)
+{
+    while(p_vma <= p_vma_end)
+    {
+        *p_vma = *p_load;
+        ++p_load;
+        ++p_vma;
+    }
+}
+
+static void zero_section(uint32_t * start, uint32_t * end)
+{
+    uint32_t * p_zero = start;
+
+    while(p_zero <= end)
+    {
+        *p_zero = 0;
+        ++p_zero;
+    }
+}
+
+#define DEFINE_IRQ_HANDLER(irq_handler, driver_irq_handler) \
+    void __attribute__((weak)) irq_handler(void) { driver_irq_handler();}
+
+#define DEFINE_DEFAULT_IRQ_HANDLER(irq_handler) void irq_handler() __attribute__((weak, alias("DefaultIRQHandler")))
+
+DEFINE_DEFAULT_IRQ_HANDLER(CTI1_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(DMA1_04_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(DMA1_15_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(DMA1_26_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(DMA1_37_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(DMA1_Error_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(CMC1_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LLWU1_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(MUB_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(WDOG1_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(CAU3_Task_Complete_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(CAU3_Security_Violation_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(TRNG_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPIT1_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPTMR2_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(TPM3_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPI2C3_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(RF0_0_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(RF0_1_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPSPI3_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPUART3_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(PORTE_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPCMP1_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(RTC_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(INTMUX1_0_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(INTMUX1_1_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(INTMUX1_2_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(INTMUX1_3_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(INTMUX1_4_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(INTMUX1_5_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(INTMUX1_6_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(INTMUX1_7_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(EWM_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(FTFE_Command_Complete_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(FTFE_Read_Collision_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(SPM_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(SCG_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPIT0_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPTMR0_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPTMR1_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(TPM0_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(TPM1_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(TPM2_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(EMVSIM0_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(FLEXIO0_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPI2C0_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPI2C1_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPI2C2_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(I2S0_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(USDHC0_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPSPI0_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPSPI1_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPSPI2_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPUART0_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPUART1_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPUART2_DriverIRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(USB0_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(PORTA_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(PORTB_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(PORTC_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(PORTD_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(ADC0_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPCMP0_IRQHandler);
+DEFINE_DEFAULT_IRQ_HANDLER(LPDAC0_IRQHandler);
+
+DEFINE_IRQ_HANDLER(DMA1_04_IRQHandler, DMA1_04_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(DMA1_15_IRQHandler, DMA1_15_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(DMA1_26_IRQHandler, DMA1_26_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(DMA1_37_IRQHandler, DMA1_37_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(DMA1_Error_IRQHandler, DMA1_Error_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(LPI2C3_IRQHandler, LPI2C3_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(LPSPI3_IRQHandler, LPSPI3_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(LPUART3_IRQHandler, LPUART3_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(INTMUX1_0_IRQHandler, INTMUX1_0_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(INTMUX1_1_IRQHandler, INTMUX1_1_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(INTMUX1_2_IRQHandler, INTMUX1_2_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(INTMUX1_3_IRQHandler, INTMUX1_3_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(INTMUX1_4_IRQHandler, INTMUX1_4_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(INTMUX1_5_IRQHandler, INTMUX1_5_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(INTMUX1_6_IRQHandler, INTMUX1_6_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(INTMUX1_7_IRQHandler, INTMUX1_7_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(FLEXIO0_IRQHandler, FLEXIO0_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(LPI2C0_IRQHandler, LPI2C0_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(LPI2C1_IRQHandler, LPI2C1_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(LPI2C2_IRQHandler, LPI2C2_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(I2S0_IRQHandler, I2S0_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(USDHC0_IRQHandler, USDHC0_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(LPSPI0_IRQHandler, LPSPI0_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(LPSPI1_IRQHandler, LPSPI1_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(LPSPI2_IRQHandler, LPSPI2_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(LPUART0_IRQHandler, LPUART0_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(LPUART1_IRQHandler, LPUART1_DriverIRQHandler);
+DEFINE_IRQ_HANDLER(LPUART2_IRQHandler, LPUART2_DriverIRQHandler);
+
+__attribute__((section("user_vectors"))) const irq_handler_t isrTable[] =
+{
+	CTI1_IRQHandler,
+	DMA1_04_IRQHandler,
+	DMA1_15_IRQHandler,
+	DMA1_26_IRQHandler,
+	DMA1_37_IRQHandler,
+	DMA1_Error_IRQHandler,
+	CMC1_IRQHandler,
+	LLWU1_IRQHandler,
+	MUB_IRQHandler,
+	WDOG1_IRQHandler,
+	CAU3_Task_Complete_IRQHandler,
+	CAU3_Security_Violation_IRQHandler,
+	TRNG_IRQHandler,
+	LPIT1_IRQHandler,
+	LPTMR2_IRQHandler,
+	TPM3_IRQHandler,
+	LPI2C3_IRQHandler,
+	RF0_0_IRQHandler,
+	RF0_1_IRQHandler,
+	LPSPI3_IRQHandler,
+	LPUART3_IRQHandler,
+	PORTE_IRQHandler,
+	LPCMP1_IRQHandler,
+	RTC_IRQHandler,
+	INTMUX1_0_IRQHandler,
+	INTMUX1_1_IRQHandler,
+	INTMUX1_2_IRQHandler,
+	INTMUX1_3_IRQHandler,
+	INTMUX1_4_IRQHandler,
+	INTMUX1_5_IRQHandler,
+	INTMUX1_6_IRQHandler,
+	INTMUX1_7_IRQHandler,
+	EWM_IRQHandler,
+	FTFE_Command_Complete_IRQHandler,
+	FTFE_Read_Collision_IRQHandler,
+	SPM_IRQHandler,
+	SCG_IRQHandler,
+	LPIT0_IRQHandler,
+	LPTMR0_IRQHandler,
+	LPTMR1_IRQHandler,
+	TPM0_IRQHandler,
+	TPM1_IRQHandler,
+	TPM2_IRQHandler,
+	EMVSIM0_IRQHandler,
+	FLEXIO0_IRQHandler,
+	LPI2C0_IRQHandler,
+	LPI2C1_IRQHandler,
+	LPI2C2_IRQHandler,
+	I2S0_IRQHandler,
+	USDHC0_IRQHandler,
+	LPSPI0_IRQHandler,
+	LPSPI1_IRQHandler,
+	LPSPI2_IRQHandler,
+	LPUART0_IRQHandler,
+	LPUART1_IRQHandler,
+	LPUART2_IRQHandler,
+	USB0_IRQHandler,
+	PORTA_IRQHandler,
+	PORTB_IRQHandler,
+	PORTC_IRQHandler,
+	PORTD_IRQHandler,
+	ADC0_IRQHandler,
+	LPCMP0_IRQHandler,
+	LPDAC0_IRQHandler,
+};
+
+extern uint32_t __VECTOR_TABLE[];
+
+static uint32_t irqNesting = 0;
+
+static void DefaultIRQHandler(void)
+{
+    for (;;)
+    {
+    }
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemInit()
+   ---------------------------------------------------------------------------- */
+
+void SystemInit (void) {
+#if (DISABLE_WDOG)
+  WDOG1->CNT = 0xD928C520U;
+  WDOG1->TOVAL = 0xFFFF;
+  WDOG1->CS = (uint32_t) ((WDOG1->CS) & ~WDOG_CS_EN_MASK) | WDOG_CS_UPDATE_MASK;
+#endif /* (DISABLE_WDOG) */
+
+  SystemInitHook();
+
+  copy_section(&__etext, &__data_start__, &__data_end__);
+  zero_section(&__bss_start__, &__bss_end__);
+
+  /* Setup the vector table address. */
+  irqNesting = 0;
+
+  __ASM volatile("csrw 0x305, %0" :: "r"((uint32_t)__VECTOR_TABLE)); /* MTVEC */
+  __ASM volatile("csrw 0x005, %0" :: "r"((uint32_t)__VECTOR_TABLE)); /* UTVEC */
+
+  /* Clear all pending flags. */
+  EVENT_UNIT->INTPTPENDCLEAR = 0xFFFFFFFF;
+  EVENT_UNIT->EVTPENDCLEAR = 0xFFFFFFFF;
+  /* Set all interrupt as secure interrupt. */
+  EVENT_UNIT->INTPTSECURE = 0xFFFFFFFF;
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemCoreClockUpdate()
+   ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate (void) {
+
+  uint32_t SCGOUTClock;                                 /* Variable to store output clock frequency of the SCG module */
+  uint16_t Divider;
+  Divider = ((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1;
+
+  switch ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) {
+    case 0x1:
+      /* System OSC */
+      SCGOUTClock = CPU_XTAL_CLK_HZ;
+      break;
+    case 0x2:
+      /* Slow IRC */
+      SCGOUTClock = (((SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) >> SCG_SIRCCFG_RANGE_SHIFT) ? 8000000 : 2000000);
+      break;
+    case 0x3:
+      /* Fast IRC */
+      SCGOUTClock = 48000000 + ((SCG->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT) * 4000000;
+      break;
+    case 0x5:
+      /* Low Power FLL */
+      SCGOUTClock = 48000000 + ((SCG->LPFLLCFG & SCG_LPFLLCFG_FSEL_MASK) >> SCG_LPFLLCFG_FSEL_SHIFT) * 24000000;
+      break;
+    default:
+      return;
+  }
+  SystemCoreClock = (SCGOUTClock / Divider);
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemInitHook()
+   ---------------------------------------------------------------------------- */
+
+__attribute__ ((weak)) void SystemInitHook (void) {
+  /* Void implementation of the weak function. */
+}
+
+#if defined(__IAR_SYSTEMS_ICC__)
+#pragma weak SystemIrqHandler
+void SystemIrqHandler(uint32_t mcause) {
+#elif defined(__GNUC__)
+__attribute__((weak)) void SystemIrqHandler(uint32_t mcause) {
+#else
+  #error Not supported compiler type
+#endif
+    uint32_t intNum;
+
+    if (mcause & 0x80000000) /* For external interrupt. */
+    {
+        intNum = mcause & 0x1FUL;
+
+        irqNesting++;
+
+        /* Clear pending flag in EVENT unit .*/
+        EVENT_UNIT->INTPTPENDCLEAR = (1U << intNum);
+
+        /* Read back to make sure write finished. */
+        (void)(EVENT_UNIT->INTPTPENDCLEAR);
+
+        __enable_irq();      /* Support nesting interrupt */
+
+        /* Now call the real irq handler for intNum */
+        isrTable[intNum]();
+
+        __disable_irq();
+
+        irqNesting--;
+    }
+}
+
+/* Use LIPT1 channel 0 for systick. */
+#define SYSTICK_LPIT LPIT1
+#define SYSTICK_LPIT_CH 0
+#define SYSTICK_LPIT_IRQn LPIT1_IRQn
+
+/* Leverage LPIT0 to provide Systick */
+void SystemSetupSystick(uint32_t tickRateHz, uint32_t intPriority)
+{
+    /* Init pit module */
+    CLOCK_EnableClock(kCLOCK_Lpit1);
+
+    /* Reset the timer channels and registers except the MCR register */
+    SYSTICK_LPIT->MCR |= LPIT_MCR_SW_RST_MASK;
+    SYSTICK_LPIT->MCR &= ~LPIT_MCR_SW_RST_MASK;
+
+    /* Setup timer operation in debug and doze modes and enable the module */
+    SYSTICK_LPIT->MCR = LPIT_MCR_DBG_EN_MASK | LPIT_MCR_DOZE_EN_MASK | LPIT_MCR_M_CEN_MASK;
+
+    /* Set timer period for channel 0 */
+    SYSTICK_LPIT->CHANNEL[SYSTICK_LPIT_CH].TVAL = (CLOCK_GetIpFreq(kCLOCK_Lpit1) / tickRateHz) - 1;
+
+    /* Enable timer interrupts for channel 0 */
+    SYSTICK_LPIT->MIER |= (1U << SYSTICK_LPIT_CH);
+
+    /* Set interrupt priority. */
+    EVENT_SetIRQPriority(SYSTICK_LPIT_IRQn, intPriority);
+
+    /* Enable interrupt at the EVENT unit */
+    EnableIRQ(SYSTICK_LPIT_IRQn);
+
+    /* Start channel 0 */
+    SYSTICK_LPIT->SETTEN |= (LPIT_SETTEN_SET_T_EN_0_MASK << SYSTICK_LPIT_CH);
+}
+
+uint32_t SystemGetIRQNestingLevel(void)
+{
+    return irqNesting;
+}
+
+void SystemClearSystickFlag(void)
+{
+    /* Channel 0. */
+    SYSTICK_LPIT->MSR = (1U << SYSTICK_LPIT_CH);
+}
+
+void EVENT_SetIRQPriority(IRQn_Type IRQn, uint8_t intPriority)
+{
+    uint8_t regIdx;
+    uint8_t regOffset;
+
+    if ((IRQn < 32) && (intPriority < 8))
+    {
+        /*
+         * 4 priority control registers, each register controls 8 interrupts.
+         * Bit 0-2: interrupt 0
+         * Bit 4-7: interrupt 1
+         * ...
+         * Bit 28-30: interrupt 7
+         */
+        regIdx = IRQn >> 3U;
+        regOffset = (IRQn & 0x07U) * 4U;
+
+        EVENT_UNIT->INTPTPRI[regIdx] = (EVENT_UNIT->INTPTPRI[regIdx] & ~(0x0F << regOffset)) | (intPriority << regOffset);
+    }
+}
+
+bool SystemInISR(void)
+{
+    return ((EVENT_UNIT->INTPTENACTIVE) != 0);;
+}
+
+void EVENT_SystemReset(void)
+{
+    EVENT_UNIT->SLPCTRL |= EVENT_SLPCTRL_SYSRSTREQST_MASK;
+}

FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/system_RV32M1_zero_riscy.h

@@ -0,0 +1,174 @@
+/*
+** ###################################################################
+**     Processors:          RV32M1_zero_riscy
+**                          RV32M1_zero_riscy
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**                          MCUXpresso Compiler
+**
+**     Reference manual:    RV32M1 Series Reference Manual, Rev. 1 , 8/10/2018
+**     Version:             rev. 1.0, 2018-10-02
+**     Build:               b180926
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2018 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2018-10-02)
+**         Initial version.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file RV32M1_zero_riscy
+ * @version 1.0
+ * @date 2018-10-02
+ * @brief Device specific configuration file for RV32M1_zero_riscy (header
+ *        file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef _SYSTEM_RV32M1_zero_riscy_H_
+#define _SYSTEM_RV32M1_zero_riscy_H_        /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <stdbool.h>
+
+
+#ifndef DISABLE_WDOG
+  #define DISABLE_WDOG  1
+#endif
+
+/* Define clock source values */
+#define CPU_XTAL_CLK_HZ                 8000000u            /* Value of the external crystal or oscillator clock frequency in Hz */
+
+/* Low power mode enable */
+/* SMC_PMPROT: AHSRUN=1, AVLP=1,ALLS=1,AVLLS=0x3 */
+#define SYSTEM_SMC_PMPROT_VALUE        0xABu               /* SMC_PMPROT */
+#define SYSTEM_SMC_PMCTRL_VALUE        0x0u                /* SMC_PMCTRL */
+
+#define DEFAULT_SYSTEM_CLOCK           48000000u           /* Default System clock value */
+
+
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit (void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate (void);
+
+/**
+ * @brief SystemInit function hook.
+ *
+ * This weak function allows to call specific initialization code during the
+ * SystemInit() execution.This can be used when an application specific code needs
+ * to be called as close to the reset entry as possible (for example the Multicore
+ * Manager MCMGR_EarlyInit() function call).
+ * NOTE: No global r/w variables can be used in this hook function because the
+ * initialization of these variables happens after this function.
+ */
+void SystemInitHook (void);
+
+/**
+ * @brief System IRQ handler which dispatches specific IRQ to corresponding registered handler.
+ *
+ * It is called from IRQ exception context and dispatches to registered handler according to
+ * MCAUSE interrupt number.
+ *
+ * @param mcause IRQ acknowledge value read from MCAUSE
+ */
+void SystemIrqHandler(uint32_t mcause);
+
+/**
+ * @brief Get IRQ nesting level of current context.
+ *
+ * If the return value is 0, then the context is not ISR, otherwise the context is ISR.
+ *
+ * @return IRQ nesting level
+ */
+uint32_t SystemGetIRQNestingLevel (void);
+
+/**
+ * @brief Setup systick for RTOS system.
+ *
+ * @param tickRateHz Tick number per second
+ * @param intPriority IRQ interrupt priority (the smaller, the higher priority)
+ */
+void SystemSetupSystick (uint32_t tickRateHz, uint32_t intPriority);
+
+/**
+ * @brief Clear systick flag status so that next tick interrupt may occur.
+ */
+void SystemClearSystickFlag (void);
+
+#define SysTick_Handler LPIT1_IRQHandler
+
+/**
+ * @brief Sysem is in ISR or not.
+ */
+bool SystemInISR(void);
+
+/**
+ * @brief Set interrupt priority in Event unit.
+ */
+void EVENT_SetIRQPriority(IRQn_Type IRQn, uint8_t intPriority);
+
+/* Priority setting macro remap. */
+#define NVIC_SetPriority EVENT_SetIRQPriority
+
+/**
+ * @brief Reset the system.
+ */
+void EVENT_SystemReset(void);
+
+#define NVIC_SystemReset EVENT_SystemReset
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SYSTEM_RV32M1_zero_riscy_H_ */

FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_debug_console.c

@@ -0,0 +1,386 @@
+/*
+ * This is a modified version of the file printf.c, which was distributed
+ * by Motorola as part of the M5407C3BOOT.zip package used to initialize
+ * the M5407C3 evaluation board.
+ *
+ * Copyright:
+ *      1999-2000 MOTOROLA, INC. All Rights Reserved.
+ *  You are hereby granted a copyright license to use, modify, and
+ *  distribute the SOFTWARE so long as this entire notice is
+ *  retained without alteration in any modified and/or redistributed
+ *  versions, and that such modified versions are clearly identified
+ *  as such. No licenses are granted by implication, estoppel or
+ *  otherwise under any patents or trademarks of Motorola, Inc. This
+ *  software is provided on an "AS IS" basis and without warranty.
+ *
+ *  To the maximum extent permitted by applicable law, MOTOROLA
+ *  DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR
+ *  PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE
+ *  SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY
+ *  ACCOMPANYING WRITTEN MATERIALS.
+ *
+ *  To the maximum extent permitted by applicable law, IN NO EVENT
+ *  SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING
+ *  WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS
+ *  INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY
+ *  LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
+ *
+ *  Motorola assumes no responsibility for the maintenance and support
+ *  of this software
+
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdarg.h>
+#include <stdlib.h>
+#if defined(__CC_ARM)
+#include <stdio.h>
+#endif
+
+#include "fsl_debug_console.h"
+#include "fsl_debug_console_conf.h"
+#include "fsl_log.h"
+#include "fsl_str.h"
+
+#if defined(__riscv)
+#include <sys/stat.h>
+#include <sys/types.h>
+#endif
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief This is a printf call back function which is used to relocate the log to buffer
+ * or print the log immediately when the local buffer is full.
+ *
+ * @param[in] buf   Buffer to store log.
+ * @param[in] indicator Buffer index.
+ * @param[in] val Target character to store.
+ * @param[in] len length of the character
+ *
+ */
+#if SDK_DEBUGCONSOLE
+static void DbgConsole_RelocateLog(char *buf, int32_t *indicator, char val, int len);
+#endif
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*************Code for DbgConsole Init, Deinit, Printf, Scanf *******************************/
+
+/* See fsl_debug_console.h for documentation of this function. */
+status_t DbgConsole_Init(uint32_t baseAddr, uint32_t baudRate, uint8_t device, uint32_t clkSrcFreq)
+{
+    assert(device != DEBUG_CONSOLE_DEVICE_TYPE_NONE);
+
+    return LOG_Init(baseAddr, device, baudRate, clkSrcFreq);
+}
+
+/* See fsl_debug_console.h for documentation of this function. */
+status_t DbgConsole_Deinit(void)
+{
+    /* LOG deinit */
+    LOG_Deinit();
+
+    return kStatus_Success;
+}
+
+status_t DbgConsole_Flush(void)
+{
+    /* wait log and io idle */
+    return LOG_WaitIdle();
+}
+
+#if SDK_DEBUGCONSOLE
+/* See fsl_debug_console.h for documentation of this function. */
+int DbgConsole_Printf(const char *fmt_s, ...)
+{
+    va_list ap;
+    int logLength = 0U, result = 0U;
+    char printBuf[DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN] = {0U};
+
+    va_start(ap, fmt_s);
+    /* format print log first */
+    logLength = StrFormatPrintf(fmt_s, ap, printBuf, DbgConsole_RelocateLog);
+    /* print log */
+    result = LOG_Push((uint8_t *)printBuf, logLength);
+
+    va_end(ap);
+
+    return result;
+}
+
+/* See fsl_debug_console.h for documentation of this function. */
+int DbgConsole_Putchar(int ch)
+{
+    /* print char */
+    return LOG_Push((uint8_t *)&ch, 1U);
+}
+
+/* See fsl_debug_console.h for documentation of this function. */
+int DbgConsole_Scanf(char *fmt_ptr, ...)
+{
+    va_list ap;
+    int result;
+    char scanfBuf[DEBUG_CONSOLE_SCANF_MAX_LOG_LEN + 1U] = {0U};
+
+    /* scanf log */
+    LOG_ReadLine((uint8_t *)scanfBuf, DEBUG_CONSOLE_SCANF_MAX_LOG_LEN);
+    /* get va_list */
+    va_start(ap, fmt_ptr);
+    /* format scanf log */
+    result = StrFormatScanf(scanfBuf, fmt_ptr, ap);
+
+    va_end(ap);
+
+    return result;
+}
+
+/* See fsl_debug_console.h for documentation of this function. */
+int DbgConsole_Getchar(void)
+{
+    uint8_t ch;
+
+    /* Get char */
+    LOG_ReadCharacter(&ch);
+
+    return ch;
+}
+
+static void DbgConsole_RelocateLog(char *buf, int32_t *indicator, char val, int len)
+{
+    int i = 0;
+
+    for (i = 0; i < len; i++)
+    {
+        if ((*indicator + 1) >= DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN)
+        {
+            LOG_Push((uint8_t *)buf, *indicator);
+            *indicator = 0U;
+        }
+
+        buf[*indicator] = val;
+        (*indicator)++;
+    }
+}
+
+#endif /* SDK_DEBUGCONSOLE */
+/*************Code to support toolchain's printf, scanf *******************************/
+/* These function __write and __read is used to support IAR toolchain to printf and scanf*/
+#if (defined(__ICCARM__))
+#pragma weak __write
+size_t __write(int handle, const unsigned char *buffer, size_t size)
+{
+    if (buffer == 0)
+    {
+        /*
+         * This means that we should flush internal buffers.  Since we don't we just return.
+         * (Remember, "handle" == -1 means that all handles should be flushed.)
+         */
+        return 0;
+    }
+
+    /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */
+    if ((handle != 1) && (handle != 2))
+    {
+        return ((size_t)-1);
+    }
+
+    /* Send data. */
+    LOG_Push((uint8_t *)buffer, 1U);
+
+    return size;
+}
+
+#pragma weak __read
+size_t __read(int handle, unsigned char *buffer, size_t size)
+{
+    /* This function only reads from "standard in", for all other file  handles it returns failure. */
+    if (handle != 0)
+    {
+        return ((size_t)-1);
+    }
+
+    /* Receive data.*/
+    LOG_ReadLine(buffer, size);
+
+    return size;
+}
+
+/* support LPC Xpresso with RedLib */
+#elif(defined(__REDLIB__))
+
+#if (!SDK_DEBUGCONSOLE) && (defined(SDK_DEBUGCONSOLE_UART))
+int __attribute__((weak)) __sys_write(int handle, char *buffer, int size)
+{
+    if (buffer == 0)
+    {
+        /* return -1 if error. */
+        return -1;
+    }
+
+    /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */
+    if ((handle != 1) && (handle != 2))
+    {
+        return -1;
+    }
+
+    /* Send data. */
+    LOG_Push((uint8_t *)buffer, size);
+
+    return 0;
+}
+
+int __attribute__((weak)) __sys_readc(void)
+{
+    char tmp;
+
+    /* Receive data. */
+    LOG_ReadCharacter((uint8_t *)&tmp);
+
+    return tmp;
+}
+#endif
+
+/* These function __write and __read is used to support ARM_GCC, KDS, Atollic toolchains to printf and scanf*/
+#elif(defined(__GNUC__))
+
+#if ((defined(__GNUC__) && (!defined(__MCUXPRESSO))) || \
+     (defined(__MCUXPRESSO) && (!SDK_DEBUGCONSOLE) && (defined(SDK_DEBUGCONSOLE_UART))))
+
+int __attribute__((weak)) _write(int handle, char *buffer, int size)
+{
+    if (buffer == 0)
+    {
+        /* return -1 if error. */
+        return -1;
+    }
+
+    /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */
+    if ((handle != 1) && (handle != 2))
+    {
+        return -1;
+    }
+
+    /* Send data. */
+    LOG_Push((uint8_t *)buffer, size);
+
+    return size;
+}
+
+int __attribute__((weak)) _read(int handle, char *buffer, int size)
+{
+    /* This function only reads from "standard in", for all other file handles it returns failure. */
+    if (handle != 0)
+    {
+        return -1;
+    }
+
+    /* Receive data. */
+    return LOG_ReadLine((uint8_t *)buffer, size);
+}
+#endif
+
+/* These function fputc and fgetc is used to support KEIL toolchain to printf and scanf*/
+#elif defined(__CC_ARM)
+struct __FILE
+{
+    int handle;
+    /*
+     * Whatever you require here. If the only file you are using is standard output using printf() for debugging,
+     * no file handling is required.
+     */
+};
+
+/* FILE is typedef in stdio.h. */
+#pragma weak __stdout
+#pragma weak __stdin
+FILE __stdout;
+FILE __stdin;
+
+#pragma weak fputc
+int fputc(int ch, FILE *f)
+{
+    /* Send data. */
+    return LOG_Push((uint8_t *)(&ch), 1);
+}
+
+#pragma weak fgetc
+int fgetc(FILE *f)
+{
+    char ch;
+
+    /* Receive data. */
+    LOG_ReadCharacter((uint8_t *)&ch);
+
+    return ch;
+}
+#endif /* __ICCARM__ */
+
+#if defined(__riscv)
+int isatty(int fd)
+{
+    return 1;
+}
+
+int fstat(int fd, struct stat *st)
+{
+    st->st_mode = S_IFCHR;
+    return 0;
+}
+
+int lseek(int fd, off_t ptr, int dir)
+{
+    return 0;
+}
+
+int close(int fd)
+{
+    return -1;
+}
+
+int read(int fd, void* ptr, size_t len)
+{
+    /* This function only reads from "standard in", for all other file handles it returns failure. */
+    if (fd != 0)
+    {
+        return -1;
+    }
+
+    /* Receive data. */
+    return LOG_ReadLine((uint8_t *)ptr, len);
+}
+
+int write(int fd, const void* ptr, size_t len)
+{
+    if (ptr == 0)
+    {
+        /* return -1 if error. */
+        return -1;
+    }
+
+    /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */
+    if ((fd != 1) && (fd != 2))
+    {
+        return -1;
+    }
+
+    /* Send data. */
+    LOG_Push((uint8_t *)ptr, len);
+
+    return len;
+}
+#endif

FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_debug_console.h

@@ -0,0 +1,162 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ * 
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Debug console shall provide input and output functions to scan and print formatted data.
+ * o Support a format specifier for PRINTF follows this prototype "%[flags][width][.precision][length]specifier"
+ *   - [flags] :'-', '+', '#', ' ', '0'
+ *   - [width]:  number (0,1...)
+ *   - [.precision]: number (0,1...)
+ *   - [length]: do not support
+ *   - [specifier]: 'd', 'i', 'f', 'F', 'x', 'X', 'o', 'p', 'u', 'c', 's', 'n'
+ * o Support a format specifier for SCANF follows this prototype " %[*][width][length]specifier"
+ *   - [*]: is supported.
+ *   - [width]: number (0,1...)
+ *   - [length]: 'h', 'hh', 'l','ll','L'. ignore ('j','z','t')
+ *   - [specifier]: 'd', 'i', 'u', 'f', 'F', 'e', 'E', 'g', 'G', 'a', 'A', 'o', 'c', 's'
+ */
+
+#ifndef _FSL_DEBUGCONSOLE_H_
+#define _FSL_DEBUGCONSOLE_H_
+
+#include "fsl_common.h"
+/*
+ * @addtogroup debugconsole
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Definition to select sdk or toolchain printf, scanf. */
+#ifndef SDK_DEBUGCONSOLE
+#define SDK_DEBUGCONSOLE 1U
+#endif
+
+#if defined(SDK_DEBUGCONSOLE) && !(SDK_DEBUGCONSOLE)
+#include <stdio.h>
+#endif
+
+#if SDK_DEBUGCONSOLE /* Select printf, scanf, putchar, getchar of SDK version. */
+#define PRINTF DbgConsole_Printf
+#define SCANF DbgConsole_Scanf
+#define PUTCHAR DbgConsole_Putchar
+#define GETCHAR DbgConsole_Getchar
+#else /* Select printf, scanf, putchar, getchar of toolchain. */
+#define PRINTF printf
+#define SCANF scanf
+#define PUTCHAR putchar
+#define GETCHAR getchar
+#endif /* SDK_DEBUGCONSOLE */
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*! @name Initialization*/
+/* @{ */
+
+/*!
+ * @brief Initializes the the peripheral used for debug messages.
+ *
+ * Call this function to enable debug log messages to be output via the specified peripheral,
+ * frequency of peripheral source clock, and base address at the specified baud rate.
+ * After this function has returned, stdout and stdin are connected to the selected peripheral.
+ *
+ * @param baseAddr      Indicates the address of the peripheral used to send debug messages.
+ * @param baudRate      The desired baud rate in bits per second.
+ * @param device        Low level device type for the debug console, can be one of the following.
+ *                      @arg DEBUG_CONSOLE_DEVICE_TYPE_UART,
+ *                      @arg DEBUG_CONSOLE_DEVICE_TYPE_LPUART,
+ *                      @arg DEBUG_CONSOLE_DEVICE_TYPE_LPSCI,
+ *                      @arg DEBUG_CONSOLE_DEVICE_TYPE_USBCDC.
+ * @param clkSrcFreq    Frequency of peripheral source clock.
+ *
+ * @return              Indicates whether initialization was successful or not.
+ * @retval kStatus_Success          Execution successfully
+ * @retval kStatus_Fail             Execution failure
+ * @retval kStatus_InvalidArgument  Invalid argument existed
+ */
+status_t DbgConsole_Init(uint32_t baseAddr, uint32_t baudRate, uint8_t device, uint32_t clkSrcFreq);
+
+/*!
+ * @brief De-initializes the peripheral used for debug messages.
+ *
+ * Call this function to disable debug log messages to be output via the specified peripheral
+ * base address and at the specified baud rate.
+ *
+ * @return Indicates whether de-initialization was successful or not.
+ */
+status_t DbgConsole_Deinit(void);
+
+/*!
+ * @brief Debug console flush log.
+ *
+ * Call this function to wait the buffer empty and io idle before.
+ * If interrupt transfer is using, make sure the global IRQ is enable before call this function
+ * This function should be called when
+ * 1, before enter power down mode
+ * 2, log is required to print to terminal immediately
+ * @return Indicates whether wait idle was successful or not.
+ */
+status_t DbgConsole_Flush(void);
+
+#if SDK_DEBUGCONSOLE
+/*!
+ * @brief Writes formatted output to the standard output stream.
+ *
+ * Call this function to write a formatted output to the standard output stream.
+ *
+ * @param   fmt_s Format control string.
+ * @return  Returns the number of characters printed or a negative value if an error occurs.
+ */
+int DbgConsole_Printf(const char *fmt_s, ...);
+
+/*!
+ * @brief Writes a character to stdout.
+ *
+ * Call this function to write a character to stdout.
+ *
+ * @param   ch Character to be written.
+ * @return  Returns the character written.
+ */
+int DbgConsole_Putchar(int ch);
+
+/*!
+ * @brief Reads formatted data from the standard input stream.
+ *
+ * Call this function to read formatted data from the standard input stream.
+ *
+ * @param   fmt_ptr Format control string.
+ * @return  Returns the number of fields successfully converted and assigned.
+ */
+int DbgConsole_Scanf(char *fmt_ptr, ...);
+
+/*!
+ * @brief Reads a character from standard input.
+ *
+ * Call this function to read a character from standard input.
+ *
+ * @return Returns the character read.
+ */
+int DbgConsole_Getchar(void);
+
+#endif /* SDK_DEBUGCONSOLE */
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @} */
+
+#endif /* _FSL_DEBUGCONSOLE_H_ */

FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_debug_console_conf.h

@@ -0,0 +1,128 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ * 
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_DEBUG_CONSOLE_CONF_H_
+#define _FSL_DEBUG_CONSOLE_CONF_H_
+
+/****************Debug console configuration********************/
+
+/*! @brief If Non-blocking mode is needed, please define it at project setting,
+* otherwise blocking mode is the default transfer mode.
+* Warning: If you want to use non-blocking transfer,please make sure the corresponding
+* IO interrupt is enable, otherwise there is no output.
+* And non-blocking is combine with buffer, no matter bare-metal or rtos.
+*/
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+/*! @brief define the transmit buffer length which is used to store the multi task log, buffer is enabled automatically
+* when
+* non-blocking transfer is using,
+* This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement.
+* If it is configured too small, log maybe missed , because the log will not be
+* buffered if the buffer is full, and the print will return immediately with -1.
+* And this value should be multiple of 4 to meet memory alignment.
+*
+*/
+#ifndef DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN
+#define DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN (512U)
+#endif /* DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN */
+
+/*! @brief define the receive buffer length which is used to store the user input, buffer is enabled automatically when
+* non-blocking transfer is using,
+* This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement.
+* If it is configured too small, log maybe missed, because buffer will be overwrited if buffer is too small.
+* And this value should be multiple of 4 to meet memory alignment.
+*
+*/
+#ifndef DEBUG_CONSOLE_RECEIVE_BUFFER_LEN
+#define DEBUG_CONSOLE_RECEIVE_BUFFER_LEN (512U)
+#endif /* DEBUG_CONSOLE_RECEIVE_BUFFER_LEN */
+
+#else
+#define DEBUG_CONSOLE_TRANSFER_BLOCKING
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+
+/*!@ brief define the MAX log length debug console support , that is when you call printf("log", x);, the log
+* length can not bigger than this value.
+* This macro decide the local log buffer length, the buffer locate at stack, the stack maybe overflow if
+* the buffer is too big and current task stack size not big enough.
+*/
+#ifndef DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN
+#define DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN (128U)
+#endif /* DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN */
+
+/*!@ brief define the buffer support buffer scanf log length, that is when you call scanf("log", &x);, the log
+* length can not bigger than this value.
+* As same as the DEBUG_CONSOLE_BUFFER_PRINTF_MAX_LOG_LEN.
+*/
+#ifndef DEBUG_CONSOLE_SCANF_MAX_LOG_LEN
+#define DEBUG_CONSOLE_SCANF_MAX_LOG_LEN (20U)
+#endif /* DEBUG_CONSOLE_SCANF_MAX_LOG_LEN */
+
+/*! @brief Debug console synchronization
+* User should not change these macro for synchronization mode, but add the
+* corresponding synchronization mechanism per different software environment.
+* Such as, if another RTOS is used,
+* add:
+*  #define DEBUG_CONSOLE_SYNCHRONIZATION_XXXX 3
+* in this configuration file and implement the synchronization in fsl.log.c.
+*/
+/*! @brief synchronization for baremetal software */
+#define DEBUG_CONSOLE_SYNCHRONIZATION_BM 0
+/*! @brief synchronization for freertos software */
+#define DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS 1
+
+/*! @brief RTOS synchronization mechanism disable
+* If not defined, default is enable, to avoid multitask log print mess.
+* If other RTOS is used, you can implement the RTOS's specific synchronization mechanism in fsl.log.c
+* If synchronization is disabled, log maybe messed on terminal.
+*/
+#ifndef DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+#ifdef FSL_RTOS_FREE_RTOS
+#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS
+#else
+#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM
+#endif /* FSL_RTOS_FREE_RTOS */
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+#endif /* DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION */
+
+/*! @brief echo function support
+* If you want to use the echo function,please define DEBUG_CONSOLE_ENABLE_ECHO
+* at your project setting.
+*/
+#ifndef DEBUG_CONSOLE_ENABLE_ECHO
+#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 0
+#else
+#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 1
+#endif /* DEBUG_CONSOLE_ENABLE_ECHO */
+
+/*********************************************************************/
+
+/***************Debug console other configuration*********************/
+/*! @brief Definition to printf the float number. */
+#ifndef PRINTF_FLOAT_ENABLE
+#define PRINTF_FLOAT_ENABLE 0U
+#endif /* PRINTF_FLOAT_ENABLE */
+
+/*! @brief Definition to scanf the float number. */
+#ifndef SCANF_FLOAT_ENABLE
+#define SCANF_FLOAT_ENABLE 0U
+#endif /* SCANF_FLOAT_ENABLE */
+
+/*! @brief Definition to support advanced format specifier for printf. */
+#ifndef PRINTF_ADVANCED_ENABLE
+#define PRINTF_ADVANCED_ENABLE 0U
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+/*! @brief Definition to support advanced format specifier for scanf. */
+#ifndef SCANF_ADVANCED_ENABLE
+#define SCANF_ADVANCED_ENABLE 0U
+#endif /* SCANF_ADVANCED_ENABLE */
+
+/*******************************************************************/
+
+#endif /* _FSL_DEBUG_CONSOLE_CONF_H_ */

FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_io.c

@@ -0,0 +1,655 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ * 
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+#include "fsl_io.h"
+#include "fsl_debug_console_conf.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* check avaliable device  */
+#if (defined(FSL_FEATURE_SOC_UART_COUNT) && (FSL_FEATURE_SOC_UART_COUNT != 0))
+#define DEBUG_CONSOLE_IO_UART
+#endif
+
+#if (defined(FSL_FEATURE_SOC_IUART_COUNT) && (FSL_FEATURE_SOC_IUART_COUNT != 0))
+#define DEBUG_CONSOLE_IO_IUART
+#endif
+
+#if (defined(FSL_FEATURE_SOC_LPUART_COUNT) && (FSL_FEATURE_SOC_LPUART_COUNT != 0))
+#define DEBUG_CONSOLE_IO_LPUART
+#endif
+
+#if (defined(FSL_FEATURE_SOC_LPSCI_COUNT) && (FSL_FEATURE_SOC_LPSCI_COUNT != 0))
+#define DEBUG_CONSOLE_IO_LPSCI
+#endif
+
+#if ((defined(FSL_FEATURE_SOC_USB_COUNT) && (FSL_FEATURE_SOC_USB_COUNT == 0)) && defined(BOARD_USE_VIRTUALCOM))
+#define DEBUG_CONSOLE_IO_USBCDC
+#endif
+
+#if (defined(FSL_FEATURE_SOC_FLEXCOMM_COUNT) && (FSL_FEATURE_SOC_FLEXCOMM_COUNT != 0))
+#define DEBUG_CONSOLE_IO_FLEXCOMM
+#endif
+
+#if (defined(FSL_FEATURE_SOC_VFIFO_COUNT) && (FSL_FEATURE_SOC_VFIFO_COUNT != 0))
+#define DEBUG_CONSOLE_IO_VUSART
+#endif
+
+/* configuration for debug console device */
+/* If new device is required as the low level device for debug console,
+ * Add the #elif branch and add the preprocessor macro to judge whether
+ * this kind of device exist in this SOC. */
+#if (defined DEBUG_CONSOLE_IO_UART) || (defined DEBUG_CONSOLE_IO_IUART)
+#include "fsl_uart.h"
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+static uart_handle_t s_ioUartHandler;
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+#endif /* defined DEBUG_CONSOLE_IO_UART) || (defined DEBUG_CONSOLE_IO_IUART */
+
+#if defined DEBUG_CONSOLE_IO_LPUART
+#include "fsl_lpuart.h"
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+static lpuart_handle_t s_ioLpuartHandler;
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+#endif /* DEBUG_CONSOLE_IO_LPUART */
+
+#if defined DEBUG_CONSOLE_IO_LPSCI
+#include "fsl_lpsci.h"
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+static lpsci_handle_t s_ioLpsciHandler;
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+#endif /* DEBUG_CONSOLE_IO_LPSCI */
+
+#if defined DEBUG_CONSOLE_IO_USBCDC
+#include "usb_device_config.h"
+#include "usb.h"
+#include "usb_device_cdc_acm.h"
+#include "usb_device_ch9.h"
+#include "virtual_com.h"
+#endif /* DEBUG_CONSOLE_IO_USBCDC */
+
+#if (defined DEBUG_CONSOLE_IO_FLEXCOMM) || (defined DEBUG_CONSOLE_IO_VUSART)
+#include "fsl_usart.h"
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+static usart_handle_t s_ioUsartHandler;
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+#endif /* defined DEBUG_CONSOLE_IO_FLEXCOMM) || (defined DEBUG_CONSOLE_IO_VUSART */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Debug console IO state information. */
+static io_state_t s_debugConsoleIO = {
+    .ioBase = NULL,
+    .ioType = DEBUG_CONSOLE_DEVICE_TYPE_NONE,
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+    .callBack = NULL,
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+};
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+
+#if (defined DEBUG_CONSOLE_IO_UART) || (defined DEBUG_CONSOLE_IO_IUART)
+static void UART_Callback(UART_Type *base, uart_handle_t *handle, status_t status, void *userData)
+{
+    bool tx = false, rx = false;
+    size_t size = 0U;
+
+    if (status == kStatus_UART_RxIdle)
+    {
+        rx = true;
+        size = handle->txDataSizeAll;
+    }
+
+    if (status == kStatus_UART_TxIdle)
+    {
+        tx = true;
+        size = handle->txDataSizeAll;
+    }
+
+    /* inform the buffer layer that transfer is complete */
+    if (s_debugConsoleIO.callBack != NULL)
+    {
+        /* call buffer callback function */
+        s_debugConsoleIO.callBack(&size, rx, tx);
+    }
+}
+#endif /* defined DEBUG_CONSOLE_IO_UART) || (defined DEBUG_CONSOLE_IO_IUART */
+
+#if defined DEBUG_CONSOLE_IO_LPSCI
+static void LPSCI_Callback(UART0_Type *base, lpsci_handle_t *handle, status_t status, void *userData)
+{
+    bool tx = false, rx = false;
+    size_t size = 0U;
+
+    if (status == kStatus_LPSCI_RxIdle)
+    {
+        rx = true;
+        size = handle->txDataSizeAll;
+    }
+
+    if (status == kStatus_LPSCI_TxIdle)
+    {
+        tx = true;
+        size = handle->txDataSizeAll;
+    }
+
+    /* inform the buffer layer that transfer is complete */
+    if (s_debugConsoleIO.callBack != NULL)
+    {
+        /* call buffer callback function */
+        s_debugConsoleIO.callBack(&size, rx, tx);
+    }
+}
+#endif /* DEBUG_CONSOLE_IO_LPSCI */
+
+#if defined DEBUG_CONSOLE_IO_LPUART
+static void LPUART_Callback(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *userData)
+{
+    bool tx = false, rx = false;
+    size_t size = 0U;
+
+    if (status == kStatus_LPUART_RxIdle)
+    {
+        rx = true;
+        size = handle->txDataSizeAll;
+    }
+
+    if (status == kStatus_LPUART_TxIdle)
+    {
+        tx = true;
+        size = handle->txDataSizeAll;
+    }
+
+    /* inform the buffer layer that transfer is complete */
+    if (s_debugConsoleIO.callBack != NULL)
+    {
+        /* call buffer callback function */
+        s_debugConsoleIO.callBack(&size, rx, tx);
+    }
+}
+#endif /* DEBUG_CONSOLE_IO_LPUART */
+
+#if (defined DEBUG_CONSOLE_IO_FLEXCOMM) || (defined DEBUG_CONSOLE_IO_VUSART)
+static void USART_Callback(USART_Type *base, usart_handle_t *handle, status_t status, void *userData)
+{
+    bool tx = false, rx = false;
+    size_t size = 0U;
+
+    if (status == kStatus_USART_RxIdle)
+    {
+        rx = true;
+        size = handle->txDataSizeAll;
+    }
+
+    if (status == kStatus_USART_TxIdle)
+    {
+        tx = true;
+        size = handle->txDataSizeAll;
+    }
+
+    /* inform the buffer layer that transfer is complete */
+    if (s_debugConsoleIO.callBack != NULL)
+    {
+        /* call buffer callback function */
+        s_debugConsoleIO.callBack(&size, rx, tx);
+    }
+}
+#endif /* defined DEBUG_CONSOLE_IO_FLEXCOMM) || (defined DEBUG_CONSOLE_IO_VUSART */
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+
+void IO_Init(io_state_t *io, uint32_t baudRate, uint32_t clkSrcFreq, uint8_t *ringBuffer)
+{
+    assert(NULL != io);
+
+    /* record device type/base */
+    s_debugConsoleIO.ioType = io->ioType;
+    s_debugConsoleIO.ioBase = (void *)(io->ioBase);
+
+    switch (s_debugConsoleIO.ioType)
+    {
+#if (defined DEBUG_CONSOLE_IO_UART) || (defined DEBUG_CONSOLE_IO_IUART)
+        case DEBUG_CONSOLE_DEVICE_TYPE_UART:
+        case DEBUG_CONSOLE_DEVICE_TYPE_IUART:
+        {
+            uart_config_t uart_config;
+            UART_GetDefaultConfig(&uart_config);
+            uart_config.baudRate_Bps = baudRate;
+            /* Enable clock and initial UART module follow user configure structure. */
+            UART_Init((UART_Type *)s_debugConsoleIO.ioBase, &uart_config, clkSrcFreq);
+            UART_EnableTx(s_debugConsoleIO.ioBase, true);
+            UART_EnableRx(s_debugConsoleIO.ioBase, true);
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+            s_debugConsoleIO.callBack = io->callBack;
+            /* create handler for interrupt transfer */
+            UART_TransferCreateHandle(s_debugConsoleIO.ioBase, &s_ioUartHandler, UART_Callback, NULL);
+            /* start ring buffer */
+            UART_TransferStartRingBuffer(s_debugConsoleIO.ioBase, &s_ioUartHandler, ringBuffer,
+                                         DEBUG_CONSOLE_RECEIVE_BUFFER_LEN);
+#endif
+        }
+        break;
+#endif
+
+#if defined DEBUG_CONSOLE_IO_LPUART
+        case DEBUG_CONSOLE_DEVICE_TYPE_LPUART:
+        {
+            lpuart_config_t lpuart_config;
+            LPUART_GetDefaultConfig(&lpuart_config);
+            lpuart_config.baudRate_Bps = baudRate;
+            /* Enable clock and initial UART module follow user configure structure. */
+            LPUART_Init((LPUART_Type *)s_debugConsoleIO.ioBase, &lpuart_config, clkSrcFreq);
+            LPUART_EnableTx(s_debugConsoleIO.ioBase, true);
+            LPUART_EnableRx(s_debugConsoleIO.ioBase, true);
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+            s_debugConsoleIO.callBack = io->callBack;
+            /* create handler for interrupt transfer */
+            LPUART_TransferCreateHandle(s_debugConsoleIO.ioBase, &s_ioLpuartHandler, LPUART_Callback, NULL);
+            /* start ring buffer */
+            LPUART_TransferStartRingBuffer(s_debugConsoleIO.ioBase, &s_ioLpuartHandler, ringBuffer,
+                                           DEBUG_CONSOLE_RECEIVE_BUFFER_LEN);
+#endif
+        }
+        break;
+#endif
+#if defined DEBUG_CONSOLE_IO_LPSCI
+        case DEBUG_CONSOLE_DEVICE_TYPE_LPSCI:
+        {
+            lpsci_config_t lpsci_config;
+            LPSCI_GetDefaultConfig(&lpsci_config);
+            lpsci_config.baudRate_Bps = baudRate;
+            /* Enable clock and initial UART module follow user configure structure. */
+            LPSCI_Init((UART0_Type *)s_debugConsoleIO.ioBase, &lpsci_config, clkSrcFreq);
+            LPSCI_EnableTx(s_debugConsoleIO.ioBase, true);
+            LPSCI_EnableRx(s_debugConsoleIO.ioBase, true);
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+            s_debugConsoleIO.callBack = io->callBack;
+            /* create handler for interrupt transfer */
+            LPSCI_TransferCreateHandle(s_debugConsoleIO.ioBase, &s_ioLpsciHandler, LPSCI_Callback, NULL);
+            /* start ring buffer */
+            LPSCI_TransferStartRingBuffer(s_debugConsoleIO.ioBase, &s_ioLpsciHandler, ringBuffer,
+                                          DEBUG_CONSOLE_RECEIVE_BUFFER_LEN);
+#endif
+        }
+        break;
+#endif
+#if defined DEBUG_CONSOLE_IO_USBCDC
+        case DEBUG_CONSOLE_DEVICE_TYPE_USBCDC:
+        {
+            s_debugConsoleIO.ioBase = USB_VcomInit();
+        }
+        break;
+#endif
+#if defined DEBUG_CONSOLE_IO_FLEXCOMM
+        case DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM:
+        {
+            usart_config_t usart_config;
+            USART_GetDefaultConfig(&usart_config);
+            usart_config.baudRate_Bps = baudRate;
+            /* Enable clock and initial UART module follow user configure structure. */
+            USART_Init((USART_Type *)s_debugConsoleIO.ioBase, &usart_config, clkSrcFreq);
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+            s_debugConsoleIO.callBack = io->callBack;
+            /* create handler for interrupt transfer */
+            USART_TransferCreateHandle(s_debugConsoleIO.ioBase, &s_ioUsartHandler, USART_Callback, NULL);
+            /* start ring buffer */
+            USART_TransferStartRingBuffer(s_debugConsoleIO.ioBase, &s_ioUsartHandler, ringBuffer,
+                                          DEBUG_CONSOLE_RECEIVE_BUFFER_LEN);
+#endif
+        }
+        break;
+#endif
+#if defined DEBUG_CONSOLE_IO_VUSART
+        case DEBUG_CONSOLE_DEVICE_TYPE_VUSART:
+        {
+            usart_config_t usart_config;
+            USART_GetDefaultConfig(&usart_config);
+            usart_config.baudRate_Bps = baudRate;
+            usart_config.enableRx = true;
+            usart_config.enableTx = true;
+            /* Enable clock and initial UART module follow user configure structure. */
+            USART_Init((USART_Type *)s_debugConsoleIO.ioBase, &usart_config, clkSrcFreq);
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+            s_debugConsoleIO.callBack = io->callBack;
+            /* create handler for interrupt transfer */
+            USART_TransferCreateHandle(s_debugConsoleIO.ioBase, &s_ioUsartHandler, USART_Callback, NULL);
+            /* start ring buffer */
+            USART_TransferStartRingBuffer(s_debugConsoleIO.ioBase, &s_ioUsartHandler, ringBuffer,
+                                          DEBUG_CONSOLE_RECEIVE_BUFFER_LEN);
+#endif
+        }
+        break;
+#endif
+    }
+}
+
+status_t IO_Deinit(void)
+{
+    if (s_debugConsoleIO.ioType == DEBUG_CONSOLE_DEVICE_TYPE_NONE)
+    {
+        return kStatus_Success;
+    }
+
+    switch (s_debugConsoleIO.ioType)
+    {
+#if (defined DEBUG_CONSOLE_IO_UART) || (defined DEBUG_CONSOLE_IO_IUART)
+        case DEBUG_CONSOLE_DEVICE_TYPE_UART:
+        case DEBUG_CONSOLE_DEVICE_TYPE_IUART:
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+            /* stop ring buffer */
+            UART_TransferStopRingBuffer(s_debugConsoleIO.ioBase, &s_ioUartHandler);
+#endif
+            /* Disable UART module. */
+            UART_Deinit((UART_Type *)s_debugConsoleIO.ioBase);
+
+            break;
+#endif
+#if defined DEBUG_CONSOLE_IO_LPSCI
+        case DEBUG_CONSOLE_DEVICE_TYPE_LPSCI:
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+            /* stop ring buffer */
+            LPSCI_TransferStopRingBuffer(s_debugConsoleIO.ioBase, &s_ioLpsciHandler);
+#endif
+            /* Disable LPSCI module. */
+            LPSCI_Deinit((UART0_Type *)s_debugConsoleIO.ioBase);
+
+            break;
+#endif
+#if defined DEBUG_CONSOLE_IO_LPUART
+        case DEBUG_CONSOLE_DEVICE_TYPE_LPUART:
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+            /* stop ring buffer */
+            LPUART_TransferStopRingBuffer(s_debugConsoleIO.ioBase, &s_ioLpuartHandler);
+#endif
+            /* Disable LPUART module. */
+            LPUART_Deinit((LPUART_Type *)s_debugConsoleIO.ioBase);
+
+            break;
+#endif
+#if defined DEBUG_CONSOLE_IO_USBCDC
+        case DEBUG_CONSOLE_DEVICE_TYPE_USBCDC:
+            /* Disable USBCDC module. */
+            USB_VcomDeinit(s_debugConsoleIO.ioBase);
+            break;
+#endif
+#if (defined DEBUG_CONSOLE_IO_FLEXCOMM) || (defined DEBUG_CONSOLE_IO_VUSART)
+        case DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM:
+        case DEBUG_CONSOLE_DEVICE_TYPE_VUSART:
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+            /* stop ring buffer */
+            USART_TransferStopRingBuffer(s_debugConsoleIO.ioBase, &s_ioUsartHandler);
+#endif
+            /* deinit IO */
+            USART_Deinit((USART_Type *)s_debugConsoleIO.ioBase);
+
+            break;
+#endif
+        default:
+            s_debugConsoleIO.ioType = DEBUG_CONSOLE_DEVICE_TYPE_NONE;
+            break;
+    }
+
+    s_debugConsoleIO.ioType = DEBUG_CONSOLE_DEVICE_TYPE_NONE;
+
+    return kStatus_Success;
+}
+
+status_t IO_WaitIdle(void)
+{
+    switch (s_debugConsoleIO.ioType)
+    {
+#if (defined DEBUG_CONSOLE_IO_UART)
+        case DEBUG_CONSOLE_DEVICE_TYPE_UART:
+            /* wait transfer complete flag */
+            while (!(UART_GetStatusFlags(s_debugConsoleIO.ioBase) & kUART_TransmissionCompleteFlag))
+                ;
+            break;
+#endif
+
+#if (defined DEBUG_CONSOLE_IO_IUART)
+        case DEBUG_CONSOLE_DEVICE_TYPE_IUART:
+            /* wait transfer complete flag */
+            while (!(UART_GetStatusFlag(s_debugConsoleIO.ioBase, kUART_TxCompleteFlag)))
+                ;
+            break;
+#endif
+
+#if defined DEBUG_CONSOLE_IO_LPSCI
+        case DEBUG_CONSOLE_DEVICE_TYPE_LPSCI:
+            /* wait transfer complete flag */
+            while (!(LPSCI_GetStatusFlags(s_debugConsoleIO.ioBase) & kLPSCI_TransmissionCompleteFlag))
+                ;
+            break;
+#endif
+
+#if defined DEBUG_CONSOLE_IO_LPUART
+        case DEBUG_CONSOLE_DEVICE_TYPE_LPUART:
+            /* wait transfer complete flag */
+            while (!(LPUART_GetStatusFlags(s_debugConsoleIO.ioBase) & kLPUART_TransmissionCompleteFlag))
+                ;
+            break;
+#endif
+
+#if (defined DEBUG_CONSOLE_IO_FLEXCOMM) || (defined DEBUG_CONSOLE_IO_VUSART)
+        case DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM:
+        case DEBUG_CONSOLE_DEVICE_TYPE_VUSART:
+            /* wait transfer complete flag */
+            while (!(USART_GetStatusFlags(s_debugConsoleIO.ioBase) & kUSART_TxFifoEmptyFlag))
+                ;
+            break;
+#endif
+        default:
+            break;
+    }
+
+    return kStatus_Success;
+}
+
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+
+status_t IO_Transfer(uint8_t *ch, size_t size, bool tx)
+{
+    status_t status = kStatus_Fail;
+
+    switch (s_debugConsoleIO.ioType)
+    {
+#if (defined DEBUG_CONSOLE_IO_UART) || (defined DEBUG_CONSOLE_IO_IUART)
+        case DEBUG_CONSOLE_DEVICE_TYPE_UART:
+        case DEBUG_CONSOLE_DEVICE_TYPE_IUART:
+        {
+            uart_transfer_t transfer = {0U};
+            transfer.data = ch;
+            transfer.dataSize = size;
+            /* transfer data */
+            if (tx)
+            {
+                status = UART_TransferSendNonBlocking(s_debugConsoleIO.ioBase, &s_ioUartHandler, &transfer);
+            }
+            else
+            {
+                status = UART_TransferReceiveNonBlocking(s_debugConsoleIO.ioBase, &s_ioUartHandler, &transfer, NULL);
+            }
+        }
+        break;
+#endif
+#if defined DEBUG_CONSOLE_IO_LPSCI
+        case DEBUG_CONSOLE_DEVICE_TYPE_LPSCI:
+        {
+            lpsci_transfer_t transfer = {0U};
+            transfer.data = ch;
+            transfer.dataSize = size;
+            /* transfer data */
+            if (tx)
+            {
+                status = LPSCI_TransferSendNonBlocking(s_debugConsoleIO.ioBase, &s_ioLpsciHandler, &transfer);
+            }
+            else
+            {
+                status = LPSCI_TransferReceiveNonBlocking(s_debugConsoleIO.ioBase, &s_ioLpsciHandler, &transfer, NULL);
+            }
+        }
+        break;
+#endif
+
+#if defined DEBUG_CONSOLE_IO_LPUART
+        case DEBUG_CONSOLE_DEVICE_TYPE_LPUART:
+        {
+            lpuart_transfer_t transfer = {0U};
+            transfer.data = ch;
+            transfer.dataSize = size;
+            /* transfer data */
+            if (tx)
+            {
+                status = LPUART_TransferSendNonBlocking(s_debugConsoleIO.ioBase, &s_ioLpuartHandler, &transfer);
+            }
+            else
+            {
+                status =
+                    LPUART_TransferReceiveNonBlocking(s_debugConsoleIO.ioBase, &s_ioLpuartHandler, &transfer, NULL);
+            }
+        }
+        break;
+#endif
+
+#if defined DEBUG_CONSOLE_IO_USBCDC
+        case DEBUG_CONSOLE_DEVICE_TYPE_USBCDC:
+        {
+            if (tx)
+            {
+                USB_VcomWriteBlocking(s_debugConsoleIO.ioBase, ch, size);
+            }
+            else
+            {
+                USB_VcomReadBlocking(s_debugConsoleIO.ioBase, ch, size);
+            }
+        }
+        break;
+#endif
+
+#if (defined DEBUG_CONSOLE_IO_FLEXCOMM) || (defined DEBUG_CONSOLE_IO_VUSART)
+        case DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM:
+        case DEBUG_CONSOLE_DEVICE_TYPE_VUSART:
+        {
+            usart_transfer_t transfer = {0U};
+            transfer.data = ch;
+            transfer.dataSize = size;
+            /* transfer data */
+            if (tx)
+            {
+                status = USART_TransferSendNonBlocking(s_debugConsoleIO.ioBase, &s_ioUsartHandler, &transfer);
+            }
+            else
+            {
+                status = USART_TransferReceiveNonBlocking(s_debugConsoleIO.ioBase, &s_ioUsartHandler, &transfer, NULL);
+            }
+        }
+        break;
+#endif
+        default:
+            break;
+    }
+
+    return status;
+}
+
+#else
+
+status_t IO_Transfer(uint8_t *ch, size_t size, bool tx)
+{
+    status_t status = kStatus_Success;
+    switch (s_debugConsoleIO.ioType)
+    {
+#if (defined DEBUG_CONSOLE_IO_UART) || (defined DEBUG_CONSOLE_IO_IUART)
+        case DEBUG_CONSOLE_DEVICE_TYPE_UART:
+        case DEBUG_CONSOLE_DEVICE_TYPE_IUART:
+        {
+            if (tx)
+            {
+                UART_WriteBlocking(s_debugConsoleIO.ioBase, ch, size);
+            }
+            else
+            {
+                status = UART_ReadBlocking(s_debugConsoleIO.ioBase, ch, size);
+            }
+        }
+        break;
+#endif
+#if defined DEBUG_CONSOLE_IO_LPSCI
+        case DEBUG_CONSOLE_DEVICE_TYPE_LPSCI:
+        {
+            if (tx)
+            {
+                LPSCI_WriteBlocking(s_debugConsoleIO.ioBase, ch, size);
+            }
+            else
+            {
+                status = LPSCI_ReadBlocking(s_debugConsoleIO.ioBase, ch, size);
+            }
+        }
+        break;
+#endif
+
+#if defined DEBUG_CONSOLE_IO_LPUART
+        case DEBUG_CONSOLE_DEVICE_TYPE_LPUART:
+        {
+            if (tx)
+            {
+                LPUART_WriteBlocking(s_debugConsoleIO.ioBase, ch, size);
+            }
+            else
+            {
+                status = LPUART_ReadBlocking(s_debugConsoleIO.ioBase, ch, size);
+            }
+        }
+        break;
+#endif
+
+#if defined DEBUG_CONSOLE_IO_USBCDC
+        case DEBUG_CONSOLE_DEVICE_TYPE_USBCDC:
+        {
+            if (tx)
+            {
+                USB_VcomWriteBlocking(s_debugConsoleIO.ioBase, ch, size);
+            }
+            else
+            {
+                status = USB_VcomReadBlocking(s_debugConsoleIO.ioBase, ch, size);
+            }
+        }
+        break;
+#endif
+
+#if (defined DEBUG_CONSOLE_IO_FLEXCOMM) || (defined DEBUG_CONSOLE_IO_VUSART)
+        case DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM:
+        case DEBUG_CONSOLE_DEVICE_TYPE_VUSART:
+        {
+            if (tx)
+            {
+                USART_WriteBlocking(s_debugConsoleIO.ioBase, ch, size);
+            }
+            else
+            {
+                status = USART_ReadBlocking(s_debugConsoleIO.ioBase, ch, size);
+            }
+        }
+        break;
+#endif
+        default:
+            status = kStatus_Fail;
+            break;
+    }
+
+    return status;
+}
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */

FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_io.h

@@ -0,0 +1,95 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ * 
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _FSL_IO_H
+#define _FSL_IO_H
+
+#include "fsl_common.h"
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief define a notify callback for IO
+* @param size , transfer data size.
+* @param rx, indicate a rx transfer is success.
+* @param tx, indicate a tx transfer is success.
+*/
+typedef void (*notify)(size_t *size, bool rx, bool tx);
+
+/*! @brief State structure storing io. */
+typedef struct io_State
+{
+    void *ioBase;   /*!< Base of the IP register. */
+    uint8_t ioType; /*!< device type */
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+    notify callBack; /*!< define the callback function for buffer */
+#endif
+
+} io_state_t;
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @brief io init function.
+ *
+ * Call this function to init IO.
+ *
+ * @param io configuration pointer
+ * @param baudRate baud rate
+ * @param clkSrcFreq clock freq
+ * @param ringbuffer used to receive character
+ */
+void IO_Init(io_state_t *io, uint32_t baudRate, uint32_t clkSrcFreq, uint8_t *ringBuffer);
+
+/*!
+ * @brief Deinit IO.
+ *
+ * Call this function to Deinit IO.
+ *
+ * @return deinit status
+ */
+status_t IO_Deinit(void);
+
+/*!
+ * @brief io transfer function.
+ *
+ * Call this function to transfer log.
+ * Print log:
+ * @code
+ * IO_Transfer(ch, size, true);
+ * @endcode
+ * Scanf log:
+ * @code
+ * IO_Transfer(ch, size, false);
+ * @endcode
+ *
+ * @param   ch  transfer buffer pointer
+ * @param	size transfer size
+ * @param   tx indicate the transfer is TX or RX
+ */
+status_t IO_Transfer(uint8_t *ch, size_t size, bool tx);
+
+/*!
+ * @brief io wait idle.
+ *
+ * Call this function to wait the io idle
+ *
+ * @return Indicates whether wait idle was successful or not.
+ */
+status_t IO_WaitIdle(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _FSL_IO_H */

FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_log.c

@@ -0,0 +1,547 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ * 
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+#include "fsl_log.h"
+#include "fsl_debug_console_conf.h"
+#include "fsl_io.h"
+#ifdef FSL_RTOS_FREE_RTOS
+#include "FreeRTOS.h"
+#include "task.h"
+#include "semphr.h"
+#endif
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#ifndef BACKSPACE
+/*! @brief character backspace ASCII value */
+#define BACKSPACE 127
+#endif
+
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+/*! @brief increase pop member */
+#define LOG_CHECK_BUFFER_INDEX_OVERFLOW(index)          \
+    {                                                   \
+        if (index >= DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN) \
+        {                                               \
+            index -= DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN; \
+        }                                               \
+    \
+\
+}
+
+/*! @brief get current runing environment is ISR or not */
+#ifdef __CA7_REV
+#define IS_RUNNING_IN_ISR() SystemGetIRQNestingLevel()
+#else
+#define IS_RUNNING_IN_ISR() __get_IPSR()
+#endif /* __CA7_REV */
+
+#else
+#define IS_RUNNING_IN_ISR() (0U)
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+
+/* define for rtos */
+#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)
+/* metex semaphore */
+#define LOG_CREATE_MUTEX_SEMAPHORE(mutex) (mutex = xSemaphoreCreateMutex())
+
+#define LOG_GIVE_MUTEX_SEMAPHORE(mutex) \
+    \
+{                                \
+        if (IS_RUNNING_IN_ISR() == 0U)  \
+        {                               \
+            xSemaphoreGive(mutex);      \
+        }                               \
+    \
+}
+
+#define LOG_TAKE_MUTEX_SEMAPHORE_BLOCKING(mutex)  \
+    \
+{                                          \
+        if (IS_RUNNING_IN_ISR() == 0U)            \
+        {                                         \
+            xSemaphoreTake(mutex, portMAX_DELAY); \
+        }                                         \
+    \
+}
+
+#define LOG_TAKE_MUTEX_SEMAPHORE_NONBLOCKING(mutex, result) \
+    \
+{                                                    \
+        if (IS_RUNNING_IN_ISR() == 0U)                      \
+        {                                                   \
+            result = xSemaphoreTake(mutex, 0U);             \
+        }                                                   \
+        else                                                \
+        {                                                   \
+            result = 1U;                                    \
+        }                                                   \
+    \
+}
+
+/* Binary semaphore */
+#define LOG_CREATE_BINARY_SEMAPHORE(binary) (binary = xSemaphoreCreateBinary())
+#define LOG_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) (xSemaphoreTake(binary, portMAX_DELAY))
+#define LOG_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) (xSemaphoreGiveFromISR(binary, NULL))
+
+#elif(DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM)
+
+#define LOG_CREATE_MUTEX_SEMAPHORE(mutex)
+#define LOG_TAKE_MUTEX_SEMAPHORE_BLOCKING(mutex)
+#define LOG_GIVE_MUTEX_SEMAPHORE(mutex)
+#define LOG_CREATE_BINARY_SEMAPHORE(binary)
+#define LOG_TAKE_MUTEX_SEMAPHORE_NONBLOCKING(mutex, result) (result = 1U)
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+#define LOG_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) \
+    \
+{                                           \
+        while (!binary)                            \
+            ;                                      \
+        binary = false;                            \
+    \
+\
+}
+#define LOG_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) (binary = true)
+#else
+#define LOG_TAKE_BINARY_SEMAPHORE_BLOCKING(binary)
+#define LOG_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary)
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+
+/* add other implementation here
+*such as :
+* #elif(DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_xxx)
+*/
+
+#else
+
+#define LOG_CREATE_MUTEX_SEMAPHORE(mutex)
+#define LOG_TAKE_MUTEX_SEMAPHORE_BLOCKING(mutex)
+#define LOG_TAKE_MUTEX_SEMAPHORE_NONBLOCKING(mutex, result) (result = 1U)
+#define LOG_GIVE_MUTEX_SEMAPHORE(mutex)
+#define LOG_CREATE_BINARY_SEMAPHORE(binary)
+#define LOG_TAKE_BINARY_SEMAPHORE_BLOCKING(binary)
+#define LOG_GIVE_BINARY_SEMAPHORE(binary)
+#endif /* DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS */
+
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+/*! @brief Define the buffer
+* The total buffer size should be calucate as (BUFFER_SUPPORT_LOG_LENGTH + 1) * BUFFER_SUPPORT_LOG_NUM * 4
+*/
+typedef struct _log_buffer
+{
+    volatile uint16_t totalIndex;                     /*!< indicate the total usage of the buffer */
+    volatile uint16_t pushIndex;                      /*!< indicate the next push index */
+    volatile uint16_t popIndex;                       /*!< indicate the pop index */
+    uint8_t txBuf[DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN]; /*!< buffer to store printf log */
+
+    uint8_t rxBuf[DEBUG_CONSOLE_RECEIVE_BUFFER_LEN]; /*!< buffer to store scanf log */
+} log_buffer_t;
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+/* A global log buffer */
+static log_buffer_t s_log_buffer;
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+
+/* lock definition */
+#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+static SemaphoreHandle_t s_logPushSemaphore = NULL;
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+static SemaphoreHandle_t s_logPopSemaphore = NULL;
+static SemaphoreHandle_t s_logReadSemaphore = NULL;
+
+#elif(DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM)
+
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+
+static volatile bool s_logReadSemaphore = false; /* transferred event from ISR for bare-metal + interrupt */
+
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+
+#else
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+
+/*******************************************************************************
+* Prototypes
+******************************************************************************/
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+/*!
+ * @brief callback function for IO layer to notify LOG
+ *
+ * @param size last transfer data size
+ * @param receive indicate a RX transfer
+ * @param transmit indicate a TX transfer
+ *
+ */
+static void LOG_Transferred(size_t *size, bool receive, bool transmit);
+
+/*!
+ * @brief log push function
+ *
+ * @param buf target buffer
+ * @param size log size
+ *
+ */
+static int LOG_BufPush(uint8_t *buf, size_t size);
+
+/*!
+ * @brief Get next avaliable log
+ *
+ * @param next avaliable size
+ * @return next avaliable address
+ */
+static uint8_t *LOG_BufGetNextAvaliableLog(size_t *size);
+
+/*!
+ * @brief buf pop
+ *
+ * @param size log size popped and next available log size
+ * @return next avaliable address
+ */
+static uint8_t *LOG_BufPop(size_t *size);
+
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+
+/*!
+ * @brief read one character
+ *
+ * @param ch character address
+ * @return indicate the read status
+ *
+ */
+static status_t LOG_ReadOneCharacter(uint8_t *ch);
+
+#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION
+/*!
+ * @brief echo one character
+ *
+ * @param ch character address
+ * @param isGetchar flag to distinguish getchar from scanf
+ * @param index special for scanf to support backspace
+ * @return indicate the read status
+ *
+ */
+static status_t LOG_EchoCharacter(uint8_t *ch, bool isGetChar, int *index);
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+status_t LOG_Init(uint32_t baseAddr, uint8_t device, uint32_t baudRate, uint32_t clkSrcFreq)
+{
+    io_state_t io;
+    /* init io */
+    io.ioBase = (void *)baseAddr;
+    io.ioType = device;
+
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+    /* memset the global queue */
+    memset(&s_log_buffer, 0U, sizeof(s_log_buffer));
+    /* init callback for NON-BLOCKING */
+    io.callBack = LOG_Transferred;
+    /* io init function */
+    IO_Init(&io, baudRate, clkSrcFreq, s_log_buffer.rxBuf);
+    /* Debug console buffer push lock create */
+    LOG_CREATE_MUTEX_SEMAPHORE(s_logPushSemaphore);
+#else
+    IO_Init(&io, baudRate, clkSrcFreq, NULL);
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+
+    /* Debug console lock create */
+    LOG_CREATE_MUTEX_SEMAPHORE(s_logPopSemaphore);
+    LOG_CREATE_BINARY_SEMAPHORE(s_logReadSemaphore);
+
+    return kStatus_Success;
+}
+
+void LOG_Deinit(void)
+{
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+    /* memset the global queue */
+    memset(&s_log_buffer, 0U, sizeof(s_log_buffer));
+#endif /*DEBUG_CONSOLE_TRANSFER_NON_BLOCKING*/
+    /* Deinit IO */
+    IO_Deinit();
+}
+
+status_t LOG_WaitIdle(void)
+{
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+    /* wait buffer empty */
+    while (!(s_log_buffer.totalIndex == 0U))
+        ;
+#endif /*DEBUG_CONSOLE_TRANSFER_NON_BLOCKING*/
+    /* wait IO idle */
+    IO_WaitIdle();
+
+    return kStatus_Success;
+}
+
+int LOG_Push(uint8_t *buf, size_t size)
+{
+    assert(buf != NULL);
+
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+    /* push to buffer */
+    LOG_BufPush(buf, size);
+    buf = LOG_BufGetNextAvaliableLog(&size);
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+    /* pop log */
+    return LOG_Pop(buf, size);
+}
+
+int LOG_Pop(uint8_t *buf, size_t size)
+{
+    uint8_t getLock = 0U;
+
+    if ((0 != size) && (NULL != buf))
+    {
+        /* take POP lock, should be non-blocking */
+        LOG_TAKE_MUTEX_SEMAPHORE_NONBLOCKING(s_logPopSemaphore, getLock);
+
+        if (getLock)
+        {
+            /* call IO transfer function */
+            if (IO_Transfer(buf, size, true) != kStatus_Success)
+            {
+                size = 0U;
+            }
+            /* release POP lock */
+            LOG_GIVE_MUTEX_SEMAPHORE(s_logPopSemaphore);
+        }
+    }
+
+    return size;
+}
+
+int LOG_ReadLine(uint8_t *buf, size_t size)
+{
+    assert(buf != NULL);
+
+    int i = 0;
+
+    /* take mutex lock function */
+    LOG_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_logPushSemaphore);
+
+    for (i = 0; i < size; i++)
+    {
+        /* recieve one char every time */
+        if (LOG_ReadOneCharacter(&buf[i]) != kStatus_Success)
+        {
+            return -1;
+        }
+#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION
+        LOG_EchoCharacter(&buf[i], false, &i);
+#endif
+        /* analysis data */
+        if ((buf[i] == '\r') || (buf[i] == '\n'))
+        {
+            /* End of Line. */
+            if (i == 0)
+            {
+                buf[i] = '\0';
+                i = -1;
+            }
+            else
+            {
+                break;
+            }
+        }
+    }
+    /* get char should not add '\0'*/
+    if (i == size)
+    {
+        buf[i] = '\0';
+    }
+    else
+    {
+        buf[i + 1] = '\0';
+    }
+
+    /* release mutex lock function */
+    LOG_GIVE_MUTEX_SEMAPHORE(s_logPushSemaphore);
+
+    return i;
+}
+
+int LOG_ReadCharacter(uint8_t *ch)
+{
+    assert(ch != NULL);
+    int ret = 0;
+
+    /* take mutex lock function */
+    LOG_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_logPushSemaphore);
+    /* read one character */
+    if (LOG_ReadOneCharacter(ch) == kStatus_Success)
+    {
+        ret = 1;
+#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION
+        LOG_EchoCharacter(ch, true, NULL);
+#endif
+    }
+    else
+    {
+        ret = -1;
+    }
+    /* release mutex lock function */
+    LOG_GIVE_MUTEX_SEMAPHORE(s_logPushSemaphore);
+
+    return ret;
+}
+
+static status_t LOG_ReadOneCharacter(uint8_t *ch)
+{
+    /* recieve one char every time */
+    if (IO_Transfer(ch, 1U, false) != kStatus_Success)
+    {
+        return kStatus_Fail;
+    }
+
+    /* wait release from ISR */
+    LOG_TAKE_BINARY_SEMAPHORE_BLOCKING(s_logReadSemaphore);
+
+    return kStatus_Success;
+}
+
+#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION
+static status_t LOG_EchoCharacter(uint8_t *ch, bool isGetChar, int *index)
+{
+    /* Due to scanf take \n and \r as end of string,should not echo */
+    if (((*ch != '\r') && (*ch != '\n')) || (isGetChar))
+    {
+        /* recieve one char every time */
+        if (IO_Transfer(ch, 1U, true) != kStatus_Success)
+        {
+            return kStatus_Fail;
+        }
+    }
+
+    if (!isGetChar)
+    {
+        if ((*index > 0) && (*ch == BACKSPACE))
+        {
+            *index -= 2;
+        }
+    }
+
+    return kStatus_Success;
+}
+#endif
+
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+static int LOG_BufPush(uint8_t *buf, size_t size)
+{
+    uint32_t pushIndex = 0U, i = 0U;
+    bool pushAvaliable = false;
+
+    /* take mutex lock function */
+    LOG_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_logPushSemaphore);
+    if (size <= (DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN - s_log_buffer.totalIndex))
+    {
+        /* get push index */
+        pushIndex = s_log_buffer.pushIndex;
+        s_log_buffer.pushIndex += size;
+        /* check index overflow */
+        LOG_CHECK_BUFFER_INDEX_OVERFLOW(s_log_buffer.pushIndex);
+        /* update push/total index value */
+        s_log_buffer.totalIndex += size;
+        pushAvaliable = true;
+    }
+    /* release mutex lock function */
+    LOG_GIVE_MUTEX_SEMAPHORE(s_logPushSemaphore);
+
+    /* check the buffer if have enough space to store the log */
+    if (pushAvaliable)
+    {
+        for (i = size; i > 0; i--)
+        {
+            /* copy log to buffer, the buffer only support a fixed length argument, if the log argument
+            is longer than the fixed length, the left argument will be losed */
+            s_log_buffer.txBuf[pushIndex] = *buf++;
+            /* increase index */
+            pushIndex++;
+            /* check index overflow */
+            LOG_CHECK_BUFFER_INDEX_OVERFLOW(pushIndex);
+        }
+    }
+    else
+    {
+        size = 0U;
+    }
+
+    return size;
+}
+
+static uint8_t *LOG_BufGetNextAvaliableLog(size_t *size)
+{
+    uint16_t popIndex = s_log_buffer.popIndex;
+
+    /* get avaliable size */
+    if (s_log_buffer.totalIndex > (DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN - popIndex))
+    {
+        *size = (DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN - popIndex);
+    }
+    else
+    {
+        *size = s_log_buffer.totalIndex;
+    }
+
+    /* return address */
+    return (&(s_log_buffer.txBuf[popIndex]));
+}
+
+static uint8_t *LOG_BufPop(size_t *size)
+{
+    if (s_log_buffer.totalIndex >= *size)
+    {
+        /* decrease the log total member */
+        s_log_buffer.totalIndex -= *size;
+        /* there is more log in the queue to be pushed */
+        if (s_log_buffer.totalIndex > 0U)
+        {
+            /* update the pop index */
+            s_log_buffer.popIndex += *size;
+            /* check index overflow */
+            LOG_CHECK_BUFFER_INDEX_OVERFLOW(s_log_buffer.popIndex);
+
+            return LOG_BufGetNextAvaliableLog(size);
+        }
+        else
+        {
+            /* reset push and pop */
+            s_log_buffer.popIndex = 0U;
+            s_log_buffer.pushIndex = 0U;
+            *size = 0U;
+        }
+    }
+
+    return NULL;
+}
+
+static void LOG_Transferred(size_t *size, bool receive, bool transmit)
+{
+    uint8_t *addr = NULL;
+
+    if (transmit)
+    {
+        addr = LOG_BufPop(size);
+        /* continue pop log from buffer */
+        LOG_Pop(addr, *size);
+    }
+
+    if (receive)
+    {
+        /* release from ISR */
+        LOG_GIVE_BINARY_SEMAPHORE_FROM_ISR(s_logReadSemaphore);
+    }
+}
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */

FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_log.h

@@ -0,0 +1,103 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ * 
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _FSL_LOG_H
+#define _FSL_LOG_H
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*************************************************************************************************
+ * Prototypes
+ ************************************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @brief Initializes
+ *
+ * Call this function to init the buffer
+ * @param baseAddr, device base address
+ * @param device, device type
+ * @param baudRate, device communicate baudrate
+ * @param clkSrcFreq, device source clock freq
+ *
+ * @return              	Indicates whether initialization was successful or not.
+ * @retval kStatus_Success  Execution successfully
+ * @retval kStatus_Fail     Execution failure
+ */
+status_t LOG_Init(uint32_t baseAddr, uint8_t device, uint32_t baudRate, uint32_t clkSrcFreq);
+
+/*!
+ * @brief De-Initializes
+ *
+ * Call this function to deinit the buffer
+ *
+ * @return Indicates whether Deinit was successful or not.
+ */
+void LOG_Deinit(void);
+
+/*!
+ * @brief log push interface
+ *
+ * Call this function to print log
+ * @param fmt, buffer pointer
+ * @param size, avaliable size
+ * @return indicate the push size
+ * @retval-1 indicate buffer is full or transfer fail.
+ * @retval size return the push log size.
+ */
+int LOG_Push(uint8_t *buf, size_t size);
+
+/*!
+ * @brief log read one line function
+ *
+ * Call this function to print log
+ * @param fmt, buffer pointer
+ * @param size, avaliable size
+ * @reutrn the number of the recieved character
+ */
+int LOG_ReadLine(uint8_t *buf, size_t size);
+
+/*!
+ * @brief log read one character function
+ *
+ * Call this function to GETCHAR
+ * @param ch receive address
+ * @reutrn the number of the recieved character
+ */
+int LOG_ReadCharacter(uint8_t *ch);
+
+/*!
+ * @brief wait log and io idle
+ *
+ * Call this function to wait log buffer empty and io idle before enter low power mode.
+ * @return Indicates whether wait idle was successful or not.
+ */
+status_t LOG_WaitIdle(void);
+
+/*!
+ * @brief log pop function
+ *
+ * Call this function to pop log from buffer.
+ * @param buf buffer address to pop
+ * @param size log size to pop
+ * @return pop log size.
+ */
+int LOG_Pop(uint8_t *buf, size_t size);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif

FreeRTOSv10.2.1/FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/common/rv32m1_sdk_riscv/devices/RV32M1/utilities/fsl_str.h

@@ -0,0 +1,59 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ * 
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _FSL_STR_H
+#define _FSL_STR_H
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @brief A function pointer which is used when format printf log.
+ */
+typedef void (*printfCb)(char *buf, int32_t *indicator, char val, int len);
+
+/*!
+ * @brief This function outputs its parameters according to a formatted string.
+ *
+ * @note I/O is performed by calling given function pointer using following
+ * (*func_ptr)(c);
+ *
+ * @param[in] fmt_ptr   Format string for printf.
+ * @param[in] args_ptr  Arguments to printf.
+ * @param[in] buf  pointer to the buffer
+ * @param cb print callbck function pointer
+ *
+ * @return Number of characters to be print
+ */
+int StrFormatPrintf(const char *fmt, va_list ap, char *buf, printfCb cb);
+
+/*!
+ * @brief Converts an input line of ASCII characters based upon a provided
+ * string format.
+ *
+ * @param[in] line_ptr The input line of ASCII data.
+ * @param[in] format   Format first points to the format string.
+ * @param[in] args_ptr The list of parameters.
+ *
+ * @return Number of input items converted and assigned.
+ * @retval IO_EOF When line_ptr is empty string "".
+ */
+int StrFormatScanf(const char *line_ptr, char *format, va_list args_ptr);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _FSL_STR_H */