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Merge remote-tracking branch 'origin/main' into develop

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This commit is contained in:
Eyck Jentzsch
2024-03-20 12:29:57 +01:00
parent fe1136c7ce 06add2e20d
commit fca9f04264
106 changed files with 131 additions and 6414 deletions
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7
benchmarks/dhrystone/Makefile
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@ -2,7 +2,7 @@ TARGET := dhrystone
ISA?=imc
ASM_SRCS :=
C_SRCS := dhry_stubs.c dhry_printf.c dhry_1.c dhry_2.c
C_SRCS := dhry_stubs.c dhry_1.c dhry_2.c
HEADERS := dhry.h
BOARD=iss
@ -14,12 +14,11 @@ else
RISCV_ABI:=ilp32
endif
# '-lgcc -lm' are needed to add softfloat routines
CFLAGS := -g -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI) -mcmodel=medlow -O3 -DHZ=32768 -DTIME -DNO_INIT -fno-inline -fno-builtin-printf -fno-common -Wno-implicit \
CFLAGS := -g -march=$(RISCV_ARCH)_zicsr_zifencei -mabi=$(RISCV_ABI) -mcmodel=medlow -O3 -DHZ=32768 -DTIME -DNO_INIT -fno-inline -fno-builtin-printf -fno-common -Wno-implicit \
-funroll-loops -fpeel-loops -fgcse-sm -fgcse-las
LDFLAGS := -g -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI) -mcmodel=medlow -Wl,--wrap=scanf -Wl,--wrap=printf -Wl,--wrap=exit -lgcc -lm
LDFLAGS := -g -march=$(RISCV_ARCH)_zicsr_zifencei -mabi=$(RISCV_ABI) -mcmodel=medlow -Wl,--wrap=scanf -Wl,--wrap=printf -Wl,--wrap=exit -lgcc -lm
TOOL_DIR=$(dir $(compiler))
TRIPLET=riscv32-unknown-elf
BSP_BASE = ../../bare-metal-bsp
include $(BSP_BASE)/env/common-gcc.mk