forked from Firmware/Firmwares
fixes TGCP settings in coremark port
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parent
06add2e20d
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@ -1 +1 @@
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Subproject commit d5304739fa8db6a3c16e417c9bc15b6fad749136
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Subproject commit 4d25972e4dd8f0053cc4fbd88be1b85f4b869cae
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@ -42,7 +42,7 @@ AS = $(TRIPLET)-as
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# Flag : CFLAGS
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# Use this flag to define compiler options. Note, you can add compiler options from the command line using XCFLAGS="other flags"
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PORT_CFLAGS = -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI) -O3 -DCLOCKS_PER_SEC=10000000 -nostdlib -nostartfiles -nodefaultlibs \
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-funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -flto -g
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-funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -flto -g -DBOARD_$(BOARD)
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FLAGS_STR = "$(PORT_CFLAGS) $(XCFLAGS) $(XLFLAGS) $(LFLAGS_END)"
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CFLAGS = $(PORT_CFLAGS) -I$(PORT_DIR) -I. -DFLAGS_STR=\"$(FLAGS_STR)\" -I$(BSP_BASE)/env/$(BOARD)
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#Flag : LFLAGS_END
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@ -673,8 +673,6 @@ uart_send_char(char c)
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}
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#elif defined(BOARD_iss)
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*((uint32_t*) 0xFFFF0000) = c;
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#elif defined(BOARD_TGCP)
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//TODO: implement
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#else
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while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ;
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UART0_REG(UART_REG_TXFIFO) = c;
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