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Add allocate+free functionality for fpga

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This commit is contained in:
Johannes Wirth
2022-01-20 18:22:21 +01:00
parent 446af340c8
commit 91f28e9f2b
3 changed files with 35 additions and 7 deletions
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fpga_spn/raven_spn
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14
fpga_spn/src/dma_regs.h
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@@ -9,8 +9,9 @@
#define DMA_REG_CLEAR_INTERRUPT 0x0C #define DMA_REG_CLEAR_INTERRUPT 0x0C
#define DMA_REG_FPGA_ADDRESS 0x10 #define DMA_REG_FPGA_ADDRESS 0x10
#define DMA_REG_SC_ADDRESS 0x20 #define DMA_REG_SC_ADDRESS 0x20
#define DMA_REG_WRITE 0x30 #define DMA_REG_OPERATION 0x30 // 0 = READ, 1 = WRITE, 2 = ALLOC, 3 = FREE
#define DMA_REG_BYTES 0x40 #define DMA_REG_BYTES 0x40
#define DMA_REG_ALLOC_ADDRESS 0x50
template<uint32_t BASE_ADDR> template<uint32_t BASE_ADDR>
class dma_regs { class dma_regs {
@@ -23,7 +24,7 @@ public:
uint32_t r_address; uint32_t r_address;
uint32_t r_write; uint32_t r_operation;
uint32_t r_bytes; uint32_t r_bytes;
@@ -43,14 +44,19 @@ public:
return *reinterpret_cast<uint32_t*>(BASE_ADDR+DMA_REG_SC_ADDRESS); return *reinterpret_cast<uint32_t*>(BASE_ADDR+DMA_REG_SC_ADDRESS);
} }
static inline uint32_t & write_reg(){ static inline uint32_t & operation_reg(){
return *reinterpret_cast<uint32_t*>(BASE_ADDR+DMA_REG_WRITE); return *reinterpret_cast<uint32_t*>(BASE_ADDR+DMA_REG_OPERATION);
} }
static inline uint32_t & bytes_reg(){ static inline uint32_t & bytes_reg(){
return *reinterpret_cast<uint32_t*>(BASE_ADDR+DMA_REG_BYTES); return *reinterpret_cast<uint32_t*>(BASE_ADDR+DMA_REG_BYTES);
} }
static inline uint32_t & alloc_address_reg(){
return *reinterpret_cast<uint32_t*>(BASE_ADDR+DMA_REG_ALLOC_ADDRESS);
}
}; };
#endif // _SPN_REGS_H_ #endif // _SPN_REGS_H_

28
fpga_spn/src/raven_spn.cpp
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@@ -20,7 +20,7 @@ void run_xspn(int in_addr, int out_addr, int num_samples, int in_beats, int out_
} }
void fpga_dma(int direction, int fpga_address, int sc_address, int num_bytes) { void fpga_dma(int direction, int fpga_address, int sc_address, int num_bytes) {
dma::write_reg() = direction; dma::operation_reg() = direction;
dma::fpga_address_reg() = fpga_address; dma::fpga_address_reg() = fpga_address;
dma::sc_address_reg() = sc_address; dma::sc_address_reg() = sc_address;
dma::bytes_reg() = num_bytes; dma::bytes_reg() = num_bytes;
@@ -29,6 +29,23 @@ void fpga_dma(int direction, int fpga_address, int sc_address, int num_bytes) {
dma::clear_interrupt_reg() = 1; dma::clear_interrupt_reg() = 1;
} }
int fpga_alloc(int num_bytes) {
dma::operation_reg() = 2;
dma::bytes_reg() = num_bytes;
dma::start_reg() = 1;
wait_for_dma_interrupt();
dma::clear_interrupt_reg() = 1;
return dma::alloc_address_reg();
}
void fpga_free(int address) {
dma::operation_reg() = 3;
dma::fpga_address_reg() = address;
dma::start_reg() = 1;
wait_for_dma_interrupt();
dma::clear_interrupt_reg() = 1;
}
static void spn_interrupt_handler(){ static void spn_interrupt_handler(){
printf("spn_interrupt_handler\n"); printf("spn_interrupt_handler\n");
hw_interrupt = false; hw_interrupt = false;
@@ -49,6 +66,8 @@ int main() {
configure_irq(2, spn_interrupt_handler); configure_irq(2, spn_interrupt_handler);
configure_irq(22, dma_interrupt_handler); configure_irq(22, dma_interrupt_handler);
spn::mode_reg() = 1; spn::mode_reg() = 1;
spn::start_reg() = 1; spn::start_reg() = 1;
wait_for_spn_interrupt(); wait_for_spn_interrupt();
@@ -83,8 +102,8 @@ int main() {
int in_addr = 0x20010000; // place input samples in the SPI memory int in_addr = 0x20010000; // place input samples in the SPI memory
int out_addr = 0x20210000; int out_addr = 0x20210000;
int fpga_address_in = 0x10000000; int fpga_address_in = fpga_alloc(step * sample_bytes + 64);
int fpga_address_out = 0x20000000; int fpga_address_out = fpga_alloc(step * result_bytes + 64);
// inject SPN input data // inject SPN input data
spn_checker::input_addr_reg() = in_addr; spn_checker::input_addr_reg() = in_addr;
@@ -107,5 +126,8 @@ int main() {
in_addr += step * sample_bytes; // 5 bytes in each sample in_addr += step * sample_bytes; // 5 bytes in each sample
} }
fpga_free(fpga_address_in);
fpga_free(fpga_address_out);
return 0; return 0;
} }