forked from Firmware/Firmwares
63 lines
1.6 KiB
C++
63 lines
1.6 KiB
C++
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#ifndef _DMA_REGS_H_
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#define _DMA_REGS_H_
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#include <util/bit_field.h>
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#include <cstdint>
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#define DMA_REG_START 0x00
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#define DMA_REG_CLEAR_INTERRUPT 0x0C
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#define DMA_REG_FPGA_ADDRESS 0x10
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#define DMA_REG_SC_ADDRESS 0x20
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#define DMA_REG_OPERATION 0x30 // 0 = READ, 1 = WRITE, 2 = ALLOC, 3 = FREE
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#define DMA_REG_BYTES 0x40
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#define DMA_REG_ALLOC_ADDRESS 0x50
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template<uint32_t BASE_ADDR>
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class dma_regs {
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public:
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// storage declarations
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// BEGIN_BF_DECL(start_t, uint32_t);
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// BF_FIELD(start, 0, 1);
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// END_BF_DECL() r_start;
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uint32_t r_start;
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uint32_t r_address;
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uint32_t r_operation;
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uint32_t r_bytes;
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static inline uint32_t& start_reg(){
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return *reinterpret_cast<uint32_t*>(BASE_ADDR+DMA_REG_START);
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}
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static inline uint32_t& clear_interrupt_reg(){
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return *reinterpret_cast<uint32_t*>(BASE_ADDR+DMA_REG_CLEAR_INTERRUPT);
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}
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static inline uint32_t & fpga_address_reg(){
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return *reinterpret_cast<uint32_t*>(BASE_ADDR+DMA_REG_FPGA_ADDRESS);
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}
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static inline uint32_t & sc_address_reg(){
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return *reinterpret_cast<uint32_t*>(BASE_ADDR+DMA_REG_SC_ADDRESS);
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}
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static inline uint32_t & operation_reg(){
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return *reinterpret_cast<uint32_t*>(BASE_ADDR+DMA_REG_OPERATION);
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}
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static inline uint32_t & bytes_reg(){
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return *reinterpret_cast<uint32_t*>(BASE_ADDR+DMA_REG_BYTES);
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}
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static inline uint32_t & alloc_address_reg(){
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return *reinterpret_cast<uint32_t*>(BASE_ADDR+DMA_REG_ALLOC_ADDRESS);
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}
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};
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#endif // _SPN_REGS_H_
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