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Fixed wrong link #2

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eyck merged 1 commits from develop into master 2019-06-29 14:48:03 +01:00
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# DBT-RISE-RISCV # DBT-RISE-RISCV
Am instruction set simulator based on DBT-RISE implementing the RISC-V ISA. The project is hosted at https://git.minres.com/DBT-RISE/DBT-RISE-RISCV . Am instruction set simulator based on DBT-RISE implementing the RISC-V ISA. The project is hosted at https://git.minres.com/VP/RISCV-VP.
**DBT-RISE-RISCV README** **DBT-RISE-RISCV README**