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20b3665003
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Back-ported DVCon turorial changes
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2018-11-12 19:36:44 +01:00 |
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a899d30556
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Implemented basic HiFive1-like platform with PLL,tracing etc.
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2018-07-13 20:04:07 +02:00 |
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dfcc3ace66
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Adapted generated code to support translation block linking
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2018-05-15 18:50:11 +02:00 |
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5b6dc36c9d
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Fixed validation errors in core dsl files.
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2018-05-09 12:14:59 +02:00 |
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19b660962b
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Adapted descriptions to improved Core DSL and regenerated code
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2018-05-01 18:33:55 +02:00 |
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fc17686ff1
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Cleanup of settings
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2018-04-27 19:53:52 +02:00 |
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cff4b1d33b
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template cleanup
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2018-04-24 19:02:21 +02:00 |
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142654b0a2
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Streamline arch descriptions according to latest CoreDSL changes
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2018-04-24 17:18:24 +02:00 |
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65ceedd157
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Updated compressed instructions for RV32D
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2018-04-24 15:48:42 +02:00 |
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ce98e2ad31
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Added RV32D extension
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2018-04-24 15:33:21 +02:00 |
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48ad30dcae
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Added RV32F extension, fixed RV32M bugs
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2018-04-24 11:05:11 +02:00 |
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dcaf5467e8
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Added Berkeley softfloat library
(http://www.jhauser.us/arithmetic/SoftFloat.html) with RISCV
specialization and cmake build
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2018-04-24 10:25:37 +02:00 |
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36be8b87f1
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Added simple example plugin creating instruction histogram
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2018-02-11 21:30:52 +00:00 |
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c5a7adcef5
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Refactored code generation to use custom templates
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2018-02-09 18:34:26 +00:00 |
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7c2539bff0
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C++11 refactoring
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2018-02-06 18:26:55 +00:00 |
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f1667c195a
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Initial RV64I verification
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2017-11-23 14:48:18 +01:00 |
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5d508740fd
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Fixed 64bit integer base instruction set
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2017-11-18 00:42:33 +01:00 |
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b0dcb3b60e
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Fixed handling of compressed ISA
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2017-10-25 22:05:31 +02:00 |
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9a617dab57
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Restructured project
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2017-09-21 20:29:23 +02:00 |
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