Eyck Jentzsch dfcc3ace66 Adapted generated code to support translation block linking		2018-05-15 18:50:11 +02:00
..
templates	Adapted generated code to support translation block linking	2018-05-15 18:50:11 +02:00
.gitignore	Refactored code generation to use custom templates	2018-02-09 18:34:26 +00:00
RV32A.core_desc	Adapted descriptions to improved Core DSL and regenerated code	2018-05-01 18:33:55 +02:00
RV32C.core_desc	Fixed validation errors in core dsl files.	2018-05-09 12:14:59 +02:00
RV32D.core_desc	Fixed validation errors in core dsl files.	2018-05-09 12:14:59 +02:00
RV32F.core_desc	Fixed validation errors in core dsl files.	2018-05-09 12:14:59 +02:00
RV32IBase.core_desc	Fixed validation errors in core dsl files.	2018-05-09 12:14:59 +02:00
RV32M.core_desc	Adapted descriptions to improved Core DSL and regenerated code	2018-05-01 18:33:55 +02:00
RV64A.core_desc	Adapted descriptions to improved Core DSL and regenerated code	2018-05-01 18:33:55 +02:00
RV64IBase.core_desc	Fixed validation errors in core dsl files.	2018-05-09 12:14:59 +02:00
RV64M.core_desc	Adapted descriptions to improved Core DSL and regenerated code	2018-05-01 18:33:55 +02:00
minres_rv.core_desc	Adapted descriptions to improved Core DSL and regenerated code	2018-05-01 18:33:55 +02:00