 Eyck Jentzsch
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b4871ac725
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Preparation for multi-threading/multi-core DBT
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2017-12-07 22:37:43 +01:00 |
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Eyck Jentzsch
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b0dcb3b60e
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Fixed handling of compressed ISA
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2017-10-25 22:05:31 +02:00 |
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Eyck Jentzsch
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9970303fa4
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Changed handling of disassembler output so that tarcing becomes possible
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2017-10-22 19:29:37 +02:00 |
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Eyck Jentzsch
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b9c910b283
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clean up class vs. struct
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2017-10-12 22:41:37 +02:00 |
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Eyck Jentzsch
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f2b9ca84b0
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Adaptation to changes in libraries
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2017-10-12 14:49:33 +02:00 |
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Eyck Jentzsch
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4867cca187
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Added SystemC version of HiFive FE310
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2017-10-04 10:31:11 +02:00 |
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Eyck Jentzsch
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d8184abbcc
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Refactored file dependencies to decouple components
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2017-09-26 17:48:51 +02:00 |
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Eyck Jentzsch
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710d61e304
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Fixed target adapter to properly handle register reading
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2017-09-25 20:38:40 +02:00 |
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Eyck Jentzsch
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b38319f9c2
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Applied clang-format
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2017-09-22 11:23:23 +02:00 |
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Eyck Jentzsch
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39150b68c0
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Adapted to log system
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2017-09-22 10:11:29 +02:00 |
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Eyck Jentzsch
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9a617dab57
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Restructured project
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2017-09-21 20:29:23 +02:00 |
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Eyck Jentzsch
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aa8c2138c6
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Added initial SystemC structure and removed easylogging
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2017-09-21 13:13:01 +02:00 |
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Eyck Jentzsch
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1cb492b594
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Renamed hart name and core wrapper name
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2017-08-29 16:56:57 +02:00 |