5 Commits

Author	SHA1	Message	Date
Eyck Jentzsch	74601e280e	Merge branch 'master' of https://git.minres.com/VP/RISCV.git	2019-06-28 22:43:24 +02:00
Eyck Jentzsch	eb8365f4c3	Updated SC-Components	2019-04-11 05:40:02 +00:00
Eyck Jentzsch	cb3a0d8411	Merge branch 'develop'	2019-01-10 11:15:02 +00:00
Eyck Jentzsch	20b3665003	Back-ported DVCon turorial changes	2018-11-12 19:36:44 +01:00
Eyck Jentzsch	38099e3fc6	Added ADC, H-Bridge and motor models, refactored project structure	2018-07-28 09:45:49 +02:00