VP/HIFIVE1-VP
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adapt to changes in scc

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This commit is contained in:
Eyck Jentzsch
2021-08-26 17:27:33 +02:00
parent b36c572e7b
commit f013775b00
24 changed files with 138 additions and 145 deletions
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22
platform/src/sysc/gpio.cpp
View File

@ -60,7 +60,7 @@ gpio::gpio(sc_core::sc_module_name nm)
SC_METHOD(reset_cb);
sensitive << rst_i;
dont_initialize();
auto pins_i_cb = [this](unsigned int tag, tlm::tlm_signal_gp<sc_logic> &gp, tlm::tlm_phase &phase,
auto pins_i_cb = [this](unsigned int tag, tlm::scc::tlm_signal_gp<sc_logic> &gp, tlm::tlm_phase &phase,
sc_core::sc_time &delay) -> tlm::tlm_sync_enum {
this->pin_input(tag, gp, delay);
return tlm::TLM_COMPLETED;
@ -70,7 +70,7 @@ gpio::gpio(sc_core::sc_module_name nm)
s.register_nb_transport(pins_i_cb, i);
++i;
}
auto iof0_i_cb = [this](unsigned int tag, tlm::tlm_signal_gp<bool> &gp, tlm::tlm_phase &phase,
auto iof0_i_cb = [this](unsigned int tag, tlm::scc::tlm_signal_gp<bool> &gp, tlm::tlm_phase &phase,
sc_core::sc_time &delay) -> tlm::tlm_sync_enum {
last_iof0[tag] = gp.get_value();
this->iof_input(tag, 0, gp, delay);
@ -81,7 +81,7 @@ gpio::gpio(sc_core::sc_module_name nm)
s.register_nb_transport(iof0_i_cb, i);
++i;
}
auto iof1_i_cb = [this](unsigned int tag, tlm::tlm_signal_gp<bool> &gp, tlm::tlm_phase &phase,
auto iof1_i_cb = [this](unsigned int tag, tlm::scc::tlm_signal_gp<bool> &gp, tlm::tlm_phase &phase,
sc_core::sc_time &delay) -> tlm::tlm_sync_enum {
last_iof1[tag] = gp.get_value();
this->iof_input(tag, 1, gp, delay);
@ -111,7 +111,7 @@ gpio::~gpio() = default;
void gpio::before_end_of_elaboration() {
if (write_to_ws.get_value()) {
SCCTRACE() << "Adding WS handler for " << (std::string{"/ws/"} + name());
SCCTRACE(SCMOD) << "Adding WS handler for " << (std::string{"/ws/"} + name());
handler = std::make_shared<WsHandler>();
sc_comm_singleton::inst().registerWebSocketHandler((std::string{"/ws/"} + name()).c_str(), handler);
}
@ -128,7 +128,7 @@ void gpio::reset_cb() {
void gpio::clock_cb() { this->clk = clk_i.read(); }
tlm::tlm_phase gpio::write_output(tlm::tlm_signal_gp<sc_dt::sc_logic> &gp, size_t i, sc_dt::sc_logic val) {
tlm::tlm_phase gpio::write_output(tlm::scc::tlm_signal_gp<sc_dt::sc_logic> &gp, size_t i, sc_dt::sc_logic val) {
sc_core::sc_time delay{SC_ZERO_TIME};
tlm::tlm_phase phase{tlm::BEGIN_REQ};
gp.set_command(tlm::TLM_WRITE_COMMAND);
@ -140,7 +140,7 @@ tlm::tlm_phase gpio::write_output(tlm::tlm_signal_gp<sc_dt::sc_logic> &gp, size_
void gpio::update_pins(uint32_t changed_bits) {
sc_core::sc_inout_rv<32>::data_type out_val;
tlm::tlm_signal_gp<sc_dt::sc_logic> gp;
tlm::scc::tlm_signal_gp<sc_dt::sc_logic> gp;
sc_logic val;
for (size_t i = 0, mask = 1; i < 32; ++i, mask <<= 1) {
if (changed_bits & mask) {
@ -161,7 +161,7 @@ void gpio::update_pins(uint32_t changed_bits) {
}
}
void gpio::pin_input(unsigned int tag, tlm::tlm_signal_gp<sc_logic> &gp, sc_core::sc_time &delay) {
void gpio::pin_input(unsigned int tag, tlm::scc::tlm_signal_gp<sc_logic> &gp, sc_core::sc_time &delay) {
if (delay > SC_ZERO_TIME) {
wait(delay);
delay = SC_ZERO_TIME;
@ -179,11 +179,11 @@ void gpio::pin_input(unsigned int tag, tlm::tlm_signal_gp<sc_logic> &gp, sc_core
}
}
void gpio::forward_pin_input(unsigned int tag, tlm::tlm_signal_gp<sc_logic> &gp) {
void gpio::forward_pin_input(unsigned int tag, tlm::scc::tlm_signal_gp<sc_logic> &gp) {
const auto mask = 1U << tag;
if (regs->iof_en & mask) {
auto &socket = regs->iof_sel & mask ? iof1_o[tag] : iof0_o[tag];
tlm::tlm_signal_gp<> new_gp;
tlm::scc::tlm_signal_gp<> new_gp;
for (size_t i = 0; i < socket.size(); ++i) {
sc_core::sc_time delay{SC_ZERO_TIME};
tlm::tlm_phase phase{tlm::BEGIN_REQ};
@ -196,7 +196,7 @@ void gpio::forward_pin_input(unsigned int tag, tlm::tlm_signal_gp<sc_logic> &gp)
}
}
void gpio::iof_input(unsigned int tag, unsigned iof_idx, tlm::tlm_signal_gp<> &gp, sc_core::sc_time &delay) {
void gpio::iof_input(unsigned int tag, unsigned iof_idx, tlm::scc::tlm_signal_gp<> &gp, sc_core::sc_time &delay) {
if (delay > SC_ZERO_TIME) {
wait(delay);
delay = SC_ZERO_TIME;
@ -209,7 +209,7 @@ void gpio::iof_input(unsigned int tag, unsigned iof_idx, tlm::tlm_signal_gp<> &g
for (size_t i = 0; i < socket.size(); ++i) {
sc_core::sc_time delay{SC_ZERO_TIME};
tlm::tlm_phase phase{tlm::BEGIN_REQ};
tlm::tlm_signal_gp<sc_logic> new_gp;
tlm::scc::tlm_signal_gp<sc_logic> new_gp;
new_gp.set_command(tlm::TLM_WRITE_COMMAND);
auto val = gp.get_value();
new_gp.set_value(val ? sc_dt::Log_1 : sc_dt::Log_0);

12
platform/src/sysc/hifive1.cpp
View File

@ -87,27 +87,27 @@ BOOST_PP_REPEAT(8, PORT_NAMING, _)
s_gpio[20].out(h_bridge[4]);
s_gpio[19].out(h_bridge[5]);
// proxy callbacks
h_bridge[0].register_nb_transport([this](tlm::tlm_signal_gp<sc_logic> &gp, tlm::tlm_phase &phase, sc_time &delay) -> tlm::tlm_sync_enum {
h_bridge[0].register_nb_transport([this](tlm::scc::tlm_signal_gp<sc_logic> &gp, tlm::tlm_phase &phase, sc_time &delay) -> tlm::tlm_sync_enum {
ha_o.write(gp.get_value());
return tlm::TLM_ACCEPTED;
});
h_bridge[1].register_nb_transport([this](tlm::tlm_signal_gp<sc_logic> &gp, tlm::tlm_phase &phase, sc_time &delay) -> tlm::tlm_sync_enum {
h_bridge[1].register_nb_transport([this](tlm::scc::tlm_signal_gp<sc_logic> &gp, tlm::tlm_phase &phase, sc_time &delay) -> tlm::tlm_sync_enum {
la_o.write(gp.get_value());
return tlm::TLM_ACCEPTED;
});
h_bridge[2].register_nb_transport([this](tlm::tlm_signal_gp<sc_logic> &gp, tlm::tlm_phase &phase, sc_time &delay) -> tlm::tlm_sync_enum {
h_bridge[2].register_nb_transport([this](tlm::scc::tlm_signal_gp<sc_logic> &gp, tlm::tlm_phase &phase, sc_time &delay) -> tlm::tlm_sync_enum {
hb_o.write(gp.get_value());
return tlm::TLM_ACCEPTED;
});
h_bridge[3].register_nb_transport([this](tlm::tlm_signal_gp<sc_logic> &gp, tlm::tlm_phase &phase, sc_time &delay) -> tlm::tlm_sync_enum {
h_bridge[3].register_nb_transport([this](tlm::scc::tlm_signal_gp<sc_logic> &gp, tlm::tlm_phase &phase, sc_time &delay) -> tlm::tlm_sync_enum {
lb_o.write(gp.get_value());
return tlm::TLM_ACCEPTED;
});
h_bridge[4].register_nb_transport([this](tlm::tlm_signal_gp<sc_logic> &gp, tlm::tlm_phase &phase, sc_time &delay) -> tlm::tlm_sync_enum {
h_bridge[4].register_nb_transport([this](tlm::scc::tlm_signal_gp<sc_logic> &gp, tlm::tlm_phase &phase, sc_time &delay) -> tlm::tlm_sync_enum {
hc_o.write(gp.get_value());
return tlm::TLM_ACCEPTED;
});
h_bridge[5].register_nb_transport([this](tlm::tlm_signal_gp<sc_logic> &gp, tlm::tlm_phase &phase, sc_time &delay) -> tlm::tlm_sync_enum {
h_bridge[5].register_nb_transport([this](tlm::scc::tlm_signal_gp<sc_logic> &gp, tlm::tlm_phase &phase, sc_time &delay) -> tlm::tlm_sync_enum {
lc_o.write(gp.get_value());
return tlm::TLM_ACCEPTED;
});

16
platform/src/sysc/mcp_adc.cpp
View File

@ -40,16 +40,16 @@ namespace sysc {
mcp_3008::mcp_3008(sc_core::sc_module_name nm)
: sysc::mcp_adc(nm, 8)
, last_tx_start(sc_core::SC_ZERO_TIME) {
sck_i.register_nb_transport([this](tlm::tlm_signal_gp<sc_dt::sc_logic> &gp, tlm::tlm_phase &phase,
sck_i.register_nb_transport([this](tlm::scc::tlm_signal_gp<sc_dt::sc_logic> &gp, tlm::tlm_phase &phase,
sc_core::sc_time &delay) -> tlm::tlm_sync_enum { return tlm::TLM_COMPLETED; });
mosi_i.register_nb_transport([this](tlm::tlm_signal_gp<sc_dt::sc_logic> &gp, tlm::tlm_phase &phase,
mosi_i.register_nb_transport([this](tlm::scc::tlm_signal_gp<sc_dt::sc_logic> &gp, tlm::tlm_phase &phase,
sc_core::sc_time &delay) -> tlm::tlm_sync_enum {
if (cs_v == sc_dt::Log_0) return receive(gp, phase, delay);
return tlm::TLM_COMPLETED;
});
cs_i.register_nb_transport([this](tlm::tlm_signal_gp<sc_dt::sc_logic> &gp, tlm::tlm_phase &phase,
cs_i.register_nb_transport([this](tlm::scc::tlm_signal_gp<sc_dt::sc_logic> &gp, tlm::tlm_phase &phase,
sc_core::sc_time &delay) -> tlm::tlm_sync_enum {
if (cs_v != sc_dt::Log_0 && gp.get_value() == sc_dt::Log_0) {
idx = 0; // falling edge
@ -60,7 +60,7 @@ mcp_3008::mcp_3008(sc_core::sc_module_name nm)
});
}
tlm::tlm_sync_enum mcp_3008::receive(tlm::tlm_signal_gp<sc_dt::sc_logic> &gp, tlm::tlm_phase &phase,
tlm::tlm_sync_enum mcp_3008::receive(tlm::scc::tlm_signal_gp<sc_dt::sc_logic> &gp, tlm::tlm_phase &phase,
sc_core::sc_time &delay) {
gp.get_extension(ext);
if (ext) {
@ -100,7 +100,7 @@ mcp_3208::mcp_3208(sc_core::sc_module_name nm)
: sysc::mcp_adc(nm, 8)
, ext(nullptr)
, last_tx_start(sc_core::SC_ZERO_TIME) {
sck_i.register_nb_transport([this](tlm::tlm_signal_gp<sc_dt::sc_logic> &gp, tlm::tlm_phase &phase,
sck_i.register_nb_transport([this](tlm::scc::tlm_signal_gp<sc_dt::sc_logic> &gp, tlm::tlm_phase &phase,
sc_core::sc_time &delay) -> tlm::tlm_sync_enum {
auto ret = tlm::TLM_COMPLETED;
if (cs_v == sc_dt::Log_0) ret = receive(gp, phase, delay);
@ -108,13 +108,13 @@ mcp_3208::mcp_3208(sc_core::sc_module_name nm)
return ret;
});
mosi_i.register_nb_transport([this](tlm::tlm_signal_gp<sc_dt::sc_logic> &gp, tlm::tlm_phase &phase,
mosi_i.register_nb_transport([this](tlm::scc::tlm_signal_gp<sc_dt::sc_logic> &gp, tlm::tlm_phase &phase,
sc_core::sc_time &delay) -> tlm::tlm_sync_enum {
mosi_v = gp.get_value();
return tlm::TLM_COMPLETED;
});
cs_i.register_nb_transport([this](tlm::tlm_signal_gp<sc_dt::sc_logic> &gp, tlm::tlm_phase &phase,
cs_i.register_nb_transport([this](tlm::scc::tlm_signal_gp<sc_dt::sc_logic> &gp, tlm::tlm_phase &phase,
sc_core::sc_time &delay) -> tlm::tlm_sync_enum {
if (cs_v != sc_dt::Log_0 && gp.get_value() == sc_dt::Log_0) { // falling edge of CS
idx = 0;
@ -128,7 +128,7 @@ mcp_3208::mcp_3208(sc_core::sc_module_name nm)
sensitive << clk_sample_evt;
}
tlm::tlm_sync_enum mcp_3208::receive(tlm::tlm_signal_gp<sc_dt::sc_logic> &gp, tlm::tlm_phase &phase,
tlm::tlm_sync_enum mcp_3208::receive(tlm::scc::tlm_signal_gp<sc_dt::sc_logic> &gp, tlm::tlm_phase &phase,
sc_core::sc_time &delay) {
gp.get_extension(ext);
if (ext) {

2
platform/src/sysc/pwm.cpp
View File

@ -223,7 +223,7 @@ void pwm::update_counter() {
void pwm::write_cmpgpio(size_t index, bool val) {
if (cmpgpio_o[index].get_interface()) {
tlm::tlm_phase phase(tlm::BEGIN_REQ);
tlm::tlm_signal_gp<> gp;
tlm::scc::tlm_signal_gp<> gp;
sc_core::sc_time delay(SC_ZERO_TIME);
gp.set_value(val);
cmpgpio_o[index]->nb_transport_fw(gp, phase, delay);

28
platform/src/sysc/spi.cpp
View File

@ -32,8 +32,8 @@
#include "sysc/SiFive/spi.h"
#include "cci_configuration"
#include "scc/signal_initiator_mixin.h"
#include "scc/signal_target_mixin.h"
#include "tlm/scc/signal_initiator_mixin.h"
#include "tlm/scc/signal_target_mixin.h"
#include "scc/tlm_target.h"
#include "scc/utilities.h"
@ -55,15 +55,15 @@ public:
~beh() override;
protected:
scc::tlm_signal_bool_opt_out _sck_o;
scc::tlm_signal_bool_opt_out _mosi_o;
scc::tlm_signal_bool_opt_in _miso_i;
sc_core::sc_vector<scc::tlm_signal_bool_opt_out> _scs_o;
tlm::scc::tlm_signal_bool_opt_out _sck_o;
tlm::scc::tlm_signal_bool_opt_out _mosi_o;
tlm::scc::tlm_signal_bool_opt_in _miso_i;
sc_core::sc_vector<tlm::scc::tlm_signal_bool_opt_out> _scs_o;
void clock_cb();
void reset_cb();
void transmit_data();
void receive_data(tlm::tlm_signal_gp<> &gp, sc_core::sc_time &delay);
void receive_data(tlm::scc::tlm_signal_gp<> &gp, sc_core::sc_time &delay);
void update_irq();
sc_core::sc_event update_irq_evt;
sc_core::sc_time clk;
@ -96,7 +96,7 @@ beh::beh(sc_core::sc_module_name nm)
dont_initialize();
SC_THREAD(transmit_data);
_miso_i.register_nb_transport(
[this](tlm::tlm_signal_gp<bool> &gp, tlm::tlm_phase &phase, sc_core::sc_time &delay) -> tlm::tlm_sync_enum {
[this](tlm::scc::tlm_signal_gp<bool> &gp, tlm::tlm_phase &phase, sc_core::sc_time &delay) -> tlm::tlm_sync_enum {
this->receive_data(gp, delay);
return tlm::TLM_COMPLETED;
});
@ -128,7 +128,7 @@ beh::beh(sc_core::sc_module_name nm)
if (regs->r_csmode.mode == 2 && regs->r_csmode.mode != bit_sub<0, 2>(data) && regs->r_csid < 4) {
tlm::tlm_phase phase(tlm::BEGIN_REQ);
sc_core::sc_time delay(SC_ZERO_TIME);
tlm::tlm_signal_gp<> gp;
tlm::scc::tlm_signal_gp<> gp;
gp.set_command(tlm::TLM_WRITE_COMMAND);
gp.set_value(true);
_scs_o[regs->r_csid]->nb_transport_fw(gp, phase, delay);
@ -140,7 +140,7 @@ beh::beh(sc_core::sc_module_name nm)
if (regs->r_csmode.mode == 2 && regs->csid != data && regs->r_csid < 4) {
tlm::tlm_phase phase(tlm::BEGIN_REQ);
sc_core::sc_time delay(SC_ZERO_TIME);
tlm::tlm_signal_gp<> gp;
tlm::scc::tlm_signal_gp<> gp;
gp.set_command(tlm::TLM_WRITE_COMMAND);
gp.set_value(true);
_scs_o[regs->r_csid]->nb_transport_fw(gp, phase, delay);
@ -153,7 +153,7 @@ beh::beh(sc_core::sc_module_name nm)
if (regs->r_csmode.mode == 2 && diff != 0 && (regs->r_csid < 4) && (diff & (1 << regs->r_csid)) != 0) {
tlm::tlm_phase phase(tlm::BEGIN_REQ);
sc_core::sc_time delay(SC_ZERO_TIME);
tlm::tlm_signal_gp<> gp;
tlm::scc::tlm_signal_gp<> gp;
gp.set_command(tlm::TLM_WRITE_COMMAND);
gp.set_value(true);
_scs_o[regs->r_csid]->nb_transport_fw(gp, phase, delay);
@ -195,10 +195,10 @@ void beh::transmit_data() {
sc_core::sc_time bit_duration(SC_ZERO_TIME);
sc_core::sc_time start_time;
auto set_bit = [&](bool val, scc::tlm_signal_bool_opt_out &socket,
auto set_bit = [&](bool val, tlm::scc::tlm_signal_bool_opt_out &socket,
bool data_valid = false) -> std::pair<bool, uint32_t> {
if (socket.get_interface() == nullptr) return std::pair<bool, uint32_t>{false, 0};
auto *gp = tlm::tlm_signal_gp<>::create();
auto *gp = tlm::scc::tlm_signal_gp<>::create();
auto *ext = new sysc::tlm_signal_spi_extension();
ext->tx.data_bits = 8;
ext->start_time = start_time;
@ -253,7 +253,7 @@ void beh::transmit_data() {
}
}
void beh::receive_data(tlm::tlm_signal_gp<> &gp, sc_core::sc_time &delay) {}
void beh::receive_data(tlm::scc::tlm_signal_gp<> &gp, sc_core::sc_time &delay) {}
void beh::update_irq() {
regs->r_ip.rxwm = regs->r_rxmark.rxmark < rx_fifo.num_available();

8
platform/src/sysc/terminal.cpp
View File

@ -46,7 +46,7 @@ terminal::terminal(const sc_core::sc_module_name &nm)
, NAMED(tx_o)
, NAMED(rx_i)
, NAMED(write_to_ws, false) {
rx_i.register_nb_transport([this](tlm::tlm_signal_gp<sc_dt::sc_logic> &gp, tlm::tlm_phase &phase,
rx_i.register_nb_transport([this](tlm::scc::tlm_signal_gp<sc_dt::sc_logic> &gp, tlm::tlm_phase &phase,
sc_core::sc_time &delay) -> tlm::tlm_sync_enum {
this->receive(gp, delay);
return tlm::TLM_COMPLETED;
@ -57,13 +57,13 @@ terminal::~terminal() = default;
void terminal::before_end_of_elaboration() {
if (write_to_ws.get_value()) {
SCCTRACE() << "Adding WS handler for " << (std::string{"/ws/"} + name());
SCCTRACE(SCMOD) << "Adding WS handler for " << (std::string{"/ws/"} + name());
handler = std::make_shared<WsHandler>();
sc_comm_singleton::inst().registerWebSocketHandler((std::string{"/ws/"} + name()).c_str(), handler);
}
}
void terminal::receive(tlm::tlm_signal_gp<sc_dt::sc_logic> &gp, sc_core::sc_time &delay) {
void terminal::receive(tlm::scc::tlm_signal_gp<sc_dt::sc_logic> &gp, sc_core::sc_time &delay) {
sysc::tlm_signal_uart_extension *ext;
gp.get_extension(ext);
if (ext && ext->start_time != last_tx_start) {
@ -80,7 +80,7 @@ void terminal::receive(tlm::tlm_signal_gp<sc_dt::sc_logic> &gp, sc_core::sc_time
this->handler->send(os.str());
});
else
SCCINFO(this->name()) << " receive: '" << msg << "'";
SCCINFO(SCMOD) << " receive: '" << msg << "'";
queue.clear();
}
}

6
platform/src/sysc/uart.cpp
View File

@ -62,7 +62,7 @@ uart::uart(sc_core::sc_module_name nm)
dont_initialize();
SC_THREAD(transmit_data);
rx_i.register_nb_transport(
[this](tlm::tlm_signal_gp<bool> &gp, tlm::tlm_phase &phase, sc_core::sc_time &delay) -> tlm::tlm_sync_enum {
[this](tlm::scc::tlm_signal_gp<bool> &gp, tlm::tlm_phase &phase, sc_core::sc_time &delay) -> tlm::tlm_sync_enum {
this->receive_data(gp, delay);
return tlm::TLM_COMPLETED;
});
@ -123,7 +123,7 @@ void uart::transmit_data() {
sc_core::sc_time start_time;
auto set_bit = [&](bool val) {
auto *gp = tlm::tlm_signal_gp<>::create();
auto *gp = tlm::scc::tlm_signal_gp<>::create();
auto *ext = new sysc::tlm_signal_uart_extension();
ext->tx.data_bits = 8;
ext->tx.parity = false;
@ -161,7 +161,7 @@ void uart::transmit_data() {
}
}
void uart::receive_data(tlm::tlm_signal_gp<> &gp, sc_core::sc_time &delay) {
void uart::receive_data(tlm::scc::tlm_signal_gp<> &gp, sc_core::sc_time &delay) {
sysc::tlm_signal_uart_extension *ext{nullptr};
gp.get_extension(ext);
if (ext && ext->start_time != rx_last_start) {