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README.md
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README.md
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# DBT-RISE-RiscV
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Am instruction set simulator based on DBT-RISE implementing the Risc-V ISA
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# DBT-RISE-RISCV
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Am instruction set simulator based on DBT-RISE implementing the RISC-V ISA
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**DBT-RISE-RiscV README**
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**DBT-RISE-RISCV README**
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This is work in progress, so use at your own risk. Goal is to implement an open-source ISS which can easily embedded e.g. into SystemC Virtual Prototypes. It used code generation to allow easy extension and adaptation of the used instruction.
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The Risc-V ISS reaches about 20MIPS at an Intel Core i7-2600K.
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The RISC-V ISS reaches about 20MIPS at an Intel Core i7-2600K.
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The implementation is based on LLVM 4.0. Eclipse CDT 4.7 (Oxygen) is recommended as IDE.
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**Quick start**
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* you need to have a decent compiler, make, python, and cmake installed
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* install LLVM 4.0 according to http://apt.llvm.org/ (if it is not already provided by your distribution)
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* install LLVM 4.0 according to http://apt.llvm.org/ (if it is not already provided by your distribution e.g by Ubuntu 17.04)
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* install conan.io (see also http://docs.conan.io/en/latest/installation.html):
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```
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pip install conan
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```
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compiler.libcxx=libstdc++11
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```
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in $HOME/.conan/profiles/default
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in $HOME/.conan/profiles/default
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