Added instruction enumeration and some cleanup
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@ -811,17 +811,18 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_csr(unsigned
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}
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template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_cycle(unsigned addr, reg_t &val) {
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auto cycle_val=this->cycles ? this->cycles : this->reg.icount;
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if (addr == mcycle) {
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val = static_cast<reg_t>(this->reg.icount);
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val = static_cast<reg_t>(cycle_val);
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} else if (addr == mcycleh) {
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if (sizeof(typename traits<BASE>::reg_t) != 4) return iss::Err;
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val = static_cast<reg_t>((this->reg.icount) >> 32);
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val = static_cast<reg_t>(cycle_val >> 32);
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}
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return iss::Ok;
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}
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template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_time(unsigned addr, reg_t &val) {
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uint64_t time_val=this->reg.icount>>12;
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uint64_t time_val=(this->cycles?this->cycles:this->reg.icount) / (100000000/32768-1); //-> ~3052;
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if (addr == time) {
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val = static_cast<reg_t>(time_val);
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} else if (addr == timeh) {
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@ -28,7 +28,7 @@
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// Created on: Fri Dec 15 14:41:57 CET 2017
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// Created on: Sat Dec 30 12:50:15 CET 2017
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// * rv32imac.h Author: <CoreDSL Generator>
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//
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////////////////////////////////////////////////////////////////////////////////
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@ -159,45 +159,48 @@ struct rv32imac: public arch_if {
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protected:
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struct RV32IMAC_regs {
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uint32_t X0;
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uint32_t X1;
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uint32_t X2;
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uint32_t X3;
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uint32_t X4;
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uint32_t X5;
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uint32_t X6;
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uint32_t X7;
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uint32_t X8;
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uint32_t X9;
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uint32_t X10;
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uint32_t X11;
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uint32_t X12;
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uint32_t X13;
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uint32_t X14;
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uint32_t X15;
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uint32_t X16;
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uint32_t X17;
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uint32_t X18;
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uint32_t X19;
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uint32_t X20;
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uint32_t X21;
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uint32_t X22;
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uint32_t X23;
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uint32_t X24;
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uint32_t X25;
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uint32_t X26;
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uint32_t X27;
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uint32_t X28;
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uint32_t X29;
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uint32_t X30;
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uint32_t X31;
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uint32_t PC;
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uint32_t NEXT_PC;
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uint32_t trap_state, pending_trap, machine_state;
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uint64_t icount;
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uint32_t X0 = 0;
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uint32_t X1 = 0;
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uint32_t X2 = 0;
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uint32_t X3 = 0;
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uint32_t X4 = 0;
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uint32_t X5 = 0;
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uint32_t X6 = 0;
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uint32_t X7 = 0;
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uint32_t X8 = 0;
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uint32_t X9 = 0;
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uint32_t X10 = 0;
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uint32_t X11 = 0;
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uint32_t X12 = 0;
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uint32_t X13 = 0;
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uint32_t X14 = 0;
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uint32_t X15 = 0;
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uint32_t X16 = 0;
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uint32_t X17 = 0;
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uint32_t X18 = 0;
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uint32_t X19 = 0;
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uint32_t X20 = 0;
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uint32_t X21 = 0;
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uint32_t X22 = 0;
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uint32_t X23 = 0;
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uint32_t X24 = 0;
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uint32_t X25 = 0;
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uint32_t X26 = 0;
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uint32_t X27 = 0;
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uint32_t X28 = 0;
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uint32_t X29 = 0;
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uint32_t X30 = 0;
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uint32_t X31 = 0;
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uint32_t PC = 0;
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uint32_t NEXT_PC = 0;
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uint32_t trap_state = 0, pending_trap = 0, machine_state = 0;
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uint64_t icount = 0;
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} reg;
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address_type addr_mode[4];
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uint64_t cycles = 0;
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};
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}
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@ -28,7 +28,7 @@
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// Created on: Fri Dec 15 14:41:58 CET 2017
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// Created on: Sat Dec 30 12:50:15 CET 2017
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// * rv64ia.h Author: <CoreDSL Generator>
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//
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////////////////////////////////////////////////////////////////////////////////
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@ -159,45 +159,48 @@ struct rv64ia: public arch_if {
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protected:
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struct RV64IA_regs {
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uint64_t X0;
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uint64_t X1;
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uint64_t X2;
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uint64_t X3;
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uint64_t X4;
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uint64_t X5;
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uint64_t X6;
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uint64_t X7;
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uint64_t X8;
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uint64_t X9;
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uint64_t X10;
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uint64_t X11;
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uint64_t X12;
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uint64_t X13;
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uint64_t X14;
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uint64_t X15;
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uint64_t X16;
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uint64_t X17;
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uint64_t X18;
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uint64_t X19;
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uint64_t X20;
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uint64_t X21;
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uint64_t X22;
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uint64_t X23;
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uint64_t X24;
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uint64_t X25;
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uint64_t X26;
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uint64_t X27;
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uint64_t X28;
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uint64_t X29;
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uint64_t X30;
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uint64_t X31;
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uint64_t PC;
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uint64_t NEXT_PC;
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uint32_t trap_state, pending_trap, machine_state;
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uint64_t icount;
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uint64_t X0 = 0;
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uint64_t X1 = 0;
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uint64_t X2 = 0;
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uint64_t X3 = 0;
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uint64_t X4 = 0;
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uint64_t X5 = 0;
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uint64_t X6 = 0;
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uint64_t X7 = 0;
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uint64_t X8 = 0;
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uint64_t X9 = 0;
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uint64_t X10 = 0;
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uint64_t X11 = 0;
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uint64_t X12 = 0;
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uint64_t X13 = 0;
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uint64_t X14 = 0;
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uint64_t X15 = 0;
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uint64_t X16 = 0;
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uint64_t X17 = 0;
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uint64_t X18 = 0;
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uint64_t X19 = 0;
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uint64_t X20 = 0;
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uint64_t X21 = 0;
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uint64_t X22 = 0;
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uint64_t X23 = 0;
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uint64_t X24 = 0;
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uint64_t X25 = 0;
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uint64_t X26 = 0;
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uint64_t X27 = 0;
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uint64_t X28 = 0;
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uint64_t X29 = 0;
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uint64_t X30 = 0;
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uint64_t X31 = 0;
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uint64_t PC = 0;
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uint64_t NEXT_PC = 0;
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uint32_t trap_state = 0, pending_trap = 0, machine_state = 0;
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uint64_t icount = 0;
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} reg;
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address_type addr_mode[4];
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uint64_t cycles = 0;
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};
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}
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