diff --git a/.gitignore b/.gitignore
index 2865d22..24b33d4 100644
--- a/.gitignore
+++ b/.gitignore
@@ -30,3 +30,4 @@ language.settings.xml
 /.gdbinit
 /*.out
 /dump.json
+/etc/
diff --git a/dbt-core b/dbt-core
index 4bfcd8a..4eb39e8 160000
--- a/dbt-core
+++ b/dbt-core
@@ -1 +1 @@
-Subproject commit 4bfcd8a10e81d610d46b329841ae3ba7cbc0627a
+Subproject commit 4eb39e8583e591b50c97051db7ac667c209459ab
diff --git a/riscv.sc/src/sc_main.cpp b/riscv.sc/src/sc_main.cpp
index 6a7230d..e01c9de 100644
--- a/riscv.sc/src/sc_main.cpp
+++ b/riscv.sc/src/sc_main.cpp
@@ -70,7 +70,6 @@ int sc_main(int argc, char *argv[]) {
             ("elf,l", po::value<std::string>(), "ELF file to load")
             ("gdb-port,g", po::value<unsigned short>()->default_value(0), "enable gdb server and specify port to use")
             ("dump-ir", "dump the intermediate representation")
-            ("cycles", po::value<int64_t>()->default_value(-1), "number of cycles to run")
             ("quantum", po::value<unsigned>(), "SystemC quantum time in ns")
             ("reset,r", po::value<std::string>(), "reset address")
             ("trace,t", po::value<unsigned>()->default_value(0), "enable tracing, or combintation of 1=signals and 2=TX text, 4=TX compressed text, 6=TX in SQLite")
diff --git a/riscv/incl/iss/arch/riscv_hart_msu_vp.h b/riscv/incl/iss/arch/riscv_hart_msu_vp.h
index 2e41781..74e86e6 100644
--- a/riscv/incl/iss/arch/riscv_hart_msu_vp.h
+++ b/riscv/incl/iss/arch/riscv_hart_msu_vp.h
@@ -811,17 +811,18 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_csr(unsigned
 }
 
 template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_cycle(unsigned addr, reg_t &val) {
+    auto cycle_val=this->cycles ? this->cycles : this->reg.icount;
     if (addr == mcycle) {
-        val = static_cast<reg_t>(this->reg.icount);
+        val = static_cast<reg_t>(cycle_val);
     } else if (addr == mcycleh) {
         if (sizeof(typename traits<BASE>::reg_t) != 4) return iss::Err;
-        val = static_cast<reg_t>((this->reg.icount) >> 32);
+        val = static_cast<reg_t>(cycle_val >> 32);
     }
     return iss::Ok;
 }
 
 template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_time(unsigned addr, reg_t &val) {
-	uint64_t time_val=this->reg.icount>>12;
+	uint64_t time_val=(this->cycles?this->cycles:this->reg.icount) / (100000000/32768-1); //-> ~3052;
     if (addr == time) {
         val = static_cast<reg_t>(time_val);
     } else if (addr == timeh) {
diff --git a/riscv/incl/iss/arch/rv32imac.h b/riscv/incl/iss/arch/rv32imac.h
index 7fbfb49..e87f6f2 100644
--- a/riscv/incl/iss/arch/rv32imac.h
+++ b/riscv/incl/iss/arch/rv32imac.h
@@ -28,7 +28,7 @@
 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 // POSSIBILITY OF SUCH DAMAGE.
 // 
-// Created on: Fri Dec 15 14:41:57 CET 2017
+// Created on: Sat Dec 30 12:50:15 CET 2017
 //             *      rv32imac.h Author: <CoreDSL Generator>
 //
 ////////////////////////////////////////////////////////////////////////////////
@@ -159,45 +159,48 @@ struct rv32imac: public arch_if {
 
 protected:
     struct RV32IMAC_regs {
-        uint32_t X0;
-        uint32_t X1;
-        uint32_t X2;
-        uint32_t X3;
-        uint32_t X4;
-        uint32_t X5;
-        uint32_t X6;
-        uint32_t X7;
-        uint32_t X8;
-        uint32_t X9;
-        uint32_t X10;
-        uint32_t X11;
-        uint32_t X12;
-        uint32_t X13;
-        uint32_t X14;
-        uint32_t X15;
-        uint32_t X16;
-        uint32_t X17;
-        uint32_t X18;
-        uint32_t X19;
-        uint32_t X20;
-        uint32_t X21;
-        uint32_t X22;
-        uint32_t X23;
-        uint32_t X24;
-        uint32_t X25;
-        uint32_t X26;
-        uint32_t X27;
-        uint32_t X28;
-        uint32_t X29;
-        uint32_t X30;
-        uint32_t X31;
-        uint32_t PC;
-        uint32_t NEXT_PC;
-        uint32_t trap_state, pending_trap, machine_state;
-        uint64_t icount;
+        uint32_t X0 = 0;
+        uint32_t X1 = 0;
+        uint32_t X2 = 0;
+        uint32_t X3 = 0;
+        uint32_t X4 = 0;
+        uint32_t X5 = 0;
+        uint32_t X6 = 0;
+        uint32_t X7 = 0;
+        uint32_t X8 = 0;
+        uint32_t X9 = 0;
+        uint32_t X10 = 0;
+        uint32_t X11 = 0;
+        uint32_t X12 = 0;
+        uint32_t X13 = 0;
+        uint32_t X14 = 0;
+        uint32_t X15 = 0;
+        uint32_t X16 = 0;
+        uint32_t X17 = 0;
+        uint32_t X18 = 0;
+        uint32_t X19 = 0;
+        uint32_t X20 = 0;
+        uint32_t X21 = 0;
+        uint32_t X22 = 0;
+        uint32_t X23 = 0;
+        uint32_t X24 = 0;
+        uint32_t X25 = 0;
+        uint32_t X26 = 0;
+        uint32_t X27 = 0;
+        uint32_t X28 = 0;
+        uint32_t X29 = 0;
+        uint32_t X30 = 0;
+        uint32_t X31 = 0;
+        uint32_t PC = 0;
+        uint32_t NEXT_PC = 0;
+        uint32_t trap_state = 0, pending_trap = 0, machine_state = 0;
+        uint64_t icount = 0;
     } reg;
 
     address_type addr_mode[4];
+
+    uint64_t cycles = 0;
+
 };
 
 }
diff --git a/riscv/incl/iss/arch/rv64ia.h b/riscv/incl/iss/arch/rv64ia.h
index 6f91112..580bb67 100644
--- a/riscv/incl/iss/arch/rv64ia.h
+++ b/riscv/incl/iss/arch/rv64ia.h
@@ -28,7 +28,7 @@
 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 // POSSIBILITY OF SUCH DAMAGE.
 // 
-// Created on: Fri Dec 15 14:41:58 CET 2017
+// Created on: Sat Dec 30 12:50:15 CET 2017
 //             *      rv64ia.h Author: <CoreDSL Generator>
 //
 ////////////////////////////////////////////////////////////////////////////////
@@ -159,45 +159,48 @@ struct rv64ia: public arch_if {
 
 protected:
     struct RV64IA_regs {
-        uint64_t X0;
-        uint64_t X1;
-        uint64_t X2;
-        uint64_t X3;
-        uint64_t X4;
-        uint64_t X5;
-        uint64_t X6;
-        uint64_t X7;
-        uint64_t X8;
-        uint64_t X9;
-        uint64_t X10;
-        uint64_t X11;
-        uint64_t X12;
-        uint64_t X13;
-        uint64_t X14;
-        uint64_t X15;
-        uint64_t X16;
-        uint64_t X17;
-        uint64_t X18;
-        uint64_t X19;
-        uint64_t X20;
-        uint64_t X21;
-        uint64_t X22;
-        uint64_t X23;
-        uint64_t X24;
-        uint64_t X25;
-        uint64_t X26;
-        uint64_t X27;
-        uint64_t X28;
-        uint64_t X29;
-        uint64_t X30;
-        uint64_t X31;
-        uint64_t PC;
-        uint64_t NEXT_PC;
-        uint32_t trap_state, pending_trap, machine_state;
-        uint64_t icount;
+        uint64_t X0 = 0;
+        uint64_t X1 = 0;
+        uint64_t X2 = 0;
+        uint64_t X3 = 0;
+        uint64_t X4 = 0;
+        uint64_t X5 = 0;
+        uint64_t X6 = 0;
+        uint64_t X7 = 0;
+        uint64_t X8 = 0;
+        uint64_t X9 = 0;
+        uint64_t X10 = 0;
+        uint64_t X11 = 0;
+        uint64_t X12 = 0;
+        uint64_t X13 = 0;
+        uint64_t X14 = 0;
+        uint64_t X15 = 0;
+        uint64_t X16 = 0;
+        uint64_t X17 = 0;
+        uint64_t X18 = 0;
+        uint64_t X19 = 0;
+        uint64_t X20 = 0;
+        uint64_t X21 = 0;
+        uint64_t X22 = 0;
+        uint64_t X23 = 0;
+        uint64_t X24 = 0;
+        uint64_t X25 = 0;
+        uint64_t X26 = 0;
+        uint64_t X27 = 0;
+        uint64_t X28 = 0;
+        uint64_t X29 = 0;
+        uint64_t X30 = 0;
+        uint64_t X31 = 0;
+        uint64_t PC = 0;
+        uint64_t NEXT_PC = 0;
+        uint32_t trap_state = 0, pending_trap = 0, machine_state = 0;
+        uint64_t icount = 0;
     } reg;
 
     address_type addr_mode[4];
+
+    uint64_t cycles = 0;
+    
 };
 
 }
diff --git a/riscv/src/internal/vm_riscv.in.cpp b/riscv/src/internal/vm_riscv.in.cpp
index 6598bd5..c1379da 100644
--- a/riscv/src/internal/vm_riscv.in.cpp
+++ b/riscv/src/internal/vm_riscv.in.cpp
@@ -186,17 +186,16 @@ private:
      ****************************************************************************/
     std::tuple<vm::continuation_e, llvm::BasicBlock *> illegal_intruction(virt_addr_t &pc, code_word_t instr,
                                                                           llvm::BasicBlock *bb) {
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, sizeof(instr_descr)/sizeof(InstructionDesriptor));
         this->builder.CreateStore(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), true),
                                    get_reg_ptr(traits<ARCH>::PC), true);
         this->builder.CreateStore(
             this->builder.CreateAdd(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::ICOUNT), true),
                                      this->gen_const(64U, 1)),
             get_reg_ptr(traits<ARCH>::ICOUNT), true);
-        if (this->debugging_enabled()) this->gen_sync(iss::PRE_SYNC);
         pc = pc + ((instr & 3) == 3 ? 4 : 2);
         this->gen_raise_trap(0, 2);     // illegal instruction trap
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, sizeof(instr_descr)/sizeof(InstructionDesriptor));
         this->gen_trap_check(this->leave_blk);
         return std::make_tuple(iss::vm::BRANCH, nullptr);
     }
@@ -227,8 +226,8 @@ std::tuple<vm::continuation_e, llvm::BasicBlock *>
 vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, llvm::BasicBlock *this_block) {
     // we fetch at max 4 byte, alignment is 2
     code_word_t insn = 0;
-    iss::addr_t paddr;
     const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
+    phys_addr_t paddr(pc);
     try {
         uint8_t *const data = (uint8_t *)&insn;
         paddr = this->core.v2p(pc);
diff --git a/riscv/src/internal/vm_rv32imac.cpp b/riscv/src/internal/vm_rv32imac.cpp
index 7014917..e06efba 100644
--- a/riscv/src/internal/vm_rv32imac.cpp
+++ b/riscv/src/internal/vm_rv32imac.cpp
@@ -380,11 +380,11 @@ private:
         /* instruction DII */
         {16, 0b0000000000000000, 0b1111111111111111, &this_class::__dii},
     };
-    // instruction LUI
+    //0: instruction LUI
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __lui(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("LUI");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 0);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         int32_t fld_imm_val = 0 | (signed_bit_sub<12,20>(instr) << 12);
@@ -406,17 +406,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 0);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction AUIPC
+    //1: instruction AUIPC
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __auipc(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("AUIPC");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 1);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         int32_t fld_imm_val = 0 | (signed_bit_sub<12,20>(instr) << 12);
@@ -440,17 +440,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 1);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction JAL
+    //2: instruction JAL
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __jal(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("JAL");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 2);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         int32_t fld_imm_val = 0 | (bit_sub<12,8>(instr) << 12) | (bit_sub<20,1>(instr) << 11) | (bit_sub<21,10>(instr) << 1) | (signed_bit_sub<31,1>(instr) << 20);
@@ -477,16 +477,16 @@ private:
             this->gen_reg_load(traits<ARCH>::PC, 0),
             this->gen_const(32U, fld_imm_val));
         this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 2);
         this->gen_trap_check(this->leave_blk);
         return std::make_tuple(iss::vm::BRANCH, nullptr);
     }
     
-    // instruction JALR
+    //3: instruction JALR
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __jalr(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("JALR");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 3);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -517,16 +517,16 @@ private:
             ret_val,
             this->builder.CreateNot(this->gen_const(32U, 1)));
         this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 3);
         this->gen_trap_check(this->leave_blk);
         return std::make_tuple(iss::vm::BRANCH, nullptr);
     }
     
-    // instruction BEQ
+    //4: instruction BEQ
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __beq(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("BEQ");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 4);
     
         int16_t fld_imm_val = 0 | (bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (signed_bit_sub<31,1>(instr) << 12);
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -557,16 +557,16 @@ private:
                 this->gen_const(32U, 4)),
             32);
         this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 4);
         this->gen_trap_check(this->leave_blk);
         return std::make_tuple(iss::vm::BRANCH, nullptr);
     }
     
-    // instruction BNE
+    //5: instruction BNE
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __bne(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("BNE");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 5);
     
         int16_t fld_imm_val = 0 | (bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (signed_bit_sub<31,1>(instr) << 12);
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -597,16 +597,16 @@ private:
                 this->gen_const(32U, 4)),
             32);
         this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 5);
         this->gen_trap_check(this->leave_blk);
         return std::make_tuple(iss::vm::BRANCH, nullptr);
     }
     
-    // instruction BLT
+    //6: instruction BLT
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __blt(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("BLT");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 6);
     
         int16_t fld_imm_val = 0 | (bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (signed_bit_sub<31,1>(instr) << 12);
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -641,16 +641,16 @@ private:
                 this->gen_const(32U, 4)),
             32);
         this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 6);
         this->gen_trap_check(this->leave_blk);
         return std::make_tuple(iss::vm::BRANCH, nullptr);
     }
     
-    // instruction BGE
+    //7: instruction BGE
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __bge(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("BGE");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 7);
     
         int16_t fld_imm_val = 0 | (bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (signed_bit_sub<31,1>(instr) << 12);
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -685,16 +685,16 @@ private:
                 this->gen_const(32U, 4)),
             32);
         this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 7);
         this->gen_trap_check(this->leave_blk);
         return std::make_tuple(iss::vm::BRANCH, nullptr);
     }
     
-    // instruction BLTU
+    //8: instruction BLTU
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __bltu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("BLTU");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 8);
     
         int16_t fld_imm_val = 0 | (bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (signed_bit_sub<31,1>(instr) << 12);
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -725,16 +725,16 @@ private:
                 this->gen_const(32U, 4)),
             32);
         this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 8);
         this->gen_trap_check(this->leave_blk);
         return std::make_tuple(iss::vm::BRANCH, nullptr);
     }
     
-    // instruction BGEU
+    //9: instruction BGEU
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __bgeu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("BGEU");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 9);
     
         int16_t fld_imm_val = 0 | (bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (signed_bit_sub<31,1>(instr) << 12);
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -765,16 +765,16 @@ private:
                 this->gen_const(32U, 4)),
             32);
         this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 9);
         this->gen_trap_check(this->leave_blk);
         return std::make_tuple(iss::vm::BRANCH, nullptr);
     }
     
-    // instruction LB
+    //10: instruction LB
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __lb(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("LB");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 10);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -803,17 +803,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 10);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction LH
+    //11: instruction LH
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __lh(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("LH");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 11);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -842,17 +842,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 11);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction LW
+    //12: instruction LW
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __lw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("LW");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 12);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -881,17 +881,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 12);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction LBU
+    //13: instruction LBU
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __lbu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("LBU");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 13);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -920,17 +920,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 13);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction LHU
+    //14: instruction LHU
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __lhu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("LHU");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 14);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -959,17 +959,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 14);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction SB
+    //15: instruction SB
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __sb(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("SB");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 15);
     
         int16_t fld_imm_val = 0 | (bit_sub<7,5>(instr)) | (signed_bit_sub<25,7>(instr) << 5);
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -996,17 +996,17 @@ private:
             offs_val,
             this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(8)));
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 15);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction SH
+    //16: instruction SH
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __sh(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("SH");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 16);
     
         int16_t fld_imm_val = 0 | (bit_sub<7,5>(instr)) | (signed_bit_sub<25,7>(instr) << 5);
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -1033,17 +1033,17 @@ private:
             offs_val,
             this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(16)));
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 16);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction SW
+    //17: instruction SW
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __sw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("SW");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 17);
     
         int16_t fld_imm_val = 0 | (bit_sub<7,5>(instr)) | (signed_bit_sub<25,7>(instr) << 5);
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -1070,17 +1070,17 @@ private:
             offs_val,
             this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32)));
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 17);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction ADDI
+    //18: instruction ADDI
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __addi(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("ADDI");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 18);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -1105,17 +1105,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 18);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction SLTI
+    //19: instruction SLTI
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __slti(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("SLTI");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 19);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -1149,17 +1149,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 19);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction SLTIU
+    //20: instruction SLTIU
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __sltiu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("SLTIU");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 20);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -1194,17 +1194,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 20);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction XORI
+    //21: instruction XORI
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __xori(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("XORI");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 21);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -1229,17 +1229,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 21);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction ORI
+    //22: instruction ORI
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __ori(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("ORI");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 22);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -1264,17 +1264,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 22);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction ANDI
+    //23: instruction ANDI
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __andi(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("ANDI");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 23);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -1299,17 +1299,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 23);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction SLLI
+    //24: instruction SLLI
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __slli(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("SLLI");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 24);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -1338,17 +1338,17 @@ private:
             }
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 24);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction SRLI
+    //25: instruction SRLI
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __srli(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("SRLI");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 25);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -1377,17 +1377,17 @@ private:
             }
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 25);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction SRAI
+    //26: instruction SRAI
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __srai(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("SRAI");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 26);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -1416,17 +1416,17 @@ private:
             }
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 26);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction ADD
+    //27: instruction ADD
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __add(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("ADD");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 27);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -1451,17 +1451,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 27);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction SUB
+    //28: instruction SUB
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __sub(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("SUB");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 28);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -1486,17 +1486,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 28);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction SLL
+    //29: instruction SLL
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __sll(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("SLL");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 29);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -1523,17 +1523,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 29);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction SLT
+    //30: instruction SLT
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __slt(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("SLT");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 30);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -1567,17 +1567,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 30);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction SLTU
+    //31: instruction SLTU
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __sltu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("SLTU");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 31);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -1613,17 +1613,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 31);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction XOR
+    //32: instruction XOR
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __xor(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("XOR");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 32);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -1648,17 +1648,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 32);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction SRL
+    //33: instruction SRL
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __srl(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("SRL");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 33);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -1685,17 +1685,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 33);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction SRA
+    //34: instruction SRA
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __sra(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("SRA");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 34);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -1722,17 +1722,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 34);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction OR
+    //35: instruction OR
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __or(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("OR");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 35);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -1757,17 +1757,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 35);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction AND
+    //36: instruction AND
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __and(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("AND");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 36);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -1792,17 +1792,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 36);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction FENCE
+    //37: instruction FENCE
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __fence(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("FENCE");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 37);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -1829,17 +1829,17 @@ private:
             (uint64_t)0,
             this->builder.CreateZExtOrTrunc(FENCE_fence_val,this->get_type(32)));
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 37);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction FENCE_I
+    //38: instruction FENCE_I
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __fence_i(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("FENCE_I");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 38);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -1861,16 +1861,16 @@ private:
             (uint64_t)1,
             this->builder.CreateZExtOrTrunc(FENCE_fencei_val,this->get_type(32)));
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 38);
         this->gen_trap_check(this->leave_blk);
         return std::make_tuple(iss::vm::FLUSH, nullptr);
     }
     
-    // instruction ECALL
+    //39: instruction ECALL
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __ecall(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("ECALL");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 39);
     
         ;
         if(this->disass_enabled){
@@ -1885,16 +1885,16 @@ private:
         pc=pc+4;
     
         this->gen_raise_trap(0, 11);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 39);
         this->gen_trap_check(this->leave_blk);
         return std::make_tuple(iss::vm::BRANCH, nullptr);
     }
     
-    // instruction EBREAK
+    //40: instruction EBREAK
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __ebreak(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("EBREAK");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 40);
     
         ;
         if(this->disass_enabled){
@@ -1909,16 +1909,16 @@ private:
         pc=pc+4;
     
         this->gen_raise_trap(0, 3);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 40);
         this->gen_trap_check(this->leave_blk);
         return std::make_tuple(iss::vm::BRANCH, nullptr);
     }
     
-    // instruction URET
+    //41: instruction URET
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __uret(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("URET");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 41);
     
         ;
         if(this->disass_enabled){
@@ -1933,16 +1933,16 @@ private:
         pc=pc+4;
     
         this->gen_leave_trap(0);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 41);
         this->gen_trap_check(this->leave_blk);
         return std::make_tuple(iss::vm::BRANCH, nullptr);
     }
     
-    // instruction SRET
+    //42: instruction SRET
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __sret(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("SRET");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 42);
     
         ;
         if(this->disass_enabled){
@@ -1957,16 +1957,16 @@ private:
         pc=pc+4;
     
         this->gen_leave_trap(1);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 42);
         this->gen_trap_check(this->leave_blk);
         return std::make_tuple(iss::vm::BRANCH, nullptr);
     }
     
-    // instruction MRET
+    //43: instruction MRET
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __mret(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("MRET");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 43);
     
         ;
         if(this->disass_enabled){
@@ -1981,16 +1981,16 @@ private:
         pc=pc+4;
     
         this->gen_leave_trap(3);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 43);
         this->gen_trap_check(this->leave_blk);
         return std::make_tuple(iss::vm::BRANCH, nullptr);
     }
     
-    // instruction WFI
+    //44: instruction WFI
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __wfi(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("WFI");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 44);
     
         ;
         if(this->disass_enabled){
@@ -2006,17 +2006,17 @@ private:
     
         this->gen_wait(1);
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 44);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction SFENCE.VMA
+    //45: instruction SFENCE.VMA
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __sfence_vma(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("SFENCE.VMA");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 45);
     
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
         uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
@@ -2042,17 +2042,17 @@ private:
             (uint64_t)3,
             this->builder.CreateZExtOrTrunc(FENCE_fencevmau_val,this->get_type(32)));
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 45);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction CSRRW
+    //46: instruction CSRRW
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __csrrw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("CSRRW");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 46);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -2088,17 +2088,17 @@ private:
                 this->builder.CreateZExtOrTrunc(CSR_csr_val,this->get_type(32)));
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 46);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction CSRRS
+    //47: instruction CSRRS
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __csrrs(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("CSRRS");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 47);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -2132,17 +2132,17 @@ private:
                 this->builder.CreateZExtOrTrunc(CSR_csr_val,this->get_type(32)));
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 47);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction CSRRC
+    //48: instruction CSRRC
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __csrrc(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("CSRRC");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 48);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -2176,17 +2176,17 @@ private:
                 this->builder.CreateZExtOrTrunc(CSR_csr_val,this->get_type(32)));
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 48);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction CSRRWI
+    //49: instruction CSRRWI
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __csrrwi(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("CSRRWI");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 49);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_zimm_val = 0 | (bit_sub<15,5>(instr));
@@ -2217,17 +2217,17 @@ private:
             fld_csr_val,
             this->builder.CreateZExtOrTrunc(CSR_csr_val,this->get_type(32)));
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 49);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction CSRRSI
+    //50: instruction CSRRSI
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __csrrsi(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("CSRRSI");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 50);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_zimm_val = 0 | (bit_sub<15,5>(instr));
@@ -2263,17 +2263,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 50);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction CSRRCI
+    //51: instruction CSRRCI
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __csrrci(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("CSRRCI");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 51);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_zimm_val = 0 | (bit_sub<15,5>(instr));
@@ -2309,17 +2309,17 @@ private:
                 this->builder.CreateZExtOrTrunc(CSR_csr_val,this->get_type(32)));
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 51);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction MUL
+    //52: instruction MUL
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __mul(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("MUL");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 52);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -2354,17 +2354,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 52);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction MULH
+    //53: instruction MULH
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __mulh(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("MULH");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 53);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -2401,17 +2401,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 53);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction MULHSU
+    //54: instruction MULHSU
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __mulhsu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("MULHSU");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 54);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -2448,17 +2448,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 54);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction MULHU
+    //55: instruction MULHU
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __mulhu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("MULHU");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 55);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -2495,17 +2495,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 55);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction DIV
+    //56: instruction DIV
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __div(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("DIV");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 56);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -2558,17 +2558,17 @@ private:
             this->builder.SetInsertPoint(bb);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 56);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction DIVU
+    //57: instruction DIVU
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __divu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("DIVU");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 57);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -2621,17 +2621,17 @@ private:
             this->builder.SetInsertPoint(bb);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 57);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction REM
+    //58: instruction REM
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __rem(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("REM");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 58);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -2684,17 +2684,17 @@ private:
             this->builder.SetInsertPoint(bb);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 58);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction REMU
+    //59: instruction REMU
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __remu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("REMU");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 59);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -2747,17 +2747,17 @@ private:
             this->builder.SetInsertPoint(bb);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 59);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction LR.W
+    //60: instruction LR.W
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __lr_w(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("LR.W");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 60);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -2793,17 +2793,17 @@ private:
                 this->builder.CreateZExtOrTrunc(RES_offs_val,this->get_type(32)));
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 60);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction SC.W
+    //61: instruction SC.W
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __sc_w(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("SC.W");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 61);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -2857,17 +2857,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 61);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction AMOSWAP.W
+    //62: instruction AMOSWAP.W
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __amoswap_w(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("AMOSWAP.W");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 62);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -2901,17 +2901,17 @@ private:
             offs_val,
             this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32)));
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 62);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction AMOADD.W
+    //63: instruction AMOADD.W
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __amoadd_w(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("AMOADD.W");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 63);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -2949,17 +2949,17 @@ private:
             offs_val,
             this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32)));
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 63);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction AMOXOR.W
+    //64: instruction AMOXOR.W
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __amoxor_w(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("AMOXOR.W");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 64);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -2997,17 +2997,17 @@ private:
             offs_val,
             this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32)));
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 64);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction AMOAND.W
+    //65: instruction AMOAND.W
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __amoand_w(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("AMOAND.W");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 65);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -3045,17 +3045,17 @@ private:
             offs_val,
             this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32)));
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 65);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction AMOOR.W
+    //66: instruction AMOOR.W
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __amoor_w(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("AMOOR.W");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 66);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -3093,17 +3093,17 @@ private:
             offs_val,
             this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32)));
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 66);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction AMOMIN.W
+    //67: instruction AMOMIN.W
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __amomin_w(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("AMOMIN.W");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 67);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -3150,17 +3150,17 @@ private:
             offs_val,
             this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32)));
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 67);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction AMOMAX.W
+    //68: instruction AMOMAX.W
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __amomax_w(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("AMOMAX.W");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 68);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -3207,17 +3207,17 @@ private:
             offs_val,
             this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32)));
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 68);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction AMOMINU.W
+    //69: instruction AMOMINU.W
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __amominu_w(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("AMOMINU.W");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 69);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -3260,17 +3260,17 @@ private:
             offs_val,
             this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32)));
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 69);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction AMOMAXU.W
+    //70: instruction AMOMAXU.W
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __amomaxu_w(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("AMOMAXU.W");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 70);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -3317,17 +3317,17 @@ private:
             offs_val,
             this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32)));
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 70);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction C.ADDI4SPN
+    //71: instruction C.ADDI4SPN
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __c_addi4spn(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("C.ADDI4SPN");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 71);
     
         uint8_t fld_rd_val = 0 | (bit_sub<2,3>(instr));
         uint16_t fld_imm_val = 0 | (bit_sub<5,1>(instr) << 3) | (bit_sub<6,1>(instr) << 2) | (bit_sub<7,4>(instr) << 6) | (bit_sub<11,2>(instr) << 4);
@@ -3354,17 +3354,17 @@ private:
             this->gen_const(32U, fld_imm_val));
         this->builder.CreateStore(X_rd_idx_val, get_reg_ptr(rd_idx_val), false);
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 71);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction C.LW
+    //72: instruction C.LW
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __c_lw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("C.LW");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 72);
     
         uint8_t fld_rd_val = 0 | (bit_sub<2,3>(instr));
         uint8_t fld_uimm_val = 0 | (bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3);
@@ -3390,17 +3390,17 @@ private:
         Value* X_rd_idx_val = this->gen_read_mem(traits<ARCH>::MEM, offs_val, 32/8);
         this->builder.CreateStore(X_rd_idx_val, get_reg_ptr(rd_idx_val), false);
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 72);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction C.SW
+    //73: instruction C.SW
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __c_sw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("C.SW");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 73);
     
         uint8_t fld_rs2_val = 0 | (bit_sub<2,3>(instr));
         uint8_t fld_uimm_val = 0 | (bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3);
@@ -3429,17 +3429,17 @@ private:
             offs_val,
             this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32)));
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 73);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction C.ADDI
+    //74: instruction C.ADDI
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __c_addi(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("C.ADDI");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 74);
     
         int8_t fld_imm_val = 0 | (bit_sub<2,5>(instr)) | (signed_bit_sub<12,1>(instr) << 5);
         uint8_t fld_rs1_val = 0 | (bit_sub<7,5>(instr));
@@ -3461,17 +3461,17 @@ private:
             this->gen_const(32U, fld_imm_val));
         this->builder.CreateStore(X_rs1_val, get_reg_ptr(fld_rs1_val), false);
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 74);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction C.NOP
+    //75: instruction C.NOP
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __c_nop(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("C.NOP");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 75);
     
         ;
         if(this->disass_enabled){
@@ -3487,17 +3487,17 @@ private:
     
         /* TODO: describe operations for C.NOP ! */
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 75);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction C.JAL
+    //76: instruction C.JAL
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __c_jal(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("C.JAL");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 76);
     
         int16_t fld_imm_val = 0 | (bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (signed_bit_sub<12,1>(instr) << 11);
         if(this->disass_enabled){
@@ -3522,16 +3522,16 @@ private:
             this->gen_reg_load(traits<ARCH>::PC, 0),
             this->gen_const(32U, fld_imm_val));
         this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 76);
         this->gen_trap_check(this->leave_blk);
         return std::make_tuple(iss::vm::BRANCH, nullptr);
     }
     
-    // instruction C.LI
+    //77: instruction C.LI
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __c_li(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("C.LI");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 77);
     
         int8_t fld_imm_val = 0 | (bit_sub<2,5>(instr)) | (signed_bit_sub<12,1>(instr) << 5);
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
@@ -3554,17 +3554,17 @@ private:
         Value* X_rd_val = this->gen_const(32U, fld_imm_val);
         this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 77);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction C.LUI
+    //78: instruction C.LUI
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __c_lui(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("C.LUI");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 78);
     
         int32_t fld_imm_val = 0 | (bit_sub<2,5>(instr) << 12) | (signed_bit_sub<12,1>(instr) << 17);
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
@@ -3590,17 +3590,17 @@ private:
         Value* X_rd_val = this->gen_const(32U, fld_imm_val);
         this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 78);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction C.ADDI16SP
+    //79: instruction C.ADDI16SP
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __c_addi16sp(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("C.ADDI16SP");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 79);
     
         int16_t fld_imm_val = 0 | (bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 7) | (bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 4) | (signed_bit_sub<12,1>(instr) << 9);
         if(this->disass_enabled){
@@ -3624,17 +3624,17 @@ private:
             this->gen_const(32U, fld_imm_val));
         this->builder.CreateStore(X_x2_idx_val, get_reg_ptr(x2_idx_val), false);
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 79);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction C.SRLI
+    //80: instruction C.SRLI
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __c_srli(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("C.SRLI");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 80);
     
         uint8_t fld_shamt_val = 0 | (bit_sub<2,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<7,3>(instr));
@@ -3657,17 +3657,17 @@ private:
             this->gen_const(32U, fld_shamt_val));
         this->builder.CreateStore(X_rs1_idx_val, get_reg_ptr(rs1_idx_val), false);
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 80);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction C.SRAI
+    //81: instruction C.SRAI
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __c_srai(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("C.SRAI");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 81);
     
         uint8_t fld_shamt_val = 0 | (bit_sub<2,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<7,3>(instr));
@@ -3690,17 +3690,17 @@ private:
             this->gen_const(32U, fld_shamt_val));
         this->builder.CreateStore(X_rs1_idx_val, get_reg_ptr(rs1_idx_val), false);
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 81);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction C.ANDI
+    //82: instruction C.ANDI
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __c_andi(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("C.ANDI");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 82);
     
         int8_t fld_imm_val = 0 | (bit_sub<2,5>(instr)) | (signed_bit_sub<12,1>(instr) << 5);
         uint8_t fld_rs1_val = 0 | (bit_sub<7,3>(instr));
@@ -3723,17 +3723,17 @@ private:
             this->gen_const(32U, fld_imm_val));
         this->builder.CreateStore(X_rs1_idx_val, get_reg_ptr(rs1_idx_val), false);
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 82);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction C.SUB
+    //83: instruction C.SUB
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __c_sub(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("C.SUB");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 83);
     
         uint8_t fld_rs2_val = 0 | (bit_sub<2,3>(instr));
         uint8_t fld_rd_val = 0 | (bit_sub<7,3>(instr));
@@ -3757,17 +3757,17 @@ private:
             this->gen_reg_load(rs2_idx_val, 0));
         this->builder.CreateStore(X_rd_idx_val, get_reg_ptr(rd_idx_val), false);
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 83);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction C.XOR
+    //84: instruction C.XOR
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __c_xor(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("C.XOR");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 84);
     
         uint8_t fld_rs2_val = 0 | (bit_sub<2,3>(instr));
         uint8_t fld_rd_val = 0 | (bit_sub<7,3>(instr));
@@ -3791,17 +3791,17 @@ private:
             this->gen_reg_load(rs2_idx_val, 0));
         this->builder.CreateStore(X_rd_idx_val, get_reg_ptr(rd_idx_val), false);
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 84);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction C.OR
+    //85: instruction C.OR
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __c_or(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("C.OR");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 85);
     
         uint8_t fld_rs2_val = 0 | (bit_sub<2,3>(instr));
         uint8_t fld_rd_val = 0 | (bit_sub<7,3>(instr));
@@ -3825,17 +3825,17 @@ private:
             this->gen_reg_load(rs2_idx_val, 0));
         this->builder.CreateStore(X_rd_idx_val, get_reg_ptr(rd_idx_val), false);
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 85);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction C.AND
+    //86: instruction C.AND
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __c_and(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("C.AND");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 86);
     
         uint8_t fld_rs2_val = 0 | (bit_sub<2,3>(instr));
         uint8_t fld_rd_val = 0 | (bit_sub<7,3>(instr));
@@ -3859,17 +3859,17 @@ private:
             this->gen_reg_load(rs2_idx_val, 0));
         this->builder.CreateStore(X_rd_idx_val, get_reg_ptr(rd_idx_val), false);
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 86);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction C.J
+    //87: instruction C.J
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __c_j(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("C.J");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 87);
     
         int16_t fld_imm_val = 0 | (bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (signed_bit_sub<12,1>(instr) << 11);
         if(this->disass_enabled){
@@ -3889,16 +3889,16 @@ private:
             this->gen_reg_load(traits<ARCH>::PC, 0),
             this->gen_const(32U, fld_imm_val));
         this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 87);
         this->gen_trap_check(this->leave_blk);
         return std::make_tuple(iss::vm::BRANCH, nullptr);
     }
     
-    // instruction C.BEQZ
+    //88: instruction C.BEQZ
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __c_beqz(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("C.BEQZ");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 88);
     
         int16_t fld_imm_val = 0 | (bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (signed_bit_sub<12,1>(instr) << 8);
         uint8_t fld_rs1_val = 0 | (bit_sub<7,3>(instr));
@@ -3929,16 +3929,16 @@ private:
                 this->gen_const(32U, 2)),
             32);
         this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 88);
         this->gen_trap_check(this->leave_blk);
         return std::make_tuple(iss::vm::BRANCH, nullptr);
     }
     
-    // instruction C.BNEZ
+    //89: instruction C.BNEZ
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __c_bnez(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("C.BNEZ");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 89);
     
         int16_t fld_imm_val = 0 | (bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (signed_bit_sub<12,1>(instr) << 8);
         uint8_t fld_rs1_val = 0 | (bit_sub<7,3>(instr));
@@ -3969,16 +3969,16 @@ private:
                 this->gen_const(32U, 2)),
             32);
         this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 89);
         this->gen_trap_check(this->leave_blk);
         return std::make_tuple(iss::vm::BRANCH, nullptr);
     }
     
-    // instruction C.SLLI
+    //90: instruction C.SLLI
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __c_slli(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("C.SLLI");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 90);
     
         uint8_t fld_shamt_val = 0 | (bit_sub<2,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<7,5>(instr));
@@ -4003,17 +4003,17 @@ private:
             this->gen_const(32U, fld_shamt_val));
         this->builder.CreateStore(X_rs1_val, get_reg_ptr(fld_rs1_val), false);
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 90);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction C.LWSP
+    //91: instruction C.LWSP
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __c_lwsp(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("C.LWSP");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 91);
     
         uint8_t fld_uimm_val = 0 | (bit_sub<2,2>(instr) << 6) | (bit_sub<4,3>(instr) << 2) | (bit_sub<12,1>(instr) << 5);
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
@@ -4037,17 +4037,17 @@ private:
         Value* X_rd_val = this->gen_read_mem(traits<ARCH>::MEM, offs_val, 32/8);
         this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 91);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction C.MV
+    //92: instruction C.MV
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __c_mv(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("C.MV");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 92);
     
         uint8_t fld_rs2_val = 0 | (bit_sub<2,5>(instr));
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
@@ -4067,17 +4067,17 @@ private:
         Value* X_rd_val = this->gen_reg_load(fld_rs2_val, 0);
         this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 92);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction C.JR
+    //93: instruction C.JR
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __c_jr(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("C.JR");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 93);
     
         uint8_t fld_rs1_val = 0 | (bit_sub<7,5>(instr));
         if(this->disass_enabled){
@@ -4095,16 +4095,16 @@ private:
     
         Value* PC_val = this->gen_reg_load(fld_rs1_val, 0);
         this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 93);
         this->gen_trap_check(this->leave_blk);
         return std::make_tuple(iss::vm::BRANCH, nullptr);
     }
     
-    // instruction C.ADD
+    //94: instruction C.ADD
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __c_add(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("C.ADD");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 94);
     
         uint8_t fld_rs2_val = 0 | (bit_sub<2,5>(instr));
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
@@ -4126,17 +4126,17 @@ private:
             this->gen_reg_load(fld_rs2_val, 0));
         this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 94);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction C.JALR
+    //95: instruction C.JALR
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __c_jalr(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("C.JALR");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 95);
     
         uint8_t fld_rs1_val = 0 | (bit_sub<7,5>(instr));
         if(this->disass_enabled){
@@ -4159,16 +4159,16 @@ private:
         this->builder.CreateStore(X_r_idx_val, get_reg_ptr(r_idx_val), false);
         Value* PC_val = this->gen_reg_load(fld_rs1_val, 0);
         this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 95);
         this->gen_trap_check(this->leave_blk);
         return std::make_tuple(iss::vm::BRANCH, nullptr);
     }
     
-    // instruction C.EBREAK
+    //96: instruction C.EBREAK
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __c_ebreak(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("C.EBREAK");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 96);
     
         ;
         if(this->disass_enabled){
@@ -4183,16 +4183,16 @@ private:
         pc=pc+2;
     
         this->gen_raise_trap(0, 3);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 96);
         this->gen_trap_check(this->leave_blk);
         return std::make_tuple(iss::vm::BRANCH, nullptr);
     }
     
-    // instruction C.SWSP
+    //97: instruction C.SWSP
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __c_swsp(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("C.SWSP");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 97);
     
         uint8_t fld_rs2_val = 0 | (bit_sub<2,5>(instr));
         uint8_t fld_uimm_val = 0 | (bit_sub<7,2>(instr) << 6) | (bit_sub<9,4>(instr) << 2);
@@ -4219,17 +4219,17 @@ private:
             offs_val,
             this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32)));
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 97);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction DII
+    //98: instruction DII
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __dii(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("DII");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 98);
     
         ;
         if(this->disass_enabled){
@@ -4245,7 +4245,7 @@ private:
     
         this->gen_raise_trap(0, 2);
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 98);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
@@ -4257,17 +4257,16 @@ private:
      ****************************************************************************/
     std::tuple<vm::continuation_e, llvm::BasicBlock *> illegal_intruction(virt_addr_t &pc, code_word_t instr,
                                                                           llvm::BasicBlock *bb) {
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, sizeof(instr_descr)/sizeof(InstructionDesriptor));
         this->builder.CreateStore(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), true),
                                    get_reg_ptr(traits<ARCH>::PC), true);
         this->builder.CreateStore(
             this->builder.CreateAdd(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::ICOUNT), true),
                                      this->gen_const(64U, 1)),
             get_reg_ptr(traits<ARCH>::ICOUNT), true);
-        if (this->debugging_enabled()) this->gen_sync(iss::PRE_SYNC);
         pc = pc + ((instr & 3) == 3 ? 4 : 2);
         this->gen_raise_trap(0, 2);     // illegal instruction trap
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, sizeof(instr_descr)/sizeof(InstructionDesriptor));
         this->gen_trap_check(this->leave_blk);
         return std::make_tuple(iss::vm::BRANCH, nullptr);
     }
diff --git a/riscv/src/internal/vm_rv64ia.cpp b/riscv/src/internal/vm_rv64ia.cpp
index 8af1940..ffdfbad 100644
--- a/riscv/src/internal/vm_rv64ia.cpp
+++ b/riscv/src/internal/vm_rv64ia.cpp
@@ -354,11 +354,11 @@ private:
         /* instruction AMOMAXU.W */
         {32, 0b11100000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amomaxu_w},
     };
-    // instruction LWU
+    //0: instruction LWU
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __lwu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("LWU");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 0);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -387,17 +387,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 0);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction LD
+    //1: instruction LD
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __ld(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("LD");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 1);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -426,17 +426,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 1);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction SD
+    //2: instruction SD
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __sd(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("SD");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 2);
     
         int16_t fld_imm_val = 0 | (bit_sub<7,5>(instr)) | (signed_bit_sub<25,7>(instr) << 5);
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -463,17 +463,17 @@ private:
             offs_val,
             this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(64)));
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 2);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction SLLI
+    //3: instruction SLLI
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __slli(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("SLLI");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 3);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -502,17 +502,17 @@ private:
             }
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 3);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction SRLI
+    //4: instruction SRLI
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __srli(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("SRLI");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 4);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -541,17 +541,17 @@ private:
             }
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 4);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction SRAI
+    //5: instruction SRAI
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __srai(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("SRAI");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 5);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -580,17 +580,17 @@ private:
             }
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 5);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction ADDIW
+    //6: instruction ADDIW
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __addiw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("ADDIW");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 6);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -622,17 +622,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 6);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction SLLIW
+    //7: instruction SLLIW
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __slliw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("SLLIW");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 7);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -664,17 +664,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 7);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction SRLIW
+    //8: instruction SRLIW
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __srliw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("SRLIW");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 8);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -706,17 +706,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 8);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction SRAIW
+    //9: instruction SRAIW
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __sraiw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("SRAIW");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 9);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -748,17 +748,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 9);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction ADDW
+    //10: instruction ADDW
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __addw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("ADDW");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 10);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -791,17 +791,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 10);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction SUBW
+    //11: instruction SUBW
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __subw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("SUBW");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 11);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -834,17 +834,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 11);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction SLLW
+    //12: instruction SLLW
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __sllw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("SLLW");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 12);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -883,17 +883,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 12);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction SRLW
+    //13: instruction SRLW
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __srlw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("SRLW");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 13);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -932,17 +932,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 13);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction SRAW
+    //14: instruction SRAW
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __sraw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("SRAW");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 14);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -981,17 +981,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 14);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction LUI
+    //15: instruction LUI
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __lui(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("LUI");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 15);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         int32_t fld_imm_val = 0 | (signed_bit_sub<12,20>(instr) << 12);
@@ -1013,17 +1013,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 15);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction AUIPC
+    //16: instruction AUIPC
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __auipc(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("AUIPC");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 16);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         int32_t fld_imm_val = 0 | (signed_bit_sub<12,20>(instr) << 12);
@@ -1047,17 +1047,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 16);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction JAL
+    //17: instruction JAL
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __jal(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("JAL");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 17);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         int32_t fld_imm_val = 0 | (bit_sub<12,8>(instr) << 12) | (bit_sub<20,1>(instr) << 11) | (bit_sub<21,10>(instr) << 1) | (signed_bit_sub<31,1>(instr) << 20);
@@ -1084,16 +1084,16 @@ private:
             this->gen_reg_load(traits<ARCH>::PC, 0),
             this->gen_const(64U, fld_imm_val));
         this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 17);
         this->gen_trap_check(this->leave_blk);
         return std::make_tuple(iss::vm::BRANCH, nullptr);
     }
     
-    // instruction JALR
+    //18: instruction JALR
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __jalr(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("JALR");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 18);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -1148,16 +1148,16 @@ private:
         this->builder.CreateBr(bbnext);
         bb=bbnext;
         this->builder.SetInsertPoint(bb);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 18);
         this->gen_trap_check(this->leave_blk);
         return std::make_tuple(iss::vm::BRANCH, nullptr);
     }
     
-    // instruction BEQ
+    //19: instruction BEQ
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __beq(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("BEQ");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 19);
     
         int16_t fld_imm_val = 0 | (bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (signed_bit_sub<31,1>(instr) << 12);
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -1188,16 +1188,16 @@ private:
                 this->gen_const(64U, 4)),
             64);
         this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 19);
         this->gen_trap_check(this->leave_blk);
         return std::make_tuple(iss::vm::BRANCH, nullptr);
     }
     
-    // instruction BNE
+    //20: instruction BNE
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __bne(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("BNE");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 20);
     
         int16_t fld_imm_val = 0 | (bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (signed_bit_sub<31,1>(instr) << 12);
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -1228,16 +1228,16 @@ private:
                 this->gen_const(64U, 4)),
             64);
         this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 20);
         this->gen_trap_check(this->leave_blk);
         return std::make_tuple(iss::vm::BRANCH, nullptr);
     }
     
-    // instruction BLT
+    //21: instruction BLT
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __blt(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("BLT");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 21);
     
         int16_t fld_imm_val = 0 | (bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (signed_bit_sub<31,1>(instr) << 12);
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -1272,16 +1272,16 @@ private:
                 this->gen_const(64U, 4)),
             64);
         this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 21);
         this->gen_trap_check(this->leave_blk);
         return std::make_tuple(iss::vm::BRANCH, nullptr);
     }
     
-    // instruction BGE
+    //22: instruction BGE
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __bge(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("BGE");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 22);
     
         int16_t fld_imm_val = 0 | (bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (signed_bit_sub<31,1>(instr) << 12);
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -1316,16 +1316,16 @@ private:
                 this->gen_const(64U, 4)),
             64);
         this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 22);
         this->gen_trap_check(this->leave_blk);
         return std::make_tuple(iss::vm::BRANCH, nullptr);
     }
     
-    // instruction BLTU
+    //23: instruction BLTU
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __bltu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("BLTU");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 23);
     
         int16_t fld_imm_val = 0 | (bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (signed_bit_sub<31,1>(instr) << 12);
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -1356,16 +1356,16 @@ private:
                 this->gen_const(64U, 4)),
             64);
         this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 23);
         this->gen_trap_check(this->leave_blk);
         return std::make_tuple(iss::vm::BRANCH, nullptr);
     }
     
-    // instruction BGEU
+    //24: instruction BGEU
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __bgeu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("BGEU");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 24);
     
         int16_t fld_imm_val = 0 | (bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (signed_bit_sub<31,1>(instr) << 12);
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -1396,16 +1396,16 @@ private:
                 this->gen_const(64U, 4)),
             64);
         this->builder.CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 24);
         this->gen_trap_check(this->leave_blk);
         return std::make_tuple(iss::vm::BRANCH, nullptr);
     }
     
-    // instruction LB
+    //25: instruction LB
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __lb(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("LB");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 25);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -1434,17 +1434,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 25);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction LH
+    //26: instruction LH
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __lh(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("LH");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 26);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -1473,17 +1473,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 26);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction LW
+    //27: instruction LW
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __lw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("LW");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 27);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -1512,17 +1512,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 27);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction LBU
+    //28: instruction LBU
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __lbu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("LBU");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 28);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -1551,17 +1551,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 28);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction LHU
+    //29: instruction LHU
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __lhu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("LHU");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 29);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -1590,17 +1590,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 29);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction SB
+    //30: instruction SB
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __sb(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("SB");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 30);
     
         int16_t fld_imm_val = 0 | (bit_sub<7,5>(instr)) | (signed_bit_sub<25,7>(instr) << 5);
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -1627,17 +1627,17 @@ private:
             offs_val,
             this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(8)));
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 30);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction SH
+    //31: instruction SH
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __sh(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("SH");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 31);
     
         int16_t fld_imm_val = 0 | (bit_sub<7,5>(instr)) | (signed_bit_sub<25,7>(instr) << 5);
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -1664,17 +1664,17 @@ private:
             offs_val,
             this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(16)));
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 31);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction SW
+    //32: instruction SW
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __sw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("SW");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 32);
     
         int16_t fld_imm_val = 0 | (bit_sub<7,5>(instr)) | (signed_bit_sub<25,7>(instr) << 5);
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -1701,17 +1701,17 @@ private:
             offs_val,
             this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32)));
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 32);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction ADDI
+    //33: instruction ADDI
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __addi(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("ADDI");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 33);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -1736,17 +1736,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 33);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction SLTI
+    //34: instruction SLTI
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __slti(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("SLTI");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 34);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -1780,17 +1780,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 34);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction SLTIU
+    //35: instruction SLTIU
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __sltiu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("SLTIU");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 35);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -1825,17 +1825,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 35);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction XORI
+    //36: instruction XORI
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __xori(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("XORI");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 36);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -1860,17 +1860,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 36);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction ORI
+    //37: instruction ORI
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __ori(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("ORI");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 37);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -1895,17 +1895,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 37);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction ANDI
+    //38: instruction ANDI
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __andi(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("ANDI");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 38);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -1930,17 +1930,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 38);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction ADD
+    //39: instruction ADD
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __add(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("ADD");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 39);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -1965,17 +1965,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 39);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction SUB
+    //40: instruction SUB
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __sub(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("SUB");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 40);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -2000,17 +2000,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 40);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction SLL
+    //41: instruction SLL
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __sll(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("SLL");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 41);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -2037,17 +2037,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 41);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction SLT
+    //42: instruction SLT
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __slt(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("SLT");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 42);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -2081,17 +2081,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 42);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction SLTU
+    //43: instruction SLTU
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __sltu(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("SLTU");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 43);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -2127,17 +2127,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 43);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction XOR
+    //44: instruction XOR
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __xor(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("XOR");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 44);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -2162,17 +2162,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 44);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction SRL
+    //45: instruction SRL
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __srl(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("SRL");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 45);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -2199,17 +2199,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 45);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction SRA
+    //46: instruction SRA
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __sra(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("SRA");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 46);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -2236,17 +2236,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 46);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction OR
+    //47: instruction OR
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __or(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("OR");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 47);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -2271,17 +2271,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 47);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction AND
+    //48: instruction AND
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __and(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("AND");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 48);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -2306,17 +2306,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 48);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction FENCE
+    //49: instruction FENCE
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __fence(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("FENCE");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 49);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -2343,17 +2343,17 @@ private:
             (uint64_t)0,
             this->builder.CreateZExtOrTrunc(FENCE_fence_val,this->get_type(64)));
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 49);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction FENCE_I
+    //50: instruction FENCE_I
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __fence_i(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("FENCE_I");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 50);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -2375,16 +2375,16 @@ private:
             (uint64_t)1,
             this->builder.CreateZExtOrTrunc(FENCE_fencei_val,this->get_type(64)));
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 50);
         this->gen_trap_check(this->leave_blk);
         return std::make_tuple(iss::vm::FLUSH, nullptr);
     }
     
-    // instruction ECALL
+    //51: instruction ECALL
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __ecall(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("ECALL");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 51);
     
         ;
         if(this->disass_enabled){
@@ -2399,16 +2399,16 @@ private:
         pc=pc+4;
     
         this->gen_raise_trap(0, 11);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 51);
         this->gen_trap_check(this->leave_blk);
         return std::make_tuple(iss::vm::BRANCH, nullptr);
     }
     
-    // instruction EBREAK
+    //52: instruction EBREAK
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __ebreak(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("EBREAK");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 52);
     
         ;
         if(this->disass_enabled){
@@ -2423,16 +2423,16 @@ private:
         pc=pc+4;
     
         this->gen_raise_trap(0, 3);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 52);
         this->gen_trap_check(this->leave_blk);
         return std::make_tuple(iss::vm::BRANCH, nullptr);
     }
     
-    // instruction URET
+    //53: instruction URET
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __uret(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("URET");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 53);
     
         ;
         if(this->disass_enabled){
@@ -2447,16 +2447,16 @@ private:
         pc=pc+4;
     
         this->gen_leave_trap(0);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 53);
         this->gen_trap_check(this->leave_blk);
         return std::make_tuple(iss::vm::BRANCH, nullptr);
     }
     
-    // instruction SRET
+    //54: instruction SRET
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __sret(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("SRET");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 54);
     
         ;
         if(this->disass_enabled){
@@ -2471,16 +2471,16 @@ private:
         pc=pc+4;
     
         this->gen_leave_trap(1);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 54);
         this->gen_trap_check(this->leave_blk);
         return std::make_tuple(iss::vm::BRANCH, nullptr);
     }
     
-    // instruction MRET
+    //55: instruction MRET
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __mret(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("MRET");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 55);
     
         ;
         if(this->disass_enabled){
@@ -2495,16 +2495,16 @@ private:
         pc=pc+4;
     
         this->gen_leave_trap(3);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 55);
         this->gen_trap_check(this->leave_blk);
         return std::make_tuple(iss::vm::BRANCH, nullptr);
     }
     
-    // instruction WFI
+    //56: instruction WFI
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __wfi(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("WFI");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 56);
     
         ;
         if(this->disass_enabled){
@@ -2520,17 +2520,17 @@ private:
     
         this->gen_wait(1);
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 56);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction SFENCE.VMA
+    //57: instruction SFENCE.VMA
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __sfence_vma(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("SFENCE.VMA");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 57);
     
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
         uint8_t fld_rs2_val = 0 | (bit_sub<20,5>(instr));
@@ -2556,17 +2556,17 @@ private:
             (uint64_t)3,
             this->builder.CreateZExtOrTrunc(FENCE_fencevmau_val,this->get_type(64)));
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 57);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction CSRRW
+    //58: instruction CSRRW
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __csrrw(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("CSRRW");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 58);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -2602,17 +2602,17 @@ private:
                 this->builder.CreateZExtOrTrunc(CSR_csr_val,this->get_type(64)));
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 58);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction CSRRS
+    //59: instruction CSRRS
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __csrrs(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("CSRRS");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 59);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -2646,17 +2646,17 @@ private:
                 this->builder.CreateZExtOrTrunc(CSR_csr_val,this->get_type(64)));
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 59);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction CSRRC
+    //60: instruction CSRRC
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __csrrc(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("CSRRC");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 60);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -2690,17 +2690,17 @@ private:
                 this->builder.CreateZExtOrTrunc(CSR_csr_val,this->get_type(64)));
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 60);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction CSRRWI
+    //61: instruction CSRRWI
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __csrrwi(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("CSRRWI");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 61);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_zimm_val = 0 | (bit_sub<15,5>(instr));
@@ -2731,17 +2731,17 @@ private:
             fld_csr_val,
             this->builder.CreateZExtOrTrunc(CSR_csr_val,this->get_type(64)));
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 61);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction CSRRSI
+    //62: instruction CSRRSI
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __csrrsi(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("CSRRSI");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 62);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_zimm_val = 0 | (bit_sub<15,5>(instr));
@@ -2777,17 +2777,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 62);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction CSRRCI
+    //63: instruction CSRRCI
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __csrrci(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("CSRRCI");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 63);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_zimm_val = 0 | (bit_sub<15,5>(instr));
@@ -2823,17 +2823,17 @@ private:
                 this->builder.CreateZExtOrTrunc(CSR_csr_val,this->get_type(64)));
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 63);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction LR.D
+    //64: instruction LR.D
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __lr_d(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("LR.D");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 64);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -2869,17 +2869,17 @@ private:
                 this->builder.CreateZExtOrTrunc(RES_offs_val,this->get_type(64)));
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 64);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction SC.D
+    //65: instruction SC.D
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __sc_d(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("SC.D");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 65);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -2934,17 +2934,17 @@ private:
         bb=bbnext;
         this->builder.SetInsertPoint(bb);
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 65);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction AMOSWAP.D
+    //66: instruction AMOSWAP.D
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __amoswap_d(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("AMOSWAP.D");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 66);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -2978,17 +2978,17 @@ private:
             offs_val,
             this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(64)));
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 66);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction AMOADD.D
+    //67: instruction AMOADD.D
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __amoadd_d(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("AMOADD.D");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 67);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -3026,17 +3026,17 @@ private:
             offs_val,
             this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(64)));
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 67);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction AMOXOR.D
+    //68: instruction AMOXOR.D
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __amoxor_d(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("AMOXOR.D");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 68);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -3074,17 +3074,17 @@ private:
             offs_val,
             this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(64)));
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 68);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction AMOAND.D
+    //69: instruction AMOAND.D
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __amoand_d(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("AMOAND.D");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 69);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -3122,17 +3122,17 @@ private:
             offs_val,
             this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(64)));
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 69);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction AMOOR.D
+    //70: instruction AMOOR.D
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __amoor_d(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("AMOOR.D");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 70);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -3170,17 +3170,17 @@ private:
             offs_val,
             this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(64)));
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 70);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction AMOMIN.D
+    //71: instruction AMOMIN.D
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __amomin_d(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("AMOMIN.D");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 71);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -3227,17 +3227,17 @@ private:
             offs_val,
             this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(64)));
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 71);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction AMOMAX.D
+    //72: instruction AMOMAX.D
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __amomax_d(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("AMOMAX.D");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 72);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -3284,17 +3284,17 @@ private:
             offs_val,
             this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(64)));
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 72);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction AMOMINU.D
+    //73: instruction AMOMINU.D
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __amominu_d(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("AMOMINU.D");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 73);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -3337,17 +3337,17 @@ private:
             offs_val,
             this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(64)));
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 73);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction AMOMAXU.D
+    //74: instruction AMOMAXU.D
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __amomaxu_d(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("AMOMAXU.D");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 74);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -3390,17 +3390,17 @@ private:
             offs_val,
             this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(64)));
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 74);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction LR.W
+    //75: instruction LR.W
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __lr_w(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("LR.W");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 75);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -3436,17 +3436,17 @@ private:
                 this->builder.CreateZExtOrTrunc(RES_offs_val,this->get_type(32)));
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 75);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction SC.W
+    //76: instruction SC.W
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __sc_w(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("SC.W");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 76);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -3500,17 +3500,17 @@ private:
             this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val), false);
         }
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 76);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction AMOSWAP.W
+    //77: instruction AMOSWAP.W
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __amoswap_w(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("AMOSWAP.W");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 77);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -3544,17 +3544,17 @@ private:
             offs_val,
             this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32)));
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 77);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction AMOADD.W
+    //78: instruction AMOADD.W
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __amoadd_w(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("AMOADD.W");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 78);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -3592,17 +3592,17 @@ private:
             offs_val,
             this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32)));
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 78);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction AMOXOR.W
+    //79: instruction AMOXOR.W
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __amoxor_w(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("AMOXOR.W");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 79);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -3640,17 +3640,17 @@ private:
             offs_val,
             this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32)));
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 79);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction AMOAND.W
+    //80: instruction AMOAND.W
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __amoand_w(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("AMOAND.W");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 80);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -3688,17 +3688,17 @@ private:
             offs_val,
             this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32)));
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 80);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction AMOOR.W
+    //81: instruction AMOOR.W
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __amoor_w(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("AMOOR.W");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 81);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -3736,17 +3736,17 @@ private:
             offs_val,
             this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32)));
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 81);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction AMOMIN.W
+    //82: instruction AMOMIN.W
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __amomin_w(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("AMOMIN.W");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 82);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -3793,17 +3793,17 @@ private:
             offs_val,
             this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32)));
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 82);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction AMOMAX.W
+    //83: instruction AMOMAX.W
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __amomax_w(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("AMOMAX.W");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 83);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -3850,17 +3850,17 @@ private:
             offs_val,
             this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32)));
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 83);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction AMOMINU.W
+    //84: instruction AMOMINU.W
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __amominu_w(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("AMOMINU.W");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 84);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -3903,17 +3903,17 @@ private:
             offs_val,
             this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32)));
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 84);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
     }
     
-    // instruction AMOMAXU.W
+    //85: instruction AMOMAXU.W
     std::tuple<vm::continuation_e, llvm::BasicBlock*> __amomaxu_w(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
         bb->setName("AMOMAXU.W");
     
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, 85);
     
         uint8_t fld_rd_val = 0 | (bit_sub<7,5>(instr));
         uint8_t fld_rs1_val = 0 | (bit_sub<15,5>(instr));
@@ -3960,7 +3960,7 @@ private:
             offs_val,
             this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32)));
         this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, 85);
         bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */
         this->gen_trap_check(bb);
         return std::make_tuple(vm::CONT, bb);
@@ -3972,17 +3972,16 @@ private:
      ****************************************************************************/
     std::tuple<vm::continuation_e, llvm::BasicBlock *> illegal_intruction(virt_addr_t &pc, code_word_t instr,
                                                                           llvm::BasicBlock *bb) {
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, sizeof(instr_descr)/sizeof(InstructionDesriptor));
         this->builder.CreateStore(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), true),
                                    get_reg_ptr(traits<ARCH>::PC), true);
         this->builder.CreateStore(
             this->builder.CreateAdd(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::ICOUNT), true),
                                      this->gen_const(64U, 1)),
             get_reg_ptr(traits<ARCH>::ICOUNT), true);
-        if (this->debugging_enabled()) this->gen_sync(iss::PRE_SYNC);
         pc = pc + ((instr & 3) == 3 ? 4 : 2);
         this->gen_raise_trap(0, 2);     // illegal instruction trap
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, sizeof(instr_descr)/sizeof(InstructionDesriptor));
         this->gen_trap_check(this->leave_blk);
         return std::make_tuple(iss::vm::BRANCH, nullptr);
     }
@@ -4013,8 +4012,8 @@ std::tuple<vm::continuation_e, llvm::BasicBlock *>
 vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, llvm::BasicBlock *this_block) {
     // we fetch at max 4 byte, alignment is 2
     code_word_t insn = 0;
-    iss::addr_t paddr(pc);
     const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
+    phys_addr_t paddr(pc);
     try {
         uint8_t *const data = (uint8_t *)&insn;
         paddr = this->core.v2p(pc);
diff --git a/riscv/src/main.cpp b/riscv/src/main.cpp
index 4affd45..8eb001a 100644
--- a/riscv/src/main.cpp
+++ b/riscv/src/main.cpp
@@ -57,13 +57,11 @@ int main(int argc, char *argv[]) {
         ("verbose,v", po::value<int>()->implicit_value(0), "Sets logging verbosity")
         ("logfile,f", po::value<std::string>(), "Sets default log file.")
         ("disass,d", po::value<std::string>()->implicit_value(""), "Enables disassembly")
-        ("elf", po::value<std::vector<std::string>>(), "ELF file(s) to load")
         ("gdb-port,g", po::value<unsigned>()->default_value(0), "enable gdb server and specify port to use")
-        ("input,i", po::value<std::string>(), "the elf file to load (instead of hex files)")
-        ("dump-ir", "dump the intermediate representation")
-        ("cycles,c", po::value<int64_t>()->default_value(-1), "number of cycles to run")
-        ("time", po::value<int>(), "SystemC simulation time in ms")
+        ("instructions,i", po::value<int64_t>()->default_value(-1), "max. number of instructions to simulate")
         ("reset,r", po::value<std::string>(), "reset address")
+        ("dump-ir", "dump the intermediate representation")
+        ("elf", po::value<std::vector<std::string>>(), "ELF file(s) to load")
         ("mem,m", po::value<std::string>(), "the memory input file")
         ("isa", po::value<std::string>()->default_value("rv32imac"), "isa to use for simulation");
     // clang-format on
@@ -137,7 +135,7 @@ int main(int argc, char *argv[]) {
             vm->reset();
         }
         int64_t cycles = -1;
-        cycles = clim["cycles"].as<int64_t>();
+        cycles = clim["instructions"].as<int64_t>();
         return vm->start(cycles, dump);
     } catch (std::exception &e) {
         LOG(ERROR) << "Unhandled Exception reached the top of main: " << e.what() << ", application will now exit"