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This commit is contained in:
Eyck Jentzsch
2017-09-21 20:29:23 +02:00
parent aa8c2138c6
commit 9a617dab57
55 changed files with 16145 additions and 166 deletions
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64
riscv/incl/sysc/SiFive/core_complex.h
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////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Contributors:
// eyck@minres.com - initial API and implementation
//
//
////////////////////////////////////////////////////////////////////////////////
#ifndef _SYSC_SIFIVE_FE310_H_
#define _SYSC_SIFIVE_FE310_H_
#include <iss/arch/rv32imac.h>
#include <iss/arch/riscv_hart_msu_vp.h>
#include <tlm>
#include <sysc/utilities.h>
namespace sysc {
namespace SiFive {
class core_complex:
public iss::arch::riscv_hart_msu_vp<iss::arch::rv32imac>,
public sc_core::sc_module {
public:
tlm::tlm_initiator_socket<32> initiator;
sc_core::sc_in<bool> rst_i;
core_complex(sc_core::sc_module_name name);
virtual ~core_complex();
};
} /* namespace SiFive */
} /* namespace sysc */
#endif /* _SYSC_SIFIVE_FE310_H_ */

11
riscv/incl/sysc/SiFive/gen/e300_plat_t.h
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#ifndef _E300_PLAT_MAP_H_
#define _E300_PLAT_MAP_H_
// need double braces, see https://stackoverflow.com/questions/6893700/how-to-construct-stdarray-object-with-initializer-list#6894191
const std::array<sysc::target_memory_map_entry<32>, 4> e300_plat_map = {{
{&i_plic, 0xc000000, 0x1000},
{&i_gpio, 0x10012000, 0x1000},
{&i_uart, 0x10013000, 0x1000},
{&i_spi, 0x10014000, 0x1000},
}};
#endif /* _E300_PLAT_MAP_H_ */

159
riscv/incl/sysc/SiFive/gen/gpio_regs.h
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////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Created on: Wed Sep 20 11:47:24 CEST 2017
// * gpio_regs.h Author: <RDL Generator>
//
////////////////////////////////////////////////////////////////////////////////
#ifndef _GPIO_REGS_H_
#define _GPIO_REGS_H_
#include <sysc/utilities.h>
#include <util/bit_field.h>
#include <sysc/register.h>
#include <sysc/tlm_target.h>
namespace sysc {
class gpio_regs :
public sc_core::sc_module,
public sysc::resetable
{
protected:
// storage declarations
uint32_t r_value;
uint32_t r_input_en;
uint32_t r_output_en;
uint32_t r_port;
uint32_t r_pue;
uint32_t r_ds;
uint32_t r_rise_ie;
uint32_t r_rise_ip;
uint32_t r_fall_ie;
uint32_t r_fall_ip;
uint32_t r_high_ie;
uint32_t r_high_ip;
uint32_t r_low_ie;
uint32_t r_low_ip;
uint32_t r_iof_en;
uint32_t r_iof_sel;
uint32_t r_out_xor;
// register declarations
sysc::sc_register<uint32_t> value;
sysc::sc_register<uint32_t> input_en;
sysc::sc_register<uint32_t> output_en;
sysc::sc_register<uint32_t> port;
sysc::sc_register<uint32_t> pue;
sysc::sc_register<uint32_t> ds;
sysc::sc_register<uint32_t> rise_ie;
sysc::sc_register<uint32_t> rise_ip;
sysc::sc_register<uint32_t> fall_ie;
sysc::sc_register<uint32_t> fall_ip;
sysc::sc_register<uint32_t> high_ie;
sysc::sc_register<uint32_t> high_ip;
sysc::sc_register<uint32_t> low_ie;
sysc::sc_register<uint32_t> low_ip;
sysc::sc_register<uint32_t> iof_en;
sysc::sc_register<uint32_t> iof_sel;
sysc::sc_register<uint32_t> out_xor;
public:
gpio_regs(sc_core::sc_module_name nm);
template<unsigned BUSWIDTH=32>
void registerResources(sysc::tlm_target<BUSWIDTH>& target);
};
}
//////////////////////////////////////////////////////////////////////////////
// member functions
//////////////////////////////////////////////////////////////////////////////
inline sysc::gpio_regs::gpio_regs(sc_core::sc_module_name nm)
: sc_core::sc_module(nm)
, NAMED(value, r_value, 0, *this)
, NAMED(input_en, r_input_en, 0, *this)
, NAMED(output_en, r_output_en, 0, *this)
, NAMED(port, r_port, 0, *this)
, NAMED(pue, r_pue, 0, *this)
, NAMED(ds, r_ds, 0, *this)
, NAMED(rise_ie, r_rise_ie, 0, *this)
, NAMED(rise_ip, r_rise_ip, 0, *this)
, NAMED(fall_ie, r_fall_ie, 0, *this)
, NAMED(fall_ip, r_fall_ip, 0, *this)
, NAMED(high_ie, r_high_ie, 0, *this)
, NAMED(high_ip, r_high_ip, 0, *this)
, NAMED(low_ie, r_low_ie, 0, *this)
, NAMED(low_ip, r_low_ip, 0, *this)
, NAMED(iof_en, r_iof_en, 0, *this)
, NAMED(iof_sel, r_iof_sel, 0, *this)
, NAMED(out_xor, r_out_xor, 0, *this)
{
}
template<unsigned BUSWIDTH>
inline void sysc::gpio_regs::registerResources(sysc::tlm_target<BUSWIDTH>& target) {
target.addResource(value, 0x0UL);
target.addResource(input_en, 0x4UL);
target.addResource(output_en, 0x8UL);
target.addResource(port, 0xcUL);
target.addResource(pue, 0x10UL);
target.addResource(ds, 0x14UL);
target.addResource(rise_ie, 0x18UL);
target.addResource(rise_ip, 0x1cUL);
target.addResource(fall_ie, 0x20UL);
target.addResource(fall_ip, 0x24UL);
target.addResource(high_ie, 0x28UL);
target.addResource(high_ip, 0x2cUL);
target.addResource(low_ie, 0x30UL);
target.addResource(low_ip, 0x34UL);
target.addResource(iof_en, 0x38UL);
target.addResource(iof_sel, 0x3cUL);
target.addResource(out_xor, 0x40UL);
}
#endif // _GPIO_REGS_H_

104
riscv/incl/sysc/SiFive/gen/plic_regs.h
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////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Created on: Wed Sep 20 22:30:45 CEST 2017
// * plic_regs.h Author: <RDL Generator>
//
////////////////////////////////////////////////////////////////////////////////
#ifndef _PLIC_REGS_H_
#define _PLIC_REGS_H_
#include <sysc/utilities.h>
#include <util/bit_field.h>
#include <sysc/register.h>
#include <sysc/tlm_target.h>
namespace sysc {
class plic_regs :
public sc_core::sc_module,
public sysc::resetable
{
protected:
// storage declarations
BEGIN_BF_DECL(priority_t, uint32_t);
BF_FIELD(priority, 0, 3);
END_BF_DECL() ;
std::array<priority_t, 255> r_priority;
uint32_t r_pending;
uint32_t r_enabled;
BEGIN_BF_DECL(threshold_t, uint32_t);
BF_FIELD(threshold, 0, 3);
END_BF_DECL() r_threshold;
uint32_t r_claim_complete;
// register declarations
sysc::sc_register_indexed<priority_t, 255> priority;
sysc::sc_register<uint32_t> pending;
sysc::sc_register<uint32_t> enabled;
sysc::sc_register<threshold_t> threshold;
sysc::sc_register<uint32_t> claim_complete;
public:
plic_regs(sc_core::sc_module_name nm);
template<unsigned BUSWIDTH=32>
void registerResources(sysc::tlm_target<BUSWIDTH>& target);
};
}
//////////////////////////////////////////////////////////////////////////////
// member functions
//////////////////////////////////////////////////////////////////////////////
inline sysc::plic_regs::plic_regs(sc_core::sc_module_name nm)
: sc_core::sc_module(nm)
, NAMED(priority, r_priority, 0, *this)
, NAMED(pending, r_pending, 0, *this)
, NAMED(enabled, r_enabled, 0, *this)
, NAMED(threshold, r_threshold, 0, *this)
, NAMED(claim_complete, r_claim_complete, 0, *this)
{
}
template<unsigned BUSWIDTH>
inline void sysc::plic_regs::registerResources(sysc::tlm_target<BUSWIDTH>& target) {
target.addResource(priority, 0x4UL);
target.addResource(pending, 0x1000UL);
target.addResource(enabled, 0x2000UL);
target.addResource(threshold, 0xc200000UL);
target.addResource(claim_complete, 0xc200004UL);
}
#endif // _PLIC_REGS_H_

199
riscv/incl/sysc/SiFive/gen/spi_regs.h
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@@ -1,199 +0,0 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Created on: Wed Sep 20 22:30:45 CEST 2017
// * spi_regs.h Author: <RDL Generator>
//
////////////////////////////////////////////////////////////////////////////////
#ifndef _SPI_REGS_H_
#define _SPI_REGS_H_
#include <sysc/utilities.h>
#include <util/bit_field.h>
#include <sysc/register.h>
#include <sysc/tlm_target.h>
namespace sysc {
class spi_regs :
public sc_core::sc_module,
public sysc::resetable
{
protected:
// storage declarations
BEGIN_BF_DECL(sckdiv_t, uint32_t);
BF_FIELD(div, 0, 12);
END_BF_DECL() r_sckdiv;
BEGIN_BF_DECL(sckmode_t, uint32_t);
BF_FIELD(pha, 0, 1);
BF_FIELD(pol, 1, 1);
END_BF_DECL() r_sckmode;
uint32_t r_csid;
uint32_t r_csdef;
BEGIN_BF_DECL(csmode_t, uint32_t);
BF_FIELD(mode, 0, 2);
END_BF_DECL() r_csmode;
BEGIN_BF_DECL(delay0_t, uint32_t);
BF_FIELD(cssck, 0, 8);
BF_FIELD(sckcs, 16, 8);
END_BF_DECL() r_delay0;
BEGIN_BF_DECL(delay1_t, uint32_t);
BF_FIELD(intercs, 0, 16);
BF_FIELD(interxfr, 16, 8);
END_BF_DECL() r_delay1;
BEGIN_BF_DECL(fmt_t, uint32_t);
BF_FIELD(proto, 0, 2);
BF_FIELD(endian, 2, 1);
BF_FIELD(dir, 3, 1);
BF_FIELD(len, 16, 4);
END_BF_DECL() r_fmt;
BEGIN_BF_DECL(txdata_t, uint32_t);
BF_FIELD(data, 0, 8);
BF_FIELD(full, 31, 1);
END_BF_DECL() r_txdata;
BEGIN_BF_DECL(rxdata_t, uint32_t);
BF_FIELD(data, 0, 8);
BF_FIELD(empty, 31, 1);
END_BF_DECL() r_rxdata;
BEGIN_BF_DECL(txmark_t, uint32_t);
BF_FIELD(txmark, 0, 3);
END_BF_DECL() r_txmark;
BEGIN_BF_DECL(rxmark_t, uint32_t);
BF_FIELD(rxmark, 0, 3);
END_BF_DECL() r_rxmark;
BEGIN_BF_DECL(fctrl_t, uint32_t);
BF_FIELD(en, 0, 1);
END_BF_DECL() r_fctrl;
BEGIN_BF_DECL(ffmt_t, uint32_t);
BF_FIELD(cmd_en, 0, 1);
BF_FIELD(addr_len, 1, 2);
BF_FIELD(pad_cnt, 3, 4);
BF_FIELD(cmd_proto, 7, 2);
BF_FIELD(addr_proto, 9, 2);
BF_FIELD(data_proto, 11, 2);
BF_FIELD(cmd_code, 16, 8);
BF_FIELD(pad_code, 24, 8);
END_BF_DECL() r_ffmt;
BEGIN_BF_DECL(ie_t, uint32_t);
BF_FIELD(txwm, 0, 1);
BF_FIELD(rxwm, 1, 1);
END_BF_DECL() r_ie;
BEGIN_BF_DECL(ip_t, uint32_t);
BF_FIELD(txwm, 0, 1);
BF_FIELD(rxwm, 1, 1);
END_BF_DECL() r_ip;
// register declarations
sysc::sc_register<sckdiv_t> sckdiv;
sysc::sc_register<sckmode_t> sckmode;
sysc::sc_register<uint32_t> csid;
sysc::sc_register<uint32_t> csdef;
sysc::sc_register<csmode_t> csmode;
sysc::sc_register<delay0_t> delay0;
sysc::sc_register<delay1_t> delay1;
sysc::sc_register<fmt_t> fmt;
sysc::sc_register<txdata_t> txdata;
sysc::sc_register<rxdata_t> rxdata;
sysc::sc_register<txmark_t> txmark;
sysc::sc_register<rxmark_t> rxmark;
sysc::sc_register<fctrl_t> fctrl;
sysc::sc_register<ffmt_t> ffmt;
sysc::sc_register<ie_t> ie;
sysc::sc_register<ip_t> ip;
public:
spi_regs(sc_core::sc_module_name nm);
template<unsigned BUSWIDTH=32>
void registerResources(sysc::tlm_target<BUSWIDTH>& target);
};
}
//////////////////////////////////////////////////////////////////////////////
// member functions
//////////////////////////////////////////////////////////////////////////////
inline sysc::spi_regs::spi_regs(sc_core::sc_module_name nm)
: sc_core::sc_module(nm)
, NAMED(sckdiv, r_sckdiv, 0, *this)
, NAMED(sckmode, r_sckmode, 0, *this)
, NAMED(csid, r_csid, 0, *this)
, NAMED(csdef, r_csdef, 0, *this)
, NAMED(csmode, r_csmode, 0, *this)
, NAMED(delay0, r_delay0, 0, *this)
, NAMED(delay1, r_delay1, 0, *this)
, NAMED(fmt, r_fmt, 0, *this)
, NAMED(txdata, r_txdata, 0, *this)
, NAMED(rxdata, r_rxdata, 0, *this)
, NAMED(txmark, r_txmark, 0, *this)
, NAMED(rxmark, r_rxmark, 0, *this)
, NAMED(fctrl, r_fctrl, 0, *this)
, NAMED(ffmt, r_ffmt, 0, *this)
, NAMED(ie, r_ie, 0, *this)
, NAMED(ip, r_ip, 0, *this)
{
}
template<unsigned BUSWIDTH>
inline void sysc::spi_regs::registerResources(sysc::tlm_target<BUSWIDTH>& target) {
target.addResource(sckdiv, 0x0UL);
target.addResource(sckmode, 0x4UL);
target.addResource(csid, 0x10UL);
target.addResource(csdef, 0x14UL);
target.addResource(csmode, 0x18UL);
target.addResource(delay0, 0x28UL);
target.addResource(delay1, 0x2cUL);
target.addResource(fmt, 0x40UL);
target.addResource(txdata, 0x48UL);
target.addResource(rxdata, 0x4cUL);
target.addResource(txmark, 0x50UL);
target.addResource(rxmark, 0x54UL);
target.addResource(fctrl, 0x60UL);
target.addResource(ffmt, 0x64UL);
target.addResource(ie, 0x70UL);
target.addResource(ip, 0x74UL);
}
#endif // _SPI_REGS_H_

132
riscv/incl/sysc/SiFive/gen/uart_regs.h
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@@ -1,132 +0,0 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Created on: Wed Sep 20 22:30:45 CEST 2017
// * uart_regs.h Author: <RDL Generator>
//
////////////////////////////////////////////////////////////////////////////////
#ifndef _UART_REGS_H_
#define _UART_REGS_H_
#include <sysc/utilities.h>
#include <util/bit_field.h>
#include <sysc/register.h>
#include <sysc/tlm_target.h>
namespace sysc {
class uart_regs :
public sc_core::sc_module,
public sysc::resetable
{
protected:
// storage declarations
BEGIN_BF_DECL(txdata_t, uint32_t);
BF_FIELD(data, 0, 8);
BF_FIELD(full, 31, 1);
END_BF_DECL() r_txdata;
BEGIN_BF_DECL(rxdata_t, uint32_t);
BF_FIELD(data, 0, 8);
BF_FIELD(empty, 31, 1);
END_BF_DECL() r_rxdata;
BEGIN_BF_DECL(txctrl_t, uint32_t);
BF_FIELD(txen, 0, 1);
BF_FIELD(nstop, 1, 1);
BF_FIELD(reserved, 2, 14);
BF_FIELD(txcnt, 16, 3);
END_BF_DECL() r_txctrl;
BEGIN_BF_DECL(rxctrl_t, uint32_t);
BF_FIELD(rxen, 0, 1);
BF_FIELD(reserved, 1, 15);
BF_FIELD(rxcnt, 16, 3);
END_BF_DECL() r_rxctrl;
BEGIN_BF_DECL(ie_t, uint32_t);
BF_FIELD(txwm, 0, 1);
BF_FIELD(rxwm, 1, 1);
END_BF_DECL() r_ie;
BEGIN_BF_DECL(ip_t, uint32_t);
BF_FIELD(txwm, 0, 1);
BF_FIELD(rxwm, 1, 1);
END_BF_DECL() r_ip;
BEGIN_BF_DECL(div_t, uint32_t);
BF_FIELD(div, 0, 16);
END_BF_DECL() r_div;
// register declarations
sysc::sc_register<txdata_t> txdata;
sysc::sc_register<rxdata_t> rxdata;
sysc::sc_register<txctrl_t> txctrl;
sysc::sc_register<rxctrl_t> rxctrl;
sysc::sc_register<ie_t> ie;
sysc::sc_register<ip_t> ip;
sysc::sc_register<div_t> div;
public:
uart_regs(sc_core::sc_module_name nm);
template<unsigned BUSWIDTH=32>
void registerResources(sysc::tlm_target<BUSWIDTH>& target);
};
}
//////////////////////////////////////////////////////////////////////////////
// member functions
//////////////////////////////////////////////////////////////////////////////
inline sysc::uart_regs::uart_regs(sc_core::sc_module_name nm)
: sc_core::sc_module(nm)
, NAMED(txdata, r_txdata, 0, *this)
, NAMED(rxdata, r_rxdata, 0, *this)
, NAMED(txctrl, r_txctrl, 0, *this)
, NAMED(rxctrl, r_rxctrl, 0, *this)
, NAMED(ie, r_ie, 0, *this)
, NAMED(ip, r_ip, 0, *this)
, NAMED(div, r_div, 0, *this)
{
}
template<unsigned BUSWIDTH>
inline void sysc::uart_regs::registerResources(sysc::tlm_target<BUSWIDTH>& target) {
target.addResource(txdata, 0x0UL);
target.addResource(rxdata, 0x4UL);
target.addResource(txctrl, 0x8UL);
target.addResource(rxctrl, 0xcUL);
target.addResource(ie, 0x10UL);
target.addResource(ip, 0x14UL);
target.addResource(div, 0x18UL);
}
#endif // _UART_REGS_H_

42
riscv/incl/sysc/SiFive/gpio.h
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@@ -1,42 +0,0 @@
/*******************************************************************************
* Copyright 2017 eyck@minres.com
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may not
* use this file except in compliance with the License. You may obtain a copy
* of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations under
* the License.
******************************************************************************/
#ifndef _GPIO_H_
#define _GPIO_H_
#include <sysc/tlm_target.h>
namespace sysc {
class gpio_regs;
class gpio: public sc_core::sc_module, public tlm_target<> {
public:
SC_HAS_PROCESS(gpio);
sc_core::sc_in<sc_core::sc_time> clk_i;
sc_core::sc_in<bool> rst_i;
gpio(sc_core::sc_module_name nm);
virtual ~gpio();
protected:
void clock_cb();
void reset_cb();
sc_core::sc_time clk;
std::unique_ptr<gpio_regs> regs;
};
} /* namespace sysc */
#endif /* _GPIO_H_ */

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riscv/incl/sysc/SiFive/platform.h
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@@ -1,62 +0,0 @@
/*******************************************************************************
* Copyright 2017 eyck@minres.com
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may not
* use this file except in compliance with the License. You may obtain a copy
* of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations under
* the License.
******************************************************************************/
/*
* simplesystem.h
*
* Created on: 17.09.2017
* Author: eyck@minres.com
*/
#ifndef SIMPLESYSTEM_H_
#define SIMPLESYSTEM_H_
#include "uart.h"
#include "spi.h"
#include "gpio.h"
#include "plic.h"
#include <sysc/router.h>
#include <sysc/kernel/sc_module.h>
#include <array>
#include "core_complex.h"
namespace sysc {
class platform: public sc_core::sc_module {
public:
SC_HAS_PROCESS(platform);
SiFive::core_complex i_master;
router<> i_router;
uart i_uart;
spi i_spi;
gpio i_gpio;
plic i_plic;
sc_core::sc_signal<sc_core::sc_time> s_clk;
sc_core::sc_signal<bool> s_rst;
platform(sc_core::sc_module_name nm);
protected:
void gen_reset();
#include "gen/e300_plat_t.h"
};
} /* namespace sysc */
#endif /* SIMPLESYSTEM_H_ */

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riscv/incl/sysc/SiFive/plic.h
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/*******************************************************************************
* Copyright 2017 eyck@minres.com
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may not
* use this file except in compliance with the License. You may obtain a copy
* of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations under
* the License.
******************************************************************************/
#ifndef _PLIC_H_
#define _PLIC_H_
#include <sysc/tlm_target.h>
namespace sysc {
class plic_regs;
class plic: public sc_core::sc_module, public tlm_target<> {
public:
SC_HAS_PROCESS(plic);
sc_core::sc_in<sc_core::sc_time> clk_i;
sc_core::sc_in<bool> rst_i;
plic(sc_core::sc_module_name nm);
virtual ~plic();
protected:
void clock_cb();
void reset_cb();
sc_core::sc_time clk;
std::unique_ptr<plic_regs> regs;
};
} /* namespace sysc */
#endif /* _PLIC_H_ */

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riscv/incl/sysc/SiFive/spi.h
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/*******************************************************************************
* Copyright 2017 eyck@minres.com
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may not
* use this file except in compliance with the License. You may obtain a copy
* of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations under
* the License.
******************************************************************************/
#ifndef _SPI_H_
#define _SPI_H_
#include <sysc/tlm_target.h>
namespace sysc {
class spi_regs;
class spi: public sc_core::sc_module, public tlm_target<> {
public:
SC_HAS_PROCESS(spi);
sc_core::sc_in<sc_core::sc_time> clk_i;
sc_core::sc_in<bool> rst_i;
spi(sc_core::sc_module_name nm);
virtual ~spi();
protected:
void clock_cb();
void reset_cb();
sc_core::sc_time clk;
std::unique_ptr<spi_regs> regs;
};
} /* namespace sysc */
#endif /* _SPI_H_ */

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riscv/incl/sysc/SiFive/uart.h
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/*******************************************************************************
* Copyright 2017 eyck@minres.com
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may not
* use this file except in compliance with the License. You may obtain a copy
* of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations under
* the License.
******************************************************************************/
#ifndef _UART_H_
#define _UART_H_
#include <sysc/tlm_target.h>
namespace sysc {
class uart_regs;
class uart: public sc_core::sc_module, public tlm_target<> {
public:
SC_HAS_PROCESS(uart);
sc_core::sc_in<sc_core::sc_time> clk_i;
sc_core::sc_in<bool> rst_i;
uart(sc_core::sc_module_name nm);
virtual ~uart();
protected:
void clock_cb();
void reset_cb();
sc_core::sc_time clk;
std::unique_ptr<uart_regs> regs;
};
} /* namespace sysc */
#endif /* _UART_H_ */