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Restructured project

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This commit is contained in:
Eyck Jentzsch
2017-09-21 20:29:23 +02:00
parent aa8c2138c6
commit 9a617dab57
55 changed files with 16145 additions and 166 deletions
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11
riscv/fe310.rdl
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@ -1,11 +0,0 @@
`include "gpio.rdl"
`include "uart.rdl"
`include "spi.rdl"
`include "plic.rdl"
addrmap e300_plat_t {
plic_regs plic @0x0C000000;
gpio_regs gpio @0x10012000;
uart_regs uart @0x10013000;
spi_regs spi @0x10014000;
} e300_plat;

0
riscv/src/RV32A.core_desc → riscv/gen_input/RV32A.core_desc
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0
riscv/src/RV32C.core_desc → riscv/gen_input/RV32C.core_desc
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0
riscv/src/RV32F.core_desc → riscv/gen_input/RV32F.core_desc
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0
riscv/src/RV32IBase.core_desc → riscv/gen_input/RV32IBase.core_desc
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0
riscv/src/RV32M.core_desc → riscv/gen_input/RV32M.core_desc
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0
riscv/src/RV64A.core_desc → riscv/gen_input/RV64A.core_desc
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0
riscv/src/RV64IBase.core_desc → riscv/gen_input/RV64IBase.core_desc
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0
riscv/src/RV64M.core_desc → riscv/gen_input/RV64M.core_desc
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0
riscv/src/minres_rv.core_desc → riscv/gen_input/minres_rv.core_desc
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122
riscv/gpio.rdl
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@ -1,122 +0,0 @@
regfile gpio_regs {
lsb0;
reg {
name="value";
desc="pin value";
field {
name = "data";
} data[31:0];
} value @0x000;
reg {
name="input_en";
desc="* pin input enable";
field {
name = "data";
} data[31:0];
} input_en @0x004;
reg {
name="output_en";
desc="pin output enable";
field {
name = "data";
} data[31:0];
} output_en @0x008;
reg {
name="port";
desc="output port value";
field {
name = "data";
} data[31:0];
} port @0x00C;
reg {
name="pue";
desc="internal pull-up enable";
field {
name = "data";
} data[31:0];
} pue @0x010;
reg {
name="ds";
desc="Pin Drive Strength";
field {
name = "data";
} data[31:0];
} ds @0x014;
reg {
name="rise_ie";
desc="rise interrupt enable";
field {
name = "data";
} data[31:0];
} rise_ie @0x018;
reg {
name="rise_ip";
desc="rise interrupt pending";
field {
name = "data";
} data[31:0];
} rise_ip @0x01C;
reg {
name="fall_ie";
desc="fall interrupt enable";
field {
name = "data";
} data[31:0];
} fall_ie @0x020;
reg {
name="fall_ip";
desc="fall interrupt pending";
field {
name = "data";
} data[31:0];
} fall_ip @0x024;
reg {
name="high_ie";
desc="high interrupt enable";
field {
name = "data";
} data[31:0];
} high_ie @0x028;
reg {
name="high_ip";
desc="high interrupt pending";
field {
name = "data";
} data[31:0];
} high_ip @0x02C;
reg {
name="low_ie";
desc="low interrupt enable";
field {
name = "data";
} data[31:0];
} low_ie @0x030;
reg {
name="low_ip";
desc="low interrupt pending";
field {
name = "data";
} data[31:0];
} low_ip @0x034;
reg {
name="iof_en";
desc="HW I/O Function enable";
field {
name = "data";
} data[31:0];
} iof_en @0x038;
reg {
name="iof_sel";
desc="HW I/O Function select";
field {
name = "data";
} data[31:0];
} iof_sel @0x03C;
reg {
name="out_xor";
desc="Output XOR (invert)";
field {
name = "data";
} data[31:0];
} out_xor @0x040;
};

3
riscv/incl/iss/arch/riscv_hart_msu_vp.h
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@ -523,7 +523,8 @@ protected:
using csr_page_type = typename csr_type::page_type;
mem_type mem;
csr_type csr;
reg_t& mstatus_r, satp_r;
reg_t& mstatus_r;
reg_t& satp_r;
unsigned to_host_wr_cnt=0;
std::stringstream uart_buf;
std::unordered_map<reg_t, uint64_t> ptw;

2
riscv/incl/iss/arch/rv32imac.h
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@ -28,7 +28,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Created on: Tue Sep 05 18:57:24 CEST 2017
// Created on: Thu Sep 21 17:01:54 CEST 2017
// * rv32imac.h Author: <CoreDSL Generator>
//
////////////////////////////////////////////////////////////////////////////////

200
riscv/incl/iss/arch/rv64ia.h Normal file
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@ -0,0 +1,200 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Created on: Thu Sep 21 17:01:54 CEST 2017
// * rv64ia.h Author: <CoreDSL Generator>
//
////////////////////////////////////////////////////////////////////////////////
#ifndef _RV64IA_H_
#define _RV64IA_H_
#include <iss/arch_if.h>
#include <iss/vm_if.h>
#include <iss/arch/traits.h>
namespace iss {
namespace arch {
struct rv64ia;
template<>
struct traits<rv64ia> {
enum constants {XLEN=64,XLEN2=128,XLEN_BIT_MASK=63,PCLEN=64,fence=0,fencei=1,fencevmal=2,fencevmau=3,MISA_VAL=2147750144,PGSIZE=4096,PGMASK=4095};
enum reg_e {
X0,
X1,
X2,
X3,
X4,
X5,
X6,
X7,
X8,
X9,
X10,
X11,
X12,
X13,
X14,
X15,
X16,
X17,
X18,
X19,
X20,
X21,
X22,
X23,
X24,
X25,
X26,
X27,
X28,
X29,
X30,
X31,
PC,
NUM_REGS,
NEXT_PC=NUM_REGS,
TRAP_STATE,
PENDING_TRAP,
MACHINE_STATE,
ICOUNT
};
typedef uint64_t reg_t;
typedef uint64_t addr_t;
typedef uint64_t code_word_t; //TODO: check removal
typedef iss::typed_addr_t<iss::VIRTUAL> virt_addr_t;
typedef iss::typed_addr_t<iss::PHYSICAL> phys_addr_t;
constexpr static unsigned reg_bit_width(unsigned r) {
const uint32_t RV64IA_reg_size[] = {64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,32,32,32,64};
return RV64IA_reg_size[r];
}
constexpr static unsigned reg_byte_offset(unsigned r) {
const uint32_t RV64IA_reg_byte_offset[] = {0,8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128,136,144,152,160,168,176,184,192,200,208,216,224,232,240,248,256,264,272,276,280,288,296};
return RV64IA_reg_byte_offset[r];
}
enum sreg_flag_e {FLAGS};
enum mem_type_e {MEM,CSR,FENCE,RES};
};
struct rv64ia: public arch_if {
using virt_addr_t = typename traits<rv64ia>::virt_addr_t;
using phys_addr_t = typename traits<rv64ia>::phys_addr_t;
using reg_t = typename traits<rv64ia>::reg_t;
using addr_t = typename traits<rv64ia>::addr_t;
rv64ia();
~rv64ia();
virtual void reset(uint64_t address=0) override;
virtual uint8_t* get_regs_base_ptr() override;
/// deprecated
virtual void get_reg(short idx, std::vector<uint8_t>& value) override {}
virtual void set_reg(short idx, const std::vector<uint8_t>& value) override {}
/// deprecated
virtual bool get_flag(int flag) override {return false;}
virtual void set_flag(int, bool value) override {};
/// deprecated
virtual void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
virtual void notify_phase(exec_phase phase){
if(phase==ISTART){
++reg.icount;
reg.PC=reg.NEXT_PC;
reg.trap_state=reg.pending_trap;
}
}
uint64_t get_icount() { return reg.icount;}
virtual phys_addr_t v2p(const iss::addr_t& pc);
virtual iss::sync_type needed_sync() const { return iss::PRE_SYNC; }
protected:
struct RV64IA_regs {
uint64_t X0;
uint64_t X1;
uint64_t X2;
uint64_t X3;
uint64_t X4;
uint64_t X5;
uint64_t X6;
uint64_t X7;
uint64_t X8;
uint64_t X9;
uint64_t X10;
uint64_t X11;
uint64_t X12;
uint64_t X13;
uint64_t X14;
uint64_t X15;
uint64_t X16;
uint64_t X17;
uint64_t X18;
uint64_t X19;
uint64_t X20;
uint64_t X21;
uint64_t X22;
uint64_t X23;
uint64_t X24;
uint64_t X25;
uint64_t X26;
uint64_t X27;
uint64_t X28;
uint64_t X29;
uint64_t X30;
uint64_t X31;
uint64_t PC;
uint64_t NEXT_PC;
uint32_t trap_state, pending_trap, machine_state;
uint64_t icount;
} reg;
};
}
}
#endif /* _RV64IA_H_ */

64
riscv/incl/sysc/SiFive/core_complex.h
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@ -1,64 +0,0 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Contributors:
// eyck@minres.com - initial API and implementation
//
//
////////////////////////////////////////////////////////////////////////////////
#ifndef _SYSC_SIFIVE_FE310_H_
#define _SYSC_SIFIVE_FE310_H_
#include <iss/arch/rv32imac.h>
#include <iss/arch/riscv_hart_msu_vp.h>
#include <tlm>
#include <sysc/utilities.h>
namespace sysc {
namespace SiFive {
class core_complex:
public iss::arch::riscv_hart_msu_vp<iss::arch::rv32imac>,
public sc_core::sc_module {
public:
tlm::tlm_initiator_socket<32> initiator;
sc_core::sc_in<bool> rst_i;
core_complex(sc_core::sc_module_name name);
virtual ~core_complex();
};
} /* namespace SiFive */
} /* namespace sysc */
#endif /* _SYSC_SIFIVE_FE310_H_ */

11
riscv/incl/sysc/SiFive/gen/e300_plat_t.h
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@ -1,11 +0,0 @@
#ifndef _E300_PLAT_MAP_H_
#define _E300_PLAT_MAP_H_
// need double braces, see https://stackoverflow.com/questions/6893700/how-to-construct-stdarray-object-with-initializer-list#6894191
const std::array<sysc::target_memory_map_entry<32>, 4> e300_plat_map = {{
{&i_plic, 0xc000000, 0x1000},
{&i_gpio, 0x10012000, 0x1000},
{&i_uart, 0x10013000, 0x1000},
{&i_spi, 0x10014000, 0x1000},
}};
#endif /* _E300_PLAT_MAP_H_ */

159
riscv/incl/sysc/SiFive/gen/gpio_regs.h
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@ -1,159 +0,0 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Created on: Wed Sep 20 11:47:24 CEST 2017
// * gpio_regs.h Author: <RDL Generator>
//
////////////////////////////////////////////////////////////////////////////////
#ifndef _GPIO_REGS_H_
#define _GPIO_REGS_H_
#include <sysc/utilities.h>
#include <util/bit_field.h>
#include <sysc/register.h>
#include <sysc/tlm_target.h>
namespace sysc {
class gpio_regs :
public sc_core::sc_module,
public sysc::resetable
{
protected:
// storage declarations
uint32_t r_value;
uint32_t r_input_en;
uint32_t r_output_en;
uint32_t r_port;
uint32_t r_pue;
uint32_t r_ds;
uint32_t r_rise_ie;
uint32_t r_rise_ip;
uint32_t r_fall_ie;
uint32_t r_fall_ip;
uint32_t r_high_ie;
uint32_t r_high_ip;
uint32_t r_low_ie;
uint32_t r_low_ip;
uint32_t r_iof_en;
uint32_t r_iof_sel;
uint32_t r_out_xor;
// register declarations
sysc::sc_register<uint32_t> value;
sysc::sc_register<uint32_t> input_en;
sysc::sc_register<uint32_t> output_en;
sysc::sc_register<uint32_t> port;
sysc::sc_register<uint32_t> pue;
sysc::sc_register<uint32_t> ds;
sysc::sc_register<uint32_t> rise_ie;
sysc::sc_register<uint32_t> rise_ip;
sysc::sc_register<uint32_t> fall_ie;
sysc::sc_register<uint32_t> fall_ip;
sysc::sc_register<uint32_t> high_ie;
sysc::sc_register<uint32_t> high_ip;
sysc::sc_register<uint32_t> low_ie;
sysc::sc_register<uint32_t> low_ip;
sysc::sc_register<uint32_t> iof_en;
sysc::sc_register<uint32_t> iof_sel;
sysc::sc_register<uint32_t> out_xor;
public:
gpio_regs(sc_core::sc_module_name nm);
template<unsigned BUSWIDTH=32>
void registerResources(sysc::tlm_target<BUSWIDTH>& target);
};
}
//////////////////////////////////////////////////////////////////////////////
// member functions
//////////////////////////////////////////////////////////////////////////////
inline sysc::gpio_regs::gpio_regs(sc_core::sc_module_name nm)
: sc_core::sc_module(nm)
, NAMED(value, r_value, 0, *this)
, NAMED(input_en, r_input_en, 0, *this)
, NAMED(output_en, r_output_en, 0, *this)
, NAMED(port, r_port, 0, *this)
, NAMED(pue, r_pue, 0, *this)
, NAMED(ds, r_ds, 0, *this)
, NAMED(rise_ie, r_rise_ie, 0, *this)
, NAMED(rise_ip, r_rise_ip, 0, *this)
, NAMED(fall_ie, r_fall_ie, 0, *this)
, NAMED(fall_ip, r_fall_ip, 0, *this)
, NAMED(high_ie, r_high_ie, 0, *this)
, NAMED(high_ip, r_high_ip, 0, *this)
, NAMED(low_ie, r_low_ie, 0, *this)
, NAMED(low_ip, r_low_ip, 0, *this)
, NAMED(iof_en, r_iof_en, 0, *this)
, NAMED(iof_sel, r_iof_sel, 0, *this)
, NAMED(out_xor, r_out_xor, 0, *this)
{
}
template<unsigned BUSWIDTH>
inline void sysc::gpio_regs::registerResources(sysc::tlm_target<BUSWIDTH>& target) {
target.addResource(value, 0x0UL);
target.addResource(input_en, 0x4UL);
target.addResource(output_en, 0x8UL);
target.addResource(port, 0xcUL);
target.addResource(pue, 0x10UL);
target.addResource(ds, 0x14UL);
target.addResource(rise_ie, 0x18UL);
target.addResource(rise_ip, 0x1cUL);
target.addResource(fall_ie, 0x20UL);
target.addResource(fall_ip, 0x24UL);
target.addResource(high_ie, 0x28UL);
target.addResource(high_ip, 0x2cUL);
target.addResource(low_ie, 0x30UL);
target.addResource(low_ip, 0x34UL);
target.addResource(iof_en, 0x38UL);
target.addResource(iof_sel, 0x3cUL);
target.addResource(out_xor, 0x40UL);
}
#endif // _GPIO_REGS_H_

104
riscv/incl/sysc/SiFive/gen/plic_regs.h
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@ -1,104 +0,0 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Created on: Wed Sep 20 22:30:45 CEST 2017
// * plic_regs.h Author: <RDL Generator>
//
////////////////////////////////////////////////////////////////////////////////
#ifndef _PLIC_REGS_H_
#define _PLIC_REGS_H_
#include <sysc/utilities.h>
#include <util/bit_field.h>
#include <sysc/register.h>
#include <sysc/tlm_target.h>
namespace sysc {
class plic_regs :
public sc_core::sc_module,
public sysc::resetable
{
protected:
// storage declarations
BEGIN_BF_DECL(priority_t, uint32_t);
BF_FIELD(priority, 0, 3);
END_BF_DECL() ;
std::array<priority_t, 255> r_priority;
uint32_t r_pending;
uint32_t r_enabled;
BEGIN_BF_DECL(threshold_t, uint32_t);
BF_FIELD(threshold, 0, 3);
END_BF_DECL() r_threshold;
uint32_t r_claim_complete;
// register declarations
sysc::sc_register_indexed<priority_t, 255> priority;
sysc::sc_register<uint32_t> pending;
sysc::sc_register<uint32_t> enabled;
sysc::sc_register<threshold_t> threshold;
sysc::sc_register<uint32_t> claim_complete;
public:
plic_regs(sc_core::sc_module_name nm);
template<unsigned BUSWIDTH=32>
void registerResources(sysc::tlm_target<BUSWIDTH>& target);
};
}
//////////////////////////////////////////////////////////////////////////////
// member functions
//////////////////////////////////////////////////////////////////////////////
inline sysc::plic_regs::plic_regs(sc_core::sc_module_name nm)
: sc_core::sc_module(nm)
, NAMED(priority, r_priority, 0, *this)
, NAMED(pending, r_pending, 0, *this)
, NAMED(enabled, r_enabled, 0, *this)
, NAMED(threshold, r_threshold, 0, *this)
, NAMED(claim_complete, r_claim_complete, 0, *this)
{
}
template<unsigned BUSWIDTH>
inline void sysc::plic_regs::registerResources(sysc::tlm_target<BUSWIDTH>& target) {
target.addResource(priority, 0x4UL);
target.addResource(pending, 0x1000UL);
target.addResource(enabled, 0x2000UL);
target.addResource(threshold, 0xc200000UL);
target.addResource(claim_complete, 0xc200004UL);
}
#endif // _PLIC_REGS_H_

199
riscv/incl/sysc/SiFive/gen/spi_regs.h
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@ -1,199 +0,0 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Created on: Wed Sep 20 22:30:45 CEST 2017
// * spi_regs.h Author: <RDL Generator>
//
////////////////////////////////////////////////////////////////////////////////
#ifndef _SPI_REGS_H_
#define _SPI_REGS_H_
#include <sysc/utilities.h>
#include <util/bit_field.h>
#include <sysc/register.h>
#include <sysc/tlm_target.h>
namespace sysc {
class spi_regs :
public sc_core::sc_module,
public sysc::resetable
{
protected:
// storage declarations
BEGIN_BF_DECL(sckdiv_t, uint32_t);
BF_FIELD(div, 0, 12);
END_BF_DECL() r_sckdiv;
BEGIN_BF_DECL(sckmode_t, uint32_t);
BF_FIELD(pha, 0, 1);
BF_FIELD(pol, 1, 1);
END_BF_DECL() r_sckmode;
uint32_t r_csid;
uint32_t r_csdef;
BEGIN_BF_DECL(csmode_t, uint32_t);
BF_FIELD(mode, 0, 2);
END_BF_DECL() r_csmode;
BEGIN_BF_DECL(delay0_t, uint32_t);
BF_FIELD(cssck, 0, 8);
BF_FIELD(sckcs, 16, 8);
END_BF_DECL() r_delay0;
BEGIN_BF_DECL(delay1_t, uint32_t);
BF_FIELD(intercs, 0, 16);
BF_FIELD(interxfr, 16, 8);
END_BF_DECL() r_delay1;
BEGIN_BF_DECL(fmt_t, uint32_t);
BF_FIELD(proto, 0, 2);
BF_FIELD(endian, 2, 1);
BF_FIELD(dir, 3, 1);
BF_FIELD(len, 16, 4);
END_BF_DECL() r_fmt;
BEGIN_BF_DECL(txdata_t, uint32_t);
BF_FIELD(data, 0, 8);
BF_FIELD(full, 31, 1);
END_BF_DECL() r_txdata;
BEGIN_BF_DECL(rxdata_t, uint32_t);
BF_FIELD(data, 0, 8);
BF_FIELD(empty, 31, 1);
END_BF_DECL() r_rxdata;
BEGIN_BF_DECL(txmark_t, uint32_t);
BF_FIELD(txmark, 0, 3);
END_BF_DECL() r_txmark;
BEGIN_BF_DECL(rxmark_t, uint32_t);
BF_FIELD(rxmark, 0, 3);
END_BF_DECL() r_rxmark;
BEGIN_BF_DECL(fctrl_t, uint32_t);
BF_FIELD(en, 0, 1);
END_BF_DECL() r_fctrl;
BEGIN_BF_DECL(ffmt_t, uint32_t);
BF_FIELD(cmd_en, 0, 1);
BF_FIELD(addr_len, 1, 2);
BF_FIELD(pad_cnt, 3, 4);
BF_FIELD(cmd_proto, 7, 2);
BF_FIELD(addr_proto, 9, 2);
BF_FIELD(data_proto, 11, 2);
BF_FIELD(cmd_code, 16, 8);
BF_FIELD(pad_code, 24, 8);
END_BF_DECL() r_ffmt;
BEGIN_BF_DECL(ie_t, uint32_t);
BF_FIELD(txwm, 0, 1);
BF_FIELD(rxwm, 1, 1);
END_BF_DECL() r_ie;
BEGIN_BF_DECL(ip_t, uint32_t);
BF_FIELD(txwm, 0, 1);
BF_FIELD(rxwm, 1, 1);
END_BF_DECL() r_ip;
// register declarations
sysc::sc_register<sckdiv_t> sckdiv;
sysc::sc_register<sckmode_t> sckmode;
sysc::sc_register<uint32_t> csid;
sysc::sc_register<uint32_t> csdef;
sysc::sc_register<csmode_t> csmode;
sysc::sc_register<delay0_t> delay0;
sysc::sc_register<delay1_t> delay1;
sysc::sc_register<fmt_t> fmt;
sysc::sc_register<txdata_t> txdata;
sysc::sc_register<rxdata_t> rxdata;
sysc::sc_register<txmark_t> txmark;
sysc::sc_register<rxmark_t> rxmark;
sysc::sc_register<fctrl_t> fctrl;
sysc::sc_register<ffmt_t> ffmt;
sysc::sc_register<ie_t> ie;
sysc::sc_register<ip_t> ip;
public:
spi_regs(sc_core::sc_module_name nm);
template<unsigned BUSWIDTH=32>
void registerResources(sysc::tlm_target<BUSWIDTH>& target);
};
}
//////////////////////////////////////////////////////////////////////////////
// member functions
//////////////////////////////////////////////////////////////////////////////
inline sysc::spi_regs::spi_regs(sc_core::sc_module_name nm)
: sc_core::sc_module(nm)
, NAMED(sckdiv, r_sckdiv, 0, *this)
, NAMED(sckmode, r_sckmode, 0, *this)
, NAMED(csid, r_csid, 0, *this)
, NAMED(csdef, r_csdef, 0, *this)
, NAMED(csmode, r_csmode, 0, *this)
, NAMED(delay0, r_delay0, 0, *this)
, NAMED(delay1, r_delay1, 0, *this)
, NAMED(fmt, r_fmt, 0, *this)
, NAMED(txdata, r_txdata, 0, *this)
, NAMED(rxdata, r_rxdata, 0, *this)
, NAMED(txmark, r_txmark, 0, *this)
, NAMED(rxmark, r_rxmark, 0, *this)
, NAMED(fctrl, r_fctrl, 0, *this)
, NAMED(ffmt, r_ffmt, 0, *this)
, NAMED(ie, r_ie, 0, *this)
, NAMED(ip, r_ip, 0, *this)
{
}
template<unsigned BUSWIDTH>
inline void sysc::spi_regs::registerResources(sysc::tlm_target<BUSWIDTH>& target) {
target.addResource(sckdiv, 0x0UL);
target.addResource(sckmode, 0x4UL);
target.addResource(csid, 0x10UL);
target.addResource(csdef, 0x14UL);
target.addResource(csmode, 0x18UL);
target.addResource(delay0, 0x28UL);
target.addResource(delay1, 0x2cUL);
target.addResource(fmt, 0x40UL);
target.addResource(txdata, 0x48UL);
target.addResource(rxdata, 0x4cUL);
target.addResource(txmark, 0x50UL);
target.addResource(rxmark, 0x54UL);
target.addResource(fctrl, 0x60UL);
target.addResource(ffmt, 0x64UL);
target.addResource(ie, 0x70UL);
target.addResource(ip, 0x74UL);
}
#endif // _SPI_REGS_H_

132
riscv/incl/sysc/SiFive/gen/uart_regs.h
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@ -1,132 +0,0 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Created on: Wed Sep 20 22:30:45 CEST 2017
// * uart_regs.h Author: <RDL Generator>
//
////////////////////////////////////////////////////////////////////////////////
#ifndef _UART_REGS_H_
#define _UART_REGS_H_
#include <sysc/utilities.h>
#include <util/bit_field.h>
#include <sysc/register.h>
#include <sysc/tlm_target.h>
namespace sysc {
class uart_regs :
public sc_core::sc_module,
public sysc::resetable
{
protected:
// storage declarations
BEGIN_BF_DECL(txdata_t, uint32_t);
BF_FIELD(data, 0, 8);
BF_FIELD(full, 31, 1);
END_BF_DECL() r_txdata;
BEGIN_BF_DECL(rxdata_t, uint32_t);
BF_FIELD(data, 0, 8);
BF_FIELD(empty, 31, 1);
END_BF_DECL() r_rxdata;
BEGIN_BF_DECL(txctrl_t, uint32_t);
BF_FIELD(txen, 0, 1);
BF_FIELD(nstop, 1, 1);
BF_FIELD(reserved, 2, 14);
BF_FIELD(txcnt, 16, 3);
END_BF_DECL() r_txctrl;
BEGIN_BF_DECL(rxctrl_t, uint32_t);
BF_FIELD(rxen, 0, 1);
BF_FIELD(reserved, 1, 15);
BF_FIELD(rxcnt, 16, 3);
END_BF_DECL() r_rxctrl;
BEGIN_BF_DECL(ie_t, uint32_t);
BF_FIELD(txwm, 0, 1);
BF_FIELD(rxwm, 1, 1);
END_BF_DECL() r_ie;
BEGIN_BF_DECL(ip_t, uint32_t);
BF_FIELD(txwm, 0, 1);
BF_FIELD(rxwm, 1, 1);
END_BF_DECL() r_ip;
BEGIN_BF_DECL(div_t, uint32_t);
BF_FIELD(div, 0, 16);
END_BF_DECL() r_div;
// register declarations
sysc::sc_register<txdata_t> txdata;
sysc::sc_register<rxdata_t> rxdata;
sysc::sc_register<txctrl_t> txctrl;
sysc::sc_register<rxctrl_t> rxctrl;
sysc::sc_register<ie_t> ie;
sysc::sc_register<ip_t> ip;
sysc::sc_register<div_t> div;
public:
uart_regs(sc_core::sc_module_name nm);
template<unsigned BUSWIDTH=32>
void registerResources(sysc::tlm_target<BUSWIDTH>& target);
};
}
//////////////////////////////////////////////////////////////////////////////
// member functions
//////////////////////////////////////////////////////////////////////////////
inline sysc::uart_regs::uart_regs(sc_core::sc_module_name nm)
: sc_core::sc_module(nm)
, NAMED(txdata, r_txdata, 0, *this)
, NAMED(rxdata, r_rxdata, 0, *this)
, NAMED(txctrl, r_txctrl, 0, *this)
, NAMED(rxctrl, r_rxctrl, 0, *this)
, NAMED(ie, r_ie, 0, *this)
, NAMED(ip, r_ip, 0, *this)
, NAMED(div, r_div, 0, *this)
{
}
template<unsigned BUSWIDTH>
inline void sysc::uart_regs::registerResources(sysc::tlm_target<BUSWIDTH>& target) {
target.addResource(txdata, 0x0UL);
target.addResource(rxdata, 0x4UL);
target.addResource(txctrl, 0x8UL);
target.addResource(rxctrl, 0xcUL);
target.addResource(ie, 0x10UL);
target.addResource(ip, 0x14UL);
target.addResource(div, 0x18UL);
}
#endif // _UART_REGS_H_

42
riscv/incl/sysc/SiFive/gpio.h
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@ -1,42 +0,0 @@
/*******************************************************************************
* Copyright 2017 eyck@minres.com
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may not
* use this file except in compliance with the License. You may obtain a copy
* of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations under
* the License.
******************************************************************************/
#ifndef _GPIO_H_
#define _GPIO_H_
#include <sysc/tlm_target.h>
namespace sysc {
class gpio_regs;
class gpio: public sc_core::sc_module, public tlm_target<> {
public:
SC_HAS_PROCESS(gpio);
sc_core::sc_in<sc_core::sc_time> clk_i;
sc_core::sc_in<bool> rst_i;
gpio(sc_core::sc_module_name nm);
virtual ~gpio();
protected:
void clock_cb();
void reset_cb();
sc_core::sc_time clk;
std::unique_ptr<gpio_regs> regs;
};
} /* namespace sysc */
#endif /* _GPIO_H_ */

62
riscv/incl/sysc/SiFive/platform.h
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@ -1,62 +0,0 @@
/*******************************************************************************
* Copyright 2017 eyck@minres.com
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may not
* use this file except in compliance with the License. You may obtain a copy
* of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations under
* the License.
******************************************************************************/
/*
* simplesystem.h
*
* Created on: 17.09.2017
* Author: eyck@minres.com
*/
#ifndef SIMPLESYSTEM_H_
#define SIMPLESYSTEM_H_
#include "uart.h"
#include "spi.h"
#include "gpio.h"
#include "plic.h"
#include <sysc/router.h>
#include <sysc/kernel/sc_module.h>
#include <array>
#include "core_complex.h"
namespace sysc {
class platform: public sc_core::sc_module {
public:
SC_HAS_PROCESS(platform);
SiFive::core_complex i_master;
router<> i_router;
uart i_uart;
spi i_spi;
gpio i_gpio;
plic i_plic;
sc_core::sc_signal<sc_core::sc_time> s_clk;
sc_core::sc_signal<bool> s_rst;
platform(sc_core::sc_module_name nm);
protected:
void gen_reset();
#include "gen/e300_plat_t.h"
};
} /* namespace sysc */
#endif /* SIMPLESYSTEM_H_ */

42
riscv/incl/sysc/SiFive/plic.h
View File

@ -1,42 +0,0 @@
/*******************************************************************************
* Copyright 2017 eyck@minres.com
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may not
* use this file except in compliance with the License. You may obtain a copy
* of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations under
* the License.
******************************************************************************/
#ifndef _PLIC_H_
#define _PLIC_H_
#include <sysc/tlm_target.h>
namespace sysc {
class plic_regs;
class plic: public sc_core::sc_module, public tlm_target<> {
public:
SC_HAS_PROCESS(plic);
sc_core::sc_in<sc_core::sc_time> clk_i;
sc_core::sc_in<bool> rst_i;
plic(sc_core::sc_module_name nm);
virtual ~plic();
protected:
void clock_cb();
void reset_cb();
sc_core::sc_time clk;
std::unique_ptr<plic_regs> regs;
};
} /* namespace sysc */
#endif /* _PLIC_H_ */

42
riscv/incl/sysc/SiFive/spi.h
View File

@ -1,42 +0,0 @@
/*******************************************************************************
* Copyright 2017 eyck@minres.com
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may not
* use this file except in compliance with the License. You may obtain a copy
* of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations under
* the License.
******************************************************************************/
#ifndef _SPI_H_
#define _SPI_H_
#include <sysc/tlm_target.h>
namespace sysc {
class spi_regs;
class spi: public sc_core::sc_module, public tlm_target<> {
public:
SC_HAS_PROCESS(spi);
sc_core::sc_in<sc_core::sc_time> clk_i;
sc_core::sc_in<bool> rst_i;
spi(sc_core::sc_module_name nm);
virtual ~spi();
protected:
void clock_cb();
void reset_cb();
sc_core::sc_time clk;
std::unique_ptr<spi_regs> regs;
};
} /* namespace sysc */
#endif /* _SPI_H_ */

42
riscv/incl/sysc/SiFive/uart.h
View File

@ -1,42 +0,0 @@
/*******************************************************************************
* Copyright 2017 eyck@minres.com
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may not
* use this file except in compliance with the License. You may obtain a copy
* of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations under
* the License.
******************************************************************************/
#ifndef _UART_H_
#define _UART_H_
#include <sysc/tlm_target.h>
namespace sysc {
class uart_regs;
class uart: public sc_core::sc_module, public tlm_target<> {
public:
SC_HAS_PROCESS(uart);
sc_core::sc_in<sc_core::sc_time> clk_i;
sc_core::sc_in<bool> rst_i;
uart(sc_core::sc_module_name nm);
virtual ~uart();
protected:
void clock_cb();
void reset_cb();
sc_core::sc_time clk;
std::unique_ptr<uart_regs> regs;
};
} /* namespace sysc */
#endif /* _UART_H_ */

37
riscv/plic.rdl
View File

@ -1,37 +0,0 @@
regfile plic_regs {
reg {
name="priority";
desc="interrupt source priority";
field {
name = "priority";
} priority[2:0];
} priority[255] @0x004;
reg {
name="pending";
desc="pending irq";
field {
name = "pending";
} pending[31:0];
} pending @0x1000;
reg {
name="enabled";
desc="enabled interrupts";
field {
name = "enabled";
} enabled[31:0];
} enabled @0x2000;
reg {
name="threshold";
desc="interrupt priority threshold";
field {
name = "threshold";
} \threshold[2:0];
} \threshold @0x0C200000;
reg {
name="claim/complete";
desc="interrupt handling completed";
field {
name = "interrupt_claimed";
} interrupt_claimed[31:0];
} claim_complete @0x0C200004;
};

17
riscv/src/CMakeLists.txt
View File

@ -6,21 +6,14 @@ set(LIB_SOURCES
iss/rv64ia.cpp
internal/vm_rv32imac.cpp
internal/vm_rv64ia.cpp
sysc/core_complex.cpp
sysc/gpio.cpp
sysc/plic.cpp
sysc/platform.cpp
sysc/spi.cpp
sysc/uart.cpp
)
set(APP_HEADERS )
set(APP_SOURCES main.cpp sc_main.cpp
)
set(APP_SOURCES main.cpp)
# Define two variables in order not to repeat ourselves.
set(LIBRARY_NAME riscv)
set(LIBRARY_NAME risc-v)
# Define the library
add_library(${LIBRARY_NAME} ${LIB_SOURCES})
@ -32,7 +25,7 @@ set_target_properties(${LIBRARY_NAME} PROPERTIES
)
# This is a make target, so you can do a "make riscv-sc"
set(APPLICATION_NAME riscv-sc)
set(APPLICATION_NAME riscv)
add_executable(${APPLICATION_NAME} ${APP_SOURCES})
@ -42,10 +35,6 @@ target_link_libraries(${APPLICATION_NAME} dbt-core)
target_link_libraries(${APPLICATION_NAME} sc-components)
target_link_libraries(${APPLICATION_NAME} external)
target_link_libraries(${APPLICATION_NAME} ${llvm_libs})
target_link_libraries(${APPLICATION_NAME} ${SystemC_LIBRARIES} )
if(SCV_FOUND)
target_link_libraries (${APPLICATION_NAME} ${SCV_LIBRARIES})
endif()
target_link_libraries(${APPLICATION_NAME} ${Boost_LIBRARIES} )
# Says how and where to install software

190
riscv/src/internal/vm_rv32imac.cpp
View File

@ -227,13 +227,13 @@ protected:
inline
llvm::Value* gen_reg_load(unsigned i, unsigned level=0){
if(level){
// if(level){
return this->builder->CreateLoad(get_reg_ptr(i), false);
} else {
if(!this->loaded_regs[i])
this->loaded_regs[i]=this->builder->CreateLoad(get_reg_ptr(i), false);
return this->loaded_regs[i];
}
// } else {
// if(!this->loaded_regs[i])
// this->loaded_regs[i]=this->builder->CreateLoad(get_reg_ptr(i), false);
// return this->loaded_regs[i];
// }
}
inline
@ -523,7 +523,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("LUI x%1$d, 0x%2$05x");
ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -556,7 +556,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("AUIPC x%1%, 0x%2$08x");
ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -591,7 +591,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("JAL x%1$d, 0x%2$x");
ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -629,7 +629,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("JALR x%1$d, x%2$d, 0x%3$x");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -670,7 +670,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("BEQ x%1$d, x%2$d, 0x%3$x");
ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -711,7 +711,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("BNE x%1$d, x%2$d, 0x%3$x");
ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -752,7 +752,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("BLT x%1$d, x%2$d, 0x%3$x");
ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -797,7 +797,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("BGE x%1$d, x%2$d, 0x%3$x");
ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -842,7 +842,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("BLTU x%1$d, x%2$d, 0x%3$x");
ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -883,7 +883,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("BGEU x%1$d, x%2$d, 0x%3$x");
ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -924,7 +924,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("LB x%1$d, %2%(x%3$d)");
ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -964,7 +964,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("LH x%1$d, %2%(x%3$d)");
ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -1004,7 +1004,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("LW x%1$d, %2%(x%3$d)");
ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -1044,7 +1044,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("LBU x%1$d, %2%(x%3$d)");
ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -1084,7 +1084,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("LHU x%1$d, %2%(x%3$d)");
ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -1124,7 +1124,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("SB x%1$d, %2%(x%3$d)");
ins_fmter % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -1162,7 +1162,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("SH x%1$d, %2%(x%3$d)");
ins_fmter % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -1200,7 +1200,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("SW x%1$d, %2%(x%3$d)");
ins_fmter % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -1238,7 +1238,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("ADDI x%1$d, x%2$d, %3%");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -1274,7 +1274,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("SLTI x%1$d, x%2$d, %3%");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -1319,7 +1319,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("SLTIU x%1$d, x%2$d, %3%");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -1365,7 +1365,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("XORI x%1$d, x%2$d, %3%");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -1401,7 +1401,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("ORI x%1$d, x%2$d, %3%");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -1437,7 +1437,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("ANDI x%1$d, x%2$d, %3%");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -1473,7 +1473,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("SLLI x%1$d, x%2$d, %3%");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_shamt_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -1509,7 +1509,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("SRLI x%1$d, x%2$d, %3%");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_shamt_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -1545,7 +1545,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("SRAI x%1$d, x%2$d, %3%");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_shamt_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -1581,7 +1581,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("ADD x%1$d, x%2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -1617,7 +1617,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("SUB x%1$d, x%2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -1653,7 +1653,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("SLL x%1$d, x%2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -1691,7 +1691,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("SLT x%1$d, x%2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -1736,7 +1736,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("SLTU x%1$d, x%2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -1783,7 +1783,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("XOR x%1$d, x%2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -1819,7 +1819,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("SRL x%1$d, x%2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -1857,7 +1857,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("SRA x%1$d, x%2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -1895,7 +1895,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("OR x%1$d, x%2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -1931,7 +1931,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("AND x%1$d, x%2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -2235,7 +2235,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("CSRRW x%1$d, %2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_csr_val % (uint64_t)fld_rs1_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -2282,7 +2282,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("CSRRS x%1$d, %2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_csr_val % (uint64_t)fld_rs1_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -2327,7 +2327,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("CSRRC x%1$d, %2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_csr_val % (uint64_t)fld_rs1_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -2372,7 +2372,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("CSRRWI x%1$d, %2$d, 0x%3$x");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_csr_val % (uint64_t)fld_zimm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -2414,7 +2414,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("CSRRSI x%1$d, %2$d, 0x%3$x");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_csr_val % (uint64_t)fld_zimm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -2461,7 +2461,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("CSRRCI x%1$d, %2$d, 0x%3$x");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_csr_val % (uint64_t)fld_zimm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -2508,7 +2508,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("MUL x%1$d, x%2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -2554,7 +2554,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("MULH x%1$d, x%2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -2602,7 +2602,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("MULHSU x%1$d, x%2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -2650,7 +2650,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("MULHU x%1$d, x%2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -2698,7 +2698,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("DIV x%1$d, x%2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -2762,7 +2762,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("DIVU x%1$d, x%2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -2826,7 +2826,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("REM x%1$d, x%2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -2890,7 +2890,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("REMU x%1$d, x%2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -2955,7 +2955,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("LR.W x%1$d, x%2$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -3003,7 +3003,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("SC.W x%1$d, x%2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -3068,7 +3068,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("AMOSWAP.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -3113,7 +3113,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("AMOADD.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -3162,7 +3162,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("AMOXOR.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -3211,7 +3211,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("AMOAND.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -3260,7 +3260,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("AMOOR.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -3309,7 +3309,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("AMOMIN.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -3367,7 +3367,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("AMOMAX.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -3425,7 +3425,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("AMOMINU.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -3479,7 +3479,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("AMOMAXU.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -3534,7 +3534,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.ADDI4SPN x%1$d, 0x%2$05x");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_nzuimm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -3573,7 +3573,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.LW x(8+%1$d), x(8+%2$d), 0x%3$05x");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_uimm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -3610,7 +3610,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.SW x(8+%1$d), x(8+%2$d), 0x%3$05x");
ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_uimm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -3648,7 +3648,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.NOP ");
ins_fmter ;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -3678,7 +3678,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.ADDI x%1$d, 0x%2$05x");
ins_fmter % (uint64_t)fld_rs1_val % (int64_t)fld_nzimm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -3713,7 +3713,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.JAL 0x%1$05x");
ins_fmter % (int64_t)fld_imm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -3749,7 +3749,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.LI x%1$d, 0x%2$05x");
ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -3783,7 +3783,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.LUI x%1$d, 0x%2$05x");
ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_nzimm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -3822,7 +3822,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.ADDI16SP 0x%1$05x");
ins_fmter % (int64_t)fld_nzimm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -3858,7 +3858,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.SRLI x(8+%1$d), %2$d");
ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_shamt_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -3895,7 +3895,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.SRAI x(8+%1$d), %2$d");
ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_shamt_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -3932,7 +3932,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.ANDI x(8+%1$d), 0x%2$05x");
ins_fmter % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -3966,7 +3966,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.SUB x(8+%1$d), x(8+%2$d)");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -4001,7 +4001,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.XOR x(8+%1$d), x(8+%2$d)");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -4036,7 +4036,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.OR x(8+%1$d), x(8+%2$d)");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -4071,7 +4071,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.AND x(8+%1$d), x(8+%2$d)");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -4105,7 +4105,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.J 0x%1$05x");
ins_fmter % (int64_t)fld_imm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -4136,7 +4136,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.BEQZ x(8+%1$d), 0x%2$05x");
ins_fmter % (uint64_t)fld_rs1d_val % (int64_t)fld_imm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -4177,7 +4177,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.BNEZ x(8+%1$d),, 0x%2$05x");
ins_fmter % (uint64_t)fld_rs1d_val % (uint64_t)fld_imm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -4218,7 +4218,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.SLLI x%1$d, %2$d");
ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_shamt_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -4286,7 +4286,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.LWSP x%1$d, sp, 0x%2$05x");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_uimm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -4321,7 +4321,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.MV x%1$d, x%2$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -4351,7 +4351,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.JR x%1$d");
ins_fmter % (uint64_t)fld_rs1_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -4406,7 +4406,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.ADD x%1$d, x%2$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -4438,7 +4438,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.JALR x%1$d");
ins_fmter % (uint64_t)fld_rs1_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -4472,7 +4472,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.SWSP x2+0x%1$05x, x%2$d");
ins_fmter % (uint64_t)fld_uimm_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -4591,7 +4591,7 @@ void vm_impl<ARCH>::gen_leave_behavior(llvm::BasicBlock* leave_blk){
template<typename ARCH>
void vm_impl<ARCH>::gen_raise_trap(uint16_t trap_id, uint16_t cause){
auto* TRAP_val = this->gen_const(traits<ARCH>::XLEN, 0x80<<24| (cause<<16) | trap_id );
auto* TRAP_val = this->gen_const(32, 0x80<<24| (cause<<16) | trap_id );
this->builder->CreateStore(TRAP_val, get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
}

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riscv/src/internal/vm_rv64ia.cpp Normal file
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63
riscv/src/sysc/core_complex.cpp → riscv/src/iss/rv64ia.cpp
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@ -1,21 +1,21 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved.
//
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
//
// 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@ -27,29 +27,50 @@
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Contributors:
// eyck@minres.com - initial API and implementation
//
//
// Created on: Tue Sep 05 18:57:24 CEST 2017
// * rv64ia.cpp Author: <CoreDSL Generator>
//
////////////////////////////////////////////////////////////////////////////////
#include <sysc/SiFive/core_complex.h>
#include "util/ities.h"
#include <util/logging.h>
namespace sysc {
namespace SiFive {
#include <elfio/elfio.hpp>
#include <iss/arch/rv64ia.h>
core_complex::core_complex(sc_core::sc_module_name name)
:sc_core::sc_module(name)
, NAMED(initiator)
, NAMED(rst_i){
// TODO Auto-generated constructor stub
#ifdef __cplusplus
extern "C" {
#endif
#include <ihex.h>
#ifdef __cplusplus
}
#endif
#include <fstream>
#include <cstdio>
#include <cstring>
using namespace iss::arch;
rv64ia::rv64ia() {
reg.icount=0;
}
core_complex::~core_complex() {
// TODO Auto-generated destructor stub
rv64ia::~rv64ia(){
}
} /* namespace SiFive */
} /* namespace sysc */
void rv64ia::reset(uint64_t address) {
for(size_t i=0; i<traits<rv64ia>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<rv64ia>::reg_t),0));
reg.PC=address;
reg.NEXT_PC=reg.PC;
reg.trap_state=0;
reg.machine_state=0x0;
}
uint8_t* rv64ia::get_regs_base_ptr(){
return reinterpret_cast<uint8_t*>(&reg);
}
rv64ia::phys_addr_t rv64ia::v2p(const iss::addr_t& pc) {
return phys_addr_t(pc); //change logical address to physical address
}

76
riscv/src/main.cpp
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@ -40,9 +40,6 @@
#include <iss/arch/rv32imac.h>
#include <iss/arch/rv64ia.h>
#include <iss/jit/MCJIThelper.h>
#ifdef WITH_SYSTEMC
#include <sysc/kernel/sc_externs.h>
#endif
#include <boost/lexical_cast.hpp>
namespace po= boost::program_options;
@ -55,52 +52,43 @@ int main(int argc, char *argv[]) {
if(parse_cli_options(vm, argc, argv)) return ERROR_IN_COMMAND_LINE;
configure_default_logger(vm);
// configure the connection logger
configure_debugger_logger();
configure_debugger_logger();
// application code comes here //
iss::init_jit(argc, argv);
if(vm.count("systemc")){
#ifdef WITH_SYSTEMC
return sc_core::sc_elab_and_sim(argc, argv);
#else
std::cerr<<"SystemC simulation is currently not supported, please rebuild with -DWITH_SYSTEMC"<<std::endl;
#endif
bool dump=vm.count("dump-ir");
// instantiate the simulator
std::unique_ptr<iss::vm_if> cpu = nullptr;
if(vm.count("rv64")==1){
if(vm.count("gdb-port")==1)
cpu = iss::create<iss::arch::rv64ia>("rv64ia", vm["gdb-port"].as<unsigned>(), dump);
else
cpu = iss::create<iss::arch::rv64ia>("rv64ia", dump);
} else {
bool dump=vm.count("dump-ir");
// instantiate the simulator
std::unique_ptr<iss::vm_if> cpu = nullptr;
if(vm.count("rv64")==1){
if(vm.count("gdb-port")==1)
cpu = iss::create<iss::arch::rv64ia>("rv64ia", vm["gdb-port"].as<unsigned>(), dump);
else
cpu = iss::create<iss::arch::rv64ia>("rv64ia", dump);
} else {
if(vm.count("gdb-port")==1)
cpu = iss::create<iss::arch::rv32imac>("rv32ima", vm["gdb-port"].as<unsigned>(), dump);
else
cpu = iss::create<iss::arch::rv32imac>("rv32ima", dump);
}
if(vm.count("elf")){
for(std::string input: vm["elf"].as<std::vector<std::string> >())
cpu->get_arch()->load_file(input);
} else if(vm.count("mem")){
cpu->get_arch()->load_file(vm["mem"].as<std::string>() , iss::arch::traits<iss::arch::rv32imac>::MEM);
} //else
// LOG(FATAL)<<"At least one (flash-)input file (ELF or IHEX) needs to be specified";
configure_disass_logger(vm);
if(vm.count("disass")){
cpu->setDisassEnabled(true);
}
if(vm.count("reset")){
auto str = vm["reset"].as<std::string>();
auto start_address = str.find("0x")==0? std::stoull(str, 0, 16):std::stoull(str, 0, 10);
cpu->reset(start_address);
} else {
cpu->reset();
}
return cpu->start(vm["cycles"].as<int64_t>());
if(vm.count("gdb-port")==1)
cpu = iss::create<iss::arch::rv32imac>("rv32ima", vm["gdb-port"].as<unsigned>(), dump);
else
cpu = iss::create<iss::arch::rv32imac>("rv32ima", dump);
}
if(vm.count("elf")){
for(std::string input: vm["elf"].as<std::vector<std::string> >())
cpu->get_arch()->load_file(input);
} else if(vm.count("mem")){
cpu->get_arch()->load_file(vm["mem"].as<std::string>() , iss::arch::traits<iss::arch::rv32imac>::MEM);
}
configure_disass_logger(vm);
if(vm.count("disass")){
cpu->setDisassEnabled(true);
}
if(vm.count("reset")){
auto str = vm["reset"].as<std::string>();
auto start_address = str.find("0x")==0? std::stoull(str, 0, 16):std::stoull(str, 0, 10);
cpu->reset(start_address);
} else {
cpu->reset();
}
return cpu->start(vm["cycles"].as<int64_t>());
} catch(std::exception& e){
LOG(logging::ERROR) << "Unhandled Exception reached the top of main: "
<< e.what() << ", application will now exit" << std::endl;

83
riscv/src/sc_main.cpp
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@ -1,83 +0,0 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright 2017 eyck@minres.com
//
// Licensed under the Apache License, Version 2.0 (the "License"); you may not
// use this file except in compliance with the License. You may obtain a copy
// of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
// License for the specific language governing permissions and limitations under
// the License.
////////////////////////////////////////////////////////////////////////////////
/*
* sc_main.cpp
*
* Created on: 17.09.2017
* Author: eyck@minres.com
*/
#include <sysc/tracer.h>
#include <sysc/scv_tr_db.h>
#include <sr_report/sr_report.h>
#include <boost/program_options.hpp>
#include <sysc/report.h>
#include <sstream>
#include <sysc/SiFive/platform.h>
using namespace sysc;
namespace po = boost::program_options;
namespace {
const size_t ERROR_IN_COMMAND_LINE = 1;
const size_t SUCCESS = 0;
const size_t ERROR_UNHANDLED_EXCEPTION = 2;
} // namespace
int sc_main(int argc, char* argv[]){
// sc_report_handler::set_handler(my_report_handler);
sysc::Logger::reporting_level()=log::DEBUG;
///////////////////////////////////////////////////////////////////////////
// CLI argument parsing
///////////////////////////////////////////////////////////////////////////
po::options_description desc("Options");\
desc.add_options()\
("help,h", "Print help message")\
("debug,d", po::value<int>(), "set debug level")\
("trace,t", "trace SystemC signals");
po::variables_map vm;
try {
po::store(po::parse_command_line(argc, argv, desc), vm); // can throw
// --help option
if ( vm.count("help") ){
std::cout << "JIT-ISS simulator for AVR" << std::endl << desc << std::endl;
return SUCCESS;
}
po::notify(vm); // throws on error, so do after help in case
// there are any problems
} catch(po::error& e){
std::cerr << "ERROR: " << e.what() << std::endl << std::endl;
std::cerr << desc << std::endl;
return ERROR_IN_COMMAND_LINE;
}
///////////////////////////////////////////////////////////////////////////
// set up tracing & transaction recording
///////////////////////////////////////////////////////////////////////////
sysc::tracer trace("simple_system", sysc::tracer::TEXT, vm.count("trace"));
///////////////////////////////////////////////////////////////////////////
// instantiate top level
///////////////////////////////////////////////////////////////////////////
platform i_simple_system("i_simple_system");
//sr_report_handler::add_sc_object_to_filter(&i_simple_system.i_master, sc_core::SC_WARNING, sc_core::SC_MEDIUM);
///////////////////////////////////////////////////////////////////////////
// run simulation
///////////////////////////////////////////////////////////////////////////
sc_start(sc_core::sc_time(100, sc_core::SC_NS));
if(!sc_end_of_simulation_invoked()) sc_stop();
return 0;
}

50
riscv/src/sysc/gpio.cpp
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@ -1,50 +0,0 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright 2017 eyck@minres.com
//
// Licensed under the Apache License, Version 2.0 (the "License"); you may not
// use this file except in compliance with the License. You may obtain a copy
// of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
// License for the specific language governing permissions and limitations under
// the License.
////////////////////////////////////////////////////////////////////////////////
#include "sysc/SiFive/gpio.h"
#include "sysc/SiFive/gen/gpio_regs.h"
#include "sysc/utilities.h"
namespace sysc {
gpio::gpio(sc_core::sc_module_name nm)
: sc_core::sc_module(nm)
, tlm_target<>(clk)
, NAMED(clk_i)
, NAMED(rst_i)
, NAMEDD(gpio_regs, regs)
{
regs->registerResources(*this);
SC_METHOD(clock_cb);
sensitive<<clk_i;
SC_METHOD(reset_cb);
sensitive<<rst_i;
}
gpio::~gpio() {
}
void gpio::clock_cb() {
}
void gpio::reset_cb() {
if(rst_i.read())
regs->reset_start();
else
regs->reset_stop();
}
} /* namespace sysc */

66
riscv/src/sysc/platform.cpp
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@ -1,66 +0,0 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright 2017 eyck@minres.com
//
// Licensed under the Apache License, Version 2.0 (the "License"); you may not
// use this file except in compliance with the License. You may obtain a copy
// of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
// License for the specific language governing permissions and limitations under
// the License.
////////////////////////////////////////////////////////////////////////////////
/*
* simplesystem.cpp
*
* Created on: 17.09.2017
* Author: eyck@minres.com
*/
#include <sysc/SiFive/platform.h>
namespace sysc {
platform::platform(sc_core::sc_module_name nm)
: sc_core::sc_module(nm)
, NAMED(i_master)
, NAMED(i_router, 4, 1)
, NAMED(i_uart)
, NAMED(i_spi)
, NAMED(i_gpio)
, NAMED(i_plic)
, NAMED(s_clk)
, NAMED(s_rst)
{
i_master.initiator(i_router.target[0]);
size_t i=0;
for(const auto& e: e300_plat_map){
i_router.initiator.at(i)(e.target->socket);
i_router.add_target_range(i, e.start, e.size);
i++;
}
i_uart.clk_i(s_clk);
i_spi.clk_i(s_clk);
i_gpio.clk_i(s_clk);
i_plic.clk_i(s_clk);
s_clk.write(10_ns);
i_uart.rst_i(s_rst);
i_spi.rst_i(s_rst);
i_gpio.rst_i(s_rst);
i_plic.rst_i(s_rst);
i_master.rst_i(s_rst);
SC_THREAD(gen_reset);
}
void platform::gen_reset() {
s_rst=true;
wait(10_ns);
s_rst=false;
}
} /* namespace sysc */

51
riscv/src/sysc/plic.cpp
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@ -1,51 +0,0 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright 2017 eyck@minres.com
//
// Licensed under the Apache License, Version 2.0 (the "License"); you may not
// use this file except in compliance with the License. You may obtain a copy
// of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
// License for the specific language governing permissions and limitations under
// the License.
////////////////////////////////////////////////////////////////////////////////
#include "sysc/SiFive/plic.h"
#include "sysc/SiFive/gen/plic_regs.h"
#include "sysc/utilities.h"
namespace sysc {
plic::plic(sc_core::sc_module_name nm)
: sc_core::sc_module(nm)
, tlm_target<>(clk)
, NAMED(clk_i)
, NAMED(rst_i)
, NAMEDD(plic_regs, regs)
{
regs->registerResources(*this);
SC_METHOD(clock_cb);
sensitive<<clk_i;
SC_METHOD(reset_cb);
sensitive<<rst_i;
}
plic::~plic() {
}
void plic::clock_cb() {
this->clk=clk_i.read();
}
void plic::reset_cb() {
if(rst_i.read())
regs->reset_start();
else
regs->reset_stop();
}
} /* namespace sysc */

51
riscv/src/sysc/spi.cpp
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@ -1,51 +0,0 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright 2017 eyck@minres.com
//
// Licensed under the Apache License, Version 2.0 (the "License"); you may not
// use this file except in compliance with the License. You may obtain a copy
// of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
// License for the specific language governing permissions and limitations under
// the License.
////////////////////////////////////////////////////////////////////////////////
#include "sysc/SiFive/spi.h"
#include "sysc/SiFive/gen/spi_regs.h"
#include "sysc/utilities.h"
namespace sysc {
spi::spi(sc_core::sc_module_name nm)
: sc_core::sc_module(nm)
, tlm_target<>(clk)
, NAMED(clk_i)
, NAMED(rst_i)
, NAMEDD(spi_regs, regs)
{
regs->registerResources(*this);
SC_METHOD(clock_cb);
sensitive<<clk_i;
SC_METHOD(reset_cb);
sensitive<<rst_i;
}
spi::~spi() {
}
void spi::clock_cb() {
this->clk=clk_i.read();
}
void spi::reset_cb() {
if(rst_i.read())
regs->reset_start();
else
regs->reset_stop();
}
} /* namespace sysc */

51
riscv/src/sysc/uart.cpp
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@ -1,51 +0,0 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright 2017 eyck@minres.com
//
// Licensed under the Apache License, Version 2.0 (the "License"); you may not
// use this file except in compliance with the License. You may obtain a copy
// of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
// License for the specific language governing permissions and limitations under
// the License.
////////////////////////////////////////////////////////////////////////////////
#include "sysc/SiFive/uart.h"
#include "sysc/SiFive/gen/uart_regs.h"
#include "sysc/utilities.h"
namespace sysc {
uart::uart(sc_core::sc_module_name nm)
: sc_core::sc_module(nm)
, tlm_target<>(clk)
, NAMED(clk_i)
, NAMED(rst_i)
, NAMEDD(uart_regs, regs)
{
regs->registerResources(*this);
SC_METHOD(clock_cb);
sensitive<<clk_i;
SC_METHOD(reset_cb);
sensitive<<rst_i;
}
uart::~uart() {
}
void uart::clock_cb() {
this->clk=clk_i.read();
}
void uart::reset_cb() {
if(rst_i.read())
regs->reset_start();
else
regs->reset_stop();
}
} /* namespace sysc */