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Added SystemC version of HiFive FE310

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This commit is contained in:
Eyck Jentzsch
2017-10-04 10:31:11 +02:00
parent d8184abbcc
commit 4867cca187
43 changed files with 1632 additions and 537 deletions
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15
riscv/src/internal/vm_riscv.in.cpp
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@ -342,21 +342,8 @@ template <>
std::unique_ptr<vm_if> create<arch::CORE_DEF_NAME>(arch::CORE_DEF_NAME *core, unsigned short port, bool dump) {
std::unique_ptr<CORE_DEF_NAME::vm_impl<arch::CORE_DEF_NAME>> ret =
std::make_unique<CORE_DEF_NAME::vm_impl<arch::CORE_DEF_NAME>>(*core, dump);
debugger::server<debugger::gdb_session>::run_server(ret.get(), port);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret.get(), port);
return ret;
}
template <> std::unique_ptr<vm_if> create<arch::CORE_DEF_NAME>(std::string inst_name, unsigned short port, bool dump) {
return create<arch::CORE_DEF_NAME>(new arch::riscv_hart_msu_vp<arch::CORE_DEF_NAME>(), port,
dump); /* FIXME: memory leak!!!!!!! */
}
template <> std::unique_ptr<vm_if> create<arch::CORE_DEF_NAME>(arch::CORE_DEF_NAME *core, bool dump) {
return std::make_unique<CORE_DEF_NAME::vm_impl<arch::CORE_DEF_NAME>>(*core, dump); /* FIXME: memory leak!!!!!!! */
}
template <> std::unique_ptr<vm_if> create<arch::CORE_DEF_NAME>(std::string inst_name, bool dump) {
return create<arch::CORE_DEF_NAME>(new arch::riscv_hart_msu_vp<arch::CORE_DEF_NAME>(), dump);
}
} // namespace iss

15
riscv/src/internal/vm_rv32imac.cpp
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@ -4014,21 +4014,8 @@ template <typename ARCH> inline void vm_impl<ARCH>::gen_trap_check(llvm::BasicBl
template <> std::unique_ptr<vm_if> create<arch::rv32imac>(arch::rv32imac *core, unsigned short port, bool dump) {
std::unique_ptr<rv32imac::vm_impl<arch::rv32imac>> ret =
std::make_unique<rv32imac::vm_impl<arch::rv32imac>>(*core, dump);
debugger::server<debugger::gdb_session>::run_server(ret.get(), port);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret.get(), port);
return ret;
}
template <> std::unique_ptr<vm_if> create<arch::rv32imac>(std::string inst_name, unsigned short port, bool dump) {
return create<arch::rv32imac>(new arch::riscv_hart_msu_vp<arch::rv32imac>(), port,
dump); /* FIXME: memory leak!!!!!!! */
}
template <> std::unique_ptr<vm_if> create<arch::rv32imac>(arch::rv32imac *core, bool dump) {
return std::make_unique<rv32imac::vm_impl<arch::rv32imac>>(*core, dump); /* FIXME: memory leak!!!!!!! */
}
template <> std::unique_ptr<vm_if> create<arch::rv32imac>(std::string inst_name, bool dump) {
return create<arch::rv32imac>(new arch::riscv_hart_msu_vp<arch::rv32imac>(), dump);
}
} // namespace iss

15
riscv/src/internal/vm_rv64ia.cpp
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@ -3101,21 +3101,8 @@ template <typename ARCH> inline void vm_impl<ARCH>::gen_trap_check(llvm::BasicBl
template <> std::unique_ptr<vm_if> create<arch::rv64ia>(arch::rv64ia *core, unsigned short port, bool dump) {
std::unique_ptr<rv64ia::vm_impl<arch::rv64ia>> ret = std::make_unique<rv64ia::vm_impl<arch::rv64ia>>(*core, dump);
debugger::server<debugger::gdb_session>::run_server(ret.get(), port);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret.get(), port);
return ret;
}
template <> std::unique_ptr<vm_if> create<arch::rv64ia>(std::string inst_name, unsigned short port, bool dump) {
return create<arch::rv64ia>(new arch::riscv_hart_msu_vp<arch::rv64ia>(), port,
dump); /* FIXME: memory leak!!!!!!! */
}
template <> std::unique_ptr<vm_if> create<arch::rv64ia>(arch::rv64ia *core, bool dump) {
return std::make_unique<rv64ia::vm_impl<arch::rv64ia>>(*core, dump); /* FIXME: memory leak!!!!!!! */
}
template <> std::unique_ptr<vm_if> create<arch::rv64ia>(std::string inst_name, bool dump) {
return create<arch::rv64ia>(new arch::riscv_hart_msu_vp<arch::rv64ia>(), dump);
}
} // namespace iss

2
riscv/src/iss/rv32imac.cpp
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@ -54,8 +54,6 @@ using namespace iss::arch;
rv32imac::rv32imac() { reg.icount = 0; }
rv32imac::~rv32imac() {}
void rv32imac::reset(uint64_t address) {
for (size_t i = 0; i < traits<rv32imac>::NUM_REGS; ++i)
set_reg(i, std::vector<uint8_t>(sizeof(traits<rv32imac>::reg_t), 0));

113
riscv/src/main.cpp
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@ -32,11 +32,12 @@
// eyck@minres.com - initial API and implementation
////////////////////////////////////////////////////////////////////////////////
#include <cli_options.h>
#include <iostream>
#include <iss/iss.h>
#include <boost/lexical_cast.hpp>
#include <boost/program_options.hpp>
#include <iss/arch/riscv_hart_msu_vp.h>
#include <iss/arch/rv32imac.h>
#include <iss/arch/rv64ia.h>
#include <iss/jit/MCJIThelper.h>
@ -45,69 +46,97 @@
namespace po = boost::program_options;
int main(int argc, char *argv[]) {
/*
* Define and parse the program options
*/
po::variables_map clim;
po::options_description desc("Options");
// clang-format off
desc.add_options()
("help,h", "Print help message")
("verbose,v", po::value<int>()->implicit_value(0), "Sets logging verbosity")
("log-file", po::value<std::string>(), "Sets default log file.")
("disass,d", po::value<std::string>()->implicit_value(""), "Enables disassembly")
("elf,l", po::value<std::vector<std::string>>(), "ELF file(s) to load")
("gdb-port,g", po::value<unsigned>()->default_value(0), "enable gdb server and specify port to use")
("input,i", po::value<std::string>(), "the elf file to load (instead of hex files)")
("dump-ir", "dump the intermediate representation")
("cycles,c", po::value<int64_t>()->default_value(-1), "number of cycles to run")
("systemc,s", "Run as SystemC simulation")
("time", po::value<int>(), "SystemC siimulation time in ms")
("reset,r", po::value<std::string>(), "reset address")
("trace", po::value<uint8_t>(), "enable tracing, or cmbintation of 1=signals and 2=TX text, 4=TX compressed text, 6=TX in SQLite")
("mem,m", po::value<std::string>(), "the memory input file")
("rv64", "run RV64");
// clang-format on
try {
/*
* Define and parse the program options
*/
po::variables_map vm;
if (parse_cli_options(vm, argc, argv)) return ERROR_IN_COMMAND_LINE;
if (vm.count("verbose")) {
auto l = logging::as_log_level(vm["verbose"].as<int>());
LOGGER(DEFAULT)::reporting_level() = l;
LOGGER(connection)::reporting_level() = l;
}
if (vm.count("log-file")) {
// configure the connection logger
auto f = fopen(vm["log-file"].as<std::string>().c_str(), "w");
LOG_OUTPUT(DEFAULT)::stream() = f;
LOG_OUTPUT(connection)::stream() = f;
po::store(po::parse_command_line(argc, argv, desc), clim); // can throw
// --help option
if (clim.count("help")) {
std::cout << "DBT-RISE-RiscV simulator for RISC-V" << std::endl << desc << std::endl;
return 0;
}
po::notify(clim); // throws on error, so do after help in case
} catch (po::error &e) {
// there are problems
std::cerr << "ERROR: " << e.what() << std::endl << std::endl;
std::cerr << desc << std::endl;
return 1;
}
if (clim.count("verbose")) {
auto l = logging::as_log_level(clim["verbose"].as<int>());
LOGGER(DEFAULT)::reporting_level() = l;
LOGGER(connection)::reporting_level() = l;
}
if (clim.count("log-file")) {
// configure the connection logger
auto f = fopen(clim["log-file"].as<std::string>().c_str(), "w");
LOG_OUTPUT(DEFAULT)::stream() = f;
LOG_OUTPUT(connection)::stream() = f;
}
try {
// application code comes here //
iss::init_jit(argc, argv);
bool dump = vm.count("dump-ir");
bool dump = clim.count("dump-ir");
// instantiate the simulator
std::unique_ptr<iss::vm_if> cpu{nullptr};
if (vm.count("rv64") == 1) {
if (vm.count("gdb-port") == 1)
cpu = iss::create<iss::arch::rv64ia>("rv64ia", vm["gdb-port"].as<unsigned>(), dump);
else
cpu = iss::create<iss::arch::rv64ia>("rv64ia", dump);
std::unique_ptr<iss::vm_if> vm{nullptr};
if (clim.count("rv64") == 1) {
auto cpu = new iss::arch::riscv_hart_msu_vp<iss::arch::rv64ia>();
vm = iss::create<iss::arch::rv64ia>(cpu, clim["gdb-port"].as<unsigned>(), dump);
} else {
if (vm.count("gdb-port") == 1)
cpu = iss::create<iss::arch::rv32imac>("rv32ima", vm["gdb-port"].as<unsigned>(), dump);
else
cpu = iss::create<iss::arch::rv32imac>("rv32ima", dump);
auto cpu = new iss::arch::riscv_hart_msu_vp<iss::arch::rv32imac>();
vm = iss::create<iss::arch::rv32imac>(cpu, clim["gdb-port"].as<unsigned>(), dump);
}
if (vm.count("elf")) {
for (std::string input : vm["elf"].as<std::vector<std::string>>()) cpu->get_arch()->load_file(input);
} else if (vm.count("mem")) {
cpu->get_arch()->load_file(vm["mem"].as<std::string>(), iss::arch::traits<iss::arch::rv32imac>::MEM);
if (clim.count("elf")) {
for (std::string input : clim["elf"].as<std::vector<std::string>>()) vm->get_arch()->load_file(input);
} else if (clim.count("mem")) {
vm->get_arch()->load_file(clim["mem"].as<std::string>(), iss::arch::traits<iss::arch::rv32imac>::MEM);
}
if (vm.count("disass")) {
cpu->setDisassEnabled(true);
if (clim.count("disass")) {
vm->setDisassEnabled(true);
LOGGER(disass)::reporting_level() = logging::INFO;
auto file_name = vm["disass"].as<std::string>();
auto file_name = clim["disass"].as<std::string>();
if (file_name.length() > 0) {
LOG_OUTPUT(disass)::stream() = fopen(file_name.c_str(), "w");
LOGGER(disass)::print_time() = false;
LOGGER(disass)::print_severity() = false;
}
}
if (vm.count("reset")) {
auto str = vm["reset"].as<std::string>();
auto start_address = str.find("0x") == 0 ? std::stoull(str, 0, 16) : std::stoull(str, 0, 10);
cpu->reset(start_address);
if (clim.count("reset")) {
auto str = clim["reset"].as<std::string>();
auto start_address = str.find("0x") == 0 ? std::stoull(str.substr(2), 0, 16) : std::stoull(str, 0, 10);
vm->reset(start_address);
} else {
cpu->reset();
vm->reset();
}
int64_t cycles = -1;
cycles = vm["cycles"].as<int64_t>();
return cpu->start(cycles);
cycles = clim["cycles"].as<int64_t>();
return vm->start(cycles);
} catch (std::exception &e) {
LOG(ERROR) << "Unhandled Exception reached the top of main: " << e.what() << ", application will now exit"
<< std::endl;
return ERROR_UNHANDLED_EXCEPTION;
return 2;
}
}