143 lines
6.4 KiB
C++
143 lines
6.4 KiB
C++
////////////////////////////////////////////////////////////////////////////////
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// Copyright (C) 2017, MINRES Technologies GmbH
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its contributors
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// may be used to endorse or promote products derived from this software
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// without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// Contributors:
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// eyck@minres.com - initial API and implementation
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////////////////////////////////////////////////////////////////////////////////
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#include <iostream>
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#include <iss/iss.h>
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#include <boost/lexical_cast.hpp>
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#include <boost/program_options.hpp>
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#include <iss/arch/riscv_hart_msu_vp.h>
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#include <iss/arch/rv32imac.h>
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#include <iss/arch/rv64ia.h>
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#include <iss/jit/MCJIThelper.h>
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#include <iss/log_categories.h>
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namespace po = boost::program_options;
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int main(int argc, char *argv[]) {
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/*
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* Define and parse the program options
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*/
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po::variables_map clim;
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po::options_description desc("Options");
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// clang-format off
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desc.add_options()
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("help,h", "Print help message")
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("verbose,v", po::value<int>()->implicit_value(0), "Sets logging verbosity")
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("log-file", po::value<std::string>(), "Sets default log file.")
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("disass,d", po::value<std::string>()->implicit_value(""), "Enables disassembly")
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("elf,l", po::value<std::vector<std::string>>(), "ELF file(s) to load")
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("gdb-port,g", po::value<unsigned>()->default_value(0), "enable gdb server and specify port to use")
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("input,i", po::value<std::string>(), "the elf file to load (instead of hex files)")
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("dump-ir", "dump the intermediate representation")
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("cycles,c", po::value<int64_t>()->default_value(-1), "number of cycles to run")
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("systemc,s", "Run as SystemC simulation")
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("time", po::value<int>(), "SystemC siimulation time in ms")
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("reset,r", po::value<std::string>(), "reset address")
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("trace", po::value<uint8_t>(), "enable tracing, or cmbintation of 1=signals and 2=TX text, 4=TX compressed text, 6=TX in SQLite")
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("mem,m", po::value<std::string>(), "the memory input file")
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("rv64", "run RV64");
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// clang-format on
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try {
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po::store(po::parse_command_line(argc, argv, desc), clim); // can throw
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// --help option
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if (clim.count("help")) {
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std::cout << "DBT-RISE-RiscV simulator for RISC-V" << std::endl << desc << std::endl;
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return 0;
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}
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po::notify(clim); // throws on error, so do after help in case
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} catch (po::error &e) {
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// there are problems
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std::cerr << "ERROR: " << e.what() << std::endl << std::endl;
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std::cerr << desc << std::endl;
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return 1;
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}
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if (clim.count("verbose")) {
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auto l = logging::as_log_level(clim["verbose"].as<int>());
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LOGGER(DEFAULT)::reporting_level() = l;
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LOGGER(connection)::reporting_level() = l;
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}
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if (clim.count("log-file")) {
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// configure the connection logger
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auto f = fopen(clim["log-file"].as<std::string>().c_str(), "w");
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LOG_OUTPUT(DEFAULT)::stream() = f;
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LOG_OUTPUT(connection)::stream() = f;
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}
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try {
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// application code comes here //
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iss::init_jit(argc, argv);
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bool dump = clim.count("dump-ir");
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// instantiate the simulator
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std::unique_ptr<iss::vm_if> vm{nullptr};
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if (clim.count("rv64") == 1) {
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auto cpu = new iss::arch::riscv_hart_msu_vp<iss::arch::rv64ia>();
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vm = iss::create<iss::arch::rv64ia>(cpu, clim["gdb-port"].as<unsigned>(), dump);
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} else {
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auto cpu = new iss::arch::riscv_hart_msu_vp<iss::arch::rv32imac>();
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vm = iss::create<iss::arch::rv32imac>(cpu, clim["gdb-port"].as<unsigned>(), dump);
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}
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if (clim.count("elf")) {
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for (std::string input : clim["elf"].as<std::vector<std::string>>()) vm->get_arch()->load_file(input);
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} else if (clim.count("mem")) {
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vm->get_arch()->load_file(clim["mem"].as<std::string>(), iss::arch::traits<iss::arch::rv32imac>::MEM);
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}
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if (clim.count("disass")) {
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vm->setDisassEnabled(true);
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LOGGER(disass)::reporting_level() = logging::INFO;
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auto file_name = clim["disass"].as<std::string>();
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if (file_name.length() > 0) {
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LOG_OUTPUT(disass)::stream() = fopen(file_name.c_str(), "w");
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LOGGER(disass)::print_time() = false;
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LOGGER(disass)::print_severity() = false;
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}
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}
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if (clim.count("reset")) {
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auto str = clim["reset"].as<std::string>();
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auto start_address = str.find("0x") == 0 ? std::stoull(str.substr(2), 0, 16) : std::stoull(str, 0, 10);
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vm->reset(start_address);
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} else {
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vm->reset();
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}
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int64_t cycles = -1;
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cycles = clim["cycles"].as<int64_t>();
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return vm->start(cycles);
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} catch (std::exception &e) {
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LOG(ERROR) << "Unhandled Exception reached the top of main: " << e.what() << ", application will now exit"
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<< std::endl;
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return 2;
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}
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}
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