Adapted descriptions to improved Core DSL and regenerated code

riscv/gen_input/templates/incl-CORENAME.h.gtl

@@ -80,6 +80,8 @@ struct traits<${coreDef.name.toLowerCase()}> {
 
     using addr_t = uint${addrDataWidth}_t;
 
+    using code_word_t = uint${addrDataWidth}_t; //TODO: check removal
+
     using virt_addr_t = iss::typed_addr_t<iss::address_type::VIRTUAL>;
 
     using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;

riscv/gen_input/templates/vm-vm_CORENAME.cpp.gtl

@@ -320,6 +320,8 @@ template <typename ARCH> inline void vm_impl<ARCH>::gen_trap_check(llvm::BasicBl
                           bb, this->trap_blk, 1);
 }
 
+} // namespace ${coreDef.name.toLowerCase()}
+
 template <>
 std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
     std::unique_ptr<${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>> ret =