diff --git a/.cproject b/.cproject index 48c5c3a..7a0ad6f 100644 --- a/.cproject +++ b/.cproject @@ -10,15 +10,14 @@ - - + - + - + diff --git a/dbt-core b/dbt-core index 393c374..23dbab0 160000 --- a/dbt-core +++ b/dbt-core @@ -1 +1 @@ -Subproject commit 393c374cac4950e629036dda1615abedf866961f +Subproject commit 23dbab0b768d122c492110d1db34408e9ae787f3 diff --git a/riscv/gen_input/RV32A.core_desc b/riscv/gen_input/RV32A.core_desc index 67e0c89..16638c5 100644 --- a/riscv/gen_input/RV32A.core_desc +++ b/riscv/gen_input/RV32A.core_desc @@ -1,108 +1,108 @@ import "RV32IBase.core_desc" InsructionSet RV32A extends RV32IBase{ - - address_spaces { - RES[8] - } - - instructions{ - LR.W { - encoding: b00010 | aq[0:0] | rl[0:0] | b00000 | rs1[4:0] | b010 | rd[4:0] | b0101111; - args_disass: "x%rd$d, x%rs1$d"; - if(rd!=0){ - val offs[XLEN] <= X[rs1]; - X[rd]<= sext(MEM[offs]{32}, XLEN); - RES[offs]{32}<=sext(-1, 32); - } - } - SC.W { - encoding: b00011 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111; - args_disass: "x%rd$d, x%rs1$d, x%rs2$d"; - val offs[XLEN] <= X[rs1]; - val res1[32] <= RES[offs]{32}; - if(res1!=0) - MEM[offs]{32} <= X[rs2]; - if(rd!=0) X[rd]<= choose(res1!=0, 0, 1); - } - AMOSWAP.W{ - encoding: b00001 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111; - args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)"; - val offs[XLEN]<=X[rs1]; - if(rd!=0) X[rd]<=sext(MEM[offs]{32}); - MEM[offs]{32}<=X[rs2]; - } - AMOADD.W{ - encoding: b00000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111; - args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)"; - val offs[XLEN]<=X[rs1]; - val res1[XLEN] <= sext(MEM[offs]{32}); - if(rd!=0) X[rd]<=res1; - val res2[XLEN]<=res1 + X[rs2]; - MEM[offs]{32}<=res2; - } - AMOXOR.W{ - encoding: b00100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111; - args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)"; - val offs[XLEN]<=X[rs1]; - val res1[XLEN] <= sext(MEM[offs]{32}); - if(rd!=0) X[rd]<=res1; - val res2[XLEN]<=res1 ^ X[rs2]; - MEM[offs]{32}<=res2; - } - AMOAND.W{ - encoding: b01100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111; - args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)"; - val offs[XLEN]<=X[rs1]; - val res1[XLEN] <= sext(MEM[offs]{32}); - if(rd!=0) X[rd]<=res1; - val res2[XLEN] <=res1 & X[rs2]; - MEM[offs]{32}<=res2; - } - AMOOR.W { - encoding: b01000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111; - args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)"; - val offs[XLEN]<=X[rs1]; - val res1[XLEN] <= sext(MEM[offs]{32}); - if(rd!=0) X[rd]<=res1; - val res2[XLEN]<=res1 | X[rs2]; - MEM[offs]{32}<=res2; - } - AMOMIN.W{ - encoding: b10000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111; - args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)"; - val offs[XLEN]<=X[rs1]; - val res1[XLEN] <= sext(MEM[offs]{32}); - if(rd!=0) X[rd]<=res1; - val res2[XLEN]<= choose(res1's>X[rs2]s, X[rs2], res1); - MEM[offs]{32}<=res2; - } - AMOMAX.W{ - encoding: b10100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111; - args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)"; - val offs[XLEN]<=X[rs1]; - val res1[XLEN] <= sext(MEM[offs]{32}); - if(rd!=0) X[rd]<=res1; - val res2[XLEN]<= choose(res1'sX[rs2], X[rs2], res1); - MEM[offs]{32}<=res2; - } - AMOMAXU.W{ - encoding: b11100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111; - args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)"; - val offs[XLEN]<=X[rs1]; - val res1[XLEN] <= zext(MEM[offs]{32}); - if(rd!=0) X[rd]<=res1; - val res2[XLEN]<= choose(res1'uX[rs2]s, X[rs2], res1); + MEM[offs]{32}<=res2; + } + AMOMAX.W{ + encoding: b10100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111; + args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)"; + val offs[XLEN]<=X[rs1]; + val res1[XLEN] <= sext(MEM[offs]{32}); + if(rd!=0) X[rd]<=res1; + val res2[XLEN]<= choose(res1'sX[rs2], X[rs2], res1); + MEM[offs]{32}<=res2; + } + AMOMAXU.W{ + encoding: b11100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0101111; + args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%aq$d,rel=%rl$d)"; + val offs[XLEN]<=X[rs1]; + val res1[XLEN] <= zext(MEM[offs]{32}); + if(rd!=0) X[rd]<=res1; + val res2[XLEN]<= choose(res1'uF[rs2]f, F[rs1]f, F[rs2]f); - val res[64] <= fdispatch_fsel_d(F[rs1]{64}, F[rs2]{64}, zext(1, 32)); - if(FLEN==64) - F[rd] <= res; - else { // NaN boxing - val upper[FLEN] <= -1; - F[rd] <= (upper<<64) | res; - } - val flags[32] <= fdispatch_fget_flags(); - FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; - } - FCVT.S.D { - encoding: b0100000 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; - args_disass:"f%rd$d, f%rs1$d"; - val res[32] <= fdispatch_fconv_d2f(F[rs1], rm{8}); - // NaN boxing - val upper[FLEN] <= -1; - F[rd] <= upper<<32 | zext(res, FLEN); - } - FCVT.D.S { - encoding: b0100001 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; - args_disass:"f%rd$d, f%rs1$d"; - val res[64] <= fdispatch_fconv_f2d(F[rs1]{32}, rm{8}); - if(FLEN==64){ - F[rd] <= res; - } else { - val upper[FLEN] <= -1; - F[rd] <= (upper<<64) | res; - } - } - FEQ.D { - encoding: b1010001 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b1010011; - args_disass:"x%rd$d, f%rs1$d, f%rs2$d"; - X[rd]<=fdispatch_fcmp_d(F[rs1]{64}, F[rs2]{64}, zext(0, 32)); - val flags[32] <= fdispatch_fget_flags(); - FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; - } - FLT.D { - encoding: b1010001 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011; - args_disass:"x%rd$d, f%rs1$d, f%rs2$d"; - X[rd]<=fdispatch_fcmp_d(F[rs1]{64}, F[rs2]{64}, zext(2, 32)); - val flags[32] <= fdispatch_fget_flags(); - FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; - } - FLE.D { - encoding: b1010001 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011; - args_disass:"x%rd$d, f%rs1$d, f%rs2$d"; - X[rd]<=fdispatch_fcmp_d(F[rs1]{64}, F[rs2]{64}, zext(1, 32)); - val flags[32] <= fdispatch_fget_flags(); - FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; - } - FCLASS.D { - encoding: b1110001 | b00000 | rs1[4:0] | b001 | rd[4:0] | b1010011; - args_disass:"x%rd$d, f%rs1$d"; - X[rd]<=fdispatch_fclass_d(F[rs1]{64}); - } - FCVT.W.D { - encoding: b1100001 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; - args_disass:"x%rd$d, f%rs1$d"; - X[rd]<= sext(fdispatch_fcvt_d(F[rs1]{64}, zext(0, 32), rm{8}), XLEN); - val flags[32] <= fdispatch_fget_flags(); - FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; - } - FCVT.WU.D { - encoding: b1100001 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; - args_disass:"x%rd$d, f%rs1$d"; - X[rd]<= zext(fdispatch_fcvt_d(F[rs1]{64}, zext(1, 32), rm{8}), XLEN); - val flags[32] <= fdispatch_fget_flags(); - FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; - } - FCVT.D.W { - encoding: b1101001 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; - args_disass:"f%rd$d, x%rs1$d"; - val res[64] <= fdispatch_fcvt_d(sext(X[rs1],64), zext(2, 32), rm{8}); - if(FLEN==64) - F[rd] <= res; - else { // NaN boxing - val upper[FLEN] <= -1; - F[rd] <= (upper<<64) | res; - } - } - FCVT.D.WU { - encoding: b1101001 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; - args_disass:"f%rd$d, x%rs1$d"; - val res[64] <=fdispatch_fcvt_d(zext(X[rs1],64), zext(3,32), rm{8}); - if(FLEN==64) - F[rd] <= res; - else { // NaN boxing - val upper[FLEN] <= -1; - F[rd] <= (upper<<64) | res; - } - } - } + constants { + FLEN, FFLAG_MASK := 0x1f + } + registers { + [31:0] F[FLEN], FCSR[32] + } + instructions{ + FLD { + encoding: imm[11:0]s | rs1[4:0] | b011 | rd[4:0] | b0000111; + args_disass:"f%rd$d, %imm%(x%rs1$d)"; + val offs[XLEN] <= X[rs1]+imm; + val res[64] <= MEM[offs]{64}; + if(FLEN==64) + F[rd] <= res; + else { // NaN boxing + val upper[FLEN] <= -1; + F[rd] <= (upper<<64) | res; + } + } + FSD { + encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b011 | imm[4:0]s | b0100111; + args_disass:"f%rs2$d, %imm%(x%rs1$d)"; + val offs[XLEN] <= X[rs1]+imm; + MEM[offs]{64}<=F[rs2]{64}; + } + FMADD.D { + encoding: rs3[4:0] | b01 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1000011; + args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d"; + //F[rd]f<= F[rs1]f * F[rs2]f + F[rs3]f; + val res[64] <= fdispatch_fmadd_d(F[rs1]{64}, F[rs2]{64}, F[rs3]{64}, zext(0, 64), choose(rm<7, rm{8}, FCSR{8})); + if(FLEN==64) + F[rd] <= res; + else { // NaN boxing + val upper[FLEN] <= -1; + F[rd] <= (upper<<64) | res; + } + val flags[32] <= fdispatch_fget_flags(); + FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; + } + FMSUB.D { + encoding: rs3[4:0] | b01 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1000111; + args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d"; + //F[rd]f<=F[rs1]f * F[rs2]f - F[rs3]f; + val res[64] <= fdispatch_fmadd_d(F[rs1]{64}, F[rs2]{64}, F[rs3]{64}, zext(1, 32), choose(rm<7, rm{8}, FCSR{8})); + if(FLEN==64) + F[rd] <= res; + else { // NaN boxing + val upper[FLEN] <= -1; + F[rd] <= (upper<<64) | res; + } + val flags[32] <= fdispatch_fget_flags(); + FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; + } + FNMADD.D { + encoding: rs3[4:0] | b01 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1001111; + args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d"; + //F[rd]f<=-F[rs1]f * F[rs2]f + F[rs3]f; + val res[64] <= fdispatch_fmadd_d(F[rs1]{64}, F[rs2]{64}, F[rs3]{64}, zext(2, 32), choose(rm<7, rm{8}, FCSR{8})); + if(FLEN==64) + F[rd] <= res; + else { // NaN boxing + val upper[FLEN] <= -1; + F[rd] <= (upper<<64) | res; + } + val flags[32] <= fdispatch_fget_flags(); + FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; + } + FNMSUB.D { + encoding: rs3[4:0] | b01 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1001011; + args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d"; + //F[rd]f<=-F[rs1]f * F[rs2]f - F[rs3]f; + val res[64] <= fdispatch_fmadd_d(F[rs1]{64}, F[rs2]{64}, F[rs3]{64}, zext(3, 32), choose(rm<7, rm{8}, FCSR{8})); + if(FLEN==64) + F[rd] <= res; + else { // NaN boxing + val upper[FLEN] <= -1; + F[rd] <= (upper<<64) | res; + } + val flags[32] <= fdispatch_fget_flags(); + FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; + } + FADD.D { + encoding: b0000001 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; + args_disass:"x%rd$d, f%rs1$d, f%rs2$d"; + // F[rd]f <= F[rs1]f + F[rs2]f; + val res[64] <= fdispatch_fadd_d(F[rs1]{64}, F[rs2]{64}, choose(rm<7, rm{8}, FCSR{8})); + if(FLEN==64) + F[rd] <= res; + else { // NaN boxing + val upper[FLEN] <= -1; + F[rd] <= (upper<<64) | res; + } + val flags[32] <= fdispatch_fget_flags(); + FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; + } + FSUB.D { + encoding: b0000101 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; + args_disass:"x%rd$d, f%rs1$d, f%rs2$d"; + // F[rd]f <= F[rs1]f - F[rs2]f; + val res[64] <= fdispatch_fsub_d(F[rs1]{64}, F[rs2]{64}, choose(rm<7, rm{8}, FCSR{8})); + if(FLEN==64) + F[rd] <= res; + else { // NaN boxing + val upper[FLEN] <= -1; + F[rd] <= (upper<<64) | res; + } + val flags[32] <= fdispatch_fget_flags(); + FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; + } + FMUL.D { + encoding: b0001001 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; + args_disass:"x%rd$d, f%rs1$d, f%rs2$d"; + // F[rd]f <= F[rs1]f * F[rs2]f; + val res[64] <= fdispatch_fmul_d(F[rs1]{64}, F[rs2]{64}, choose(rm<7, rm{8}, FCSR{8})); + if(FLEN==64) + F[rd] <= res; + else { // NaN boxing + val upper[FLEN] <= -1; + F[rd] <= (upper<<64) | res; + } + val flags[32] <= fdispatch_fget_flags(); + FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; + } + FDIV.D { + encoding: b0001101 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; + args_disass:"x%rd$d, f%rs1$d, f%rs2$d"; + // F[rd]f <= F[rs1]f / F[rs2]f; + val res[64] <= fdispatch_fdiv_d(F[rs1]{64}, F[rs2]{64}, choose(rm<7, rm{8}, FCSR{8})); + if(FLEN==64) + F[rd] <= res; + else { // NaN boxing + val upper[FLEN] <= -1; + F[rd] <= (upper<<64) | res; + } + val flags[32] <= fdispatch_fget_flags(); + FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; + } + FSQRT.D { + encoding: b0101101 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; + args_disass:"x%rd$d, f%rs1$d"; + //F[rd]f<=sqrt(F[rs1]f); + val res[64] <= fdispatch_fsqrt_d(F[rs1]{64}, choose(rm<7, rm{8}, FCSR{8})); + if(FLEN==64) + F[rd] <= res; + else { // NaN boxing + val upper[FLEN] <= -1; + F[rd] <= (upper<<64) | res; + } + val flags[32] <= fdispatch_fget_flags(); + FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; + } + FSGNJ.D { + encoding: b0010001 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011; + args_disass:"f%rd$d, f%rs1$d, f%rs2$d"; + val res[64] <= (F[rs1]{64} & 0x7fffffff) | (F[rs2]{64} & 0x80000000); + if(FLEN==64) + F[rd] <= res; + else { // NaN boxing + val upper[FLEN] <= -1; + F[rd] <= (upper<<64) | res; + } + } + FSGNJN.D { + encoding: b0010001 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011; + args_disass:"f%rd$d, f%rs1$d, f%rs2$d"; + val res[64] <= (F[rs1]{64} & 0x7fffffff) | (~F[rs2]{64} & 0x80000000); + if(FLEN==64) + F[rd] <= res; + else { // NaN boxing + val upper[FLEN] <= -1; + F[rd] <= (upper<<64) | res; + } + } + FSGNJX.D { + encoding: b0010001 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b1010011; + args_disass:"f%rd$d, f%rs1$d, f%rs2$d"; + val res[64] <= F[rs1]{64} ^ (F[rs2]{64} & 0x80000000); + if(FLEN==64) + F[rd] <= res; + else { // NaN boxing + val upper[FLEN] <= -1; + F[rd] <= (upper<<64) | res; + } + } + FMIN.D { + encoding: b0010101 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011; + args_disass:"f%rd$d, f%rs1$d, f%rs2$d"; + //F[rd]f<= choose(F[rs1]fF[rs2]f, F[rs1]f, F[rs2]f); + val res[64] <= fdispatch_fsel_d(F[rs1]{64}, F[rs2]{64}, zext(1, 32)); + if(FLEN==64) + F[rd] <= res; + else { // NaN boxing + val upper[FLEN] <= -1; + F[rd] <= (upper<<64) | res; + } + val flags[32] <= fdispatch_fget_flags(); + FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; + } + FCVT.S.D { + encoding: b0100000 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; + args_disass:"f%rd$d, f%rs1$d"; + val res[32] <= fdispatch_fconv_d2f(F[rs1], rm{8}); + // NaN boxing + val upper[FLEN] <= -1; + F[rd] <= upper<<32 | zext(res, FLEN); + } + FCVT.D.S { + encoding: b0100001 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; + args_disass:"f%rd$d, f%rs1$d"; + val res[64] <= fdispatch_fconv_f2d(F[rs1]{32}, rm{8}); + if(FLEN==64){ + F[rd] <= res; + } else { + val upper[FLEN] <= -1; + F[rd] <= (upper<<64) | res; + } + } + FEQ.D { + encoding: b1010001 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b1010011; + args_disass:"x%rd$d, f%rs1$d, f%rs2$d"; + X[rd]<=fdispatch_fcmp_d(F[rs1]{64}, F[rs2]{64}, zext(0, 32)); + val flags[32] <= fdispatch_fget_flags(); + FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; + } + FLT.D { + encoding: b1010001 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011; + args_disass:"x%rd$d, f%rs1$d, f%rs2$d"; + X[rd]<=fdispatch_fcmp_d(F[rs1]{64}, F[rs2]{64}, zext(2, 32)); + val flags[32] <= fdispatch_fget_flags(); + FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; + } + FLE.D { + encoding: b1010001 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011; + args_disass:"x%rd$d, f%rs1$d, f%rs2$d"; + X[rd]<=fdispatch_fcmp_d(F[rs1]{64}, F[rs2]{64}, zext(1, 32)); + val flags[32] <= fdispatch_fget_flags(); + FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; + } + FCLASS.D { + encoding: b1110001 | b00000 | rs1[4:0] | b001 | rd[4:0] | b1010011; + args_disass:"x%rd$d, f%rs1$d"; + X[rd]<=fdispatch_fclass_d(F[rs1]{64}); + } + FCVT.W.D { + encoding: b1100001 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; + args_disass:"x%rd$d, f%rs1$d"; + X[rd]<= sext(fdispatch_fcvt_d(F[rs1]{64}, zext(0, 32), rm{8}), XLEN); + val flags[32] <= fdispatch_fget_flags(); + FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; + } + FCVT.WU.D { + encoding: b1100001 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; + args_disass:"x%rd$d, f%rs1$d"; + X[rd]<= zext(fdispatch_fcvt_d(F[rs1]{64}, zext(1, 32), rm{8}), XLEN); + val flags[32] <= fdispatch_fget_flags(); + FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; + } + FCVT.D.W { + encoding: b1101001 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; + args_disass:"f%rd$d, x%rs1$d"; + val res[64] <= fdispatch_fcvt_d(sext(X[rs1],64), zext(2, 32), rm{8}); + if(FLEN==64) + F[rd] <= res; + else { // NaN boxing + val upper[FLEN] <= -1; + F[rd] <= (upper<<64) | res; + } + } + FCVT.D.WU { + encoding: b1101001 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; + args_disass:"f%rd$d, x%rs1$d"; + val res[64] <=fdispatch_fcvt_d(zext(X[rs1],64), zext(3,32), rm{8}); + if(FLEN==64) + F[rd] <= res; + else { // NaN boxing + val upper[FLEN] <= -1; + F[rd] <= (upper<<64) | res; + } + } + } } \ No newline at end of file diff --git a/riscv/gen_input/RV32F.core_desc b/riscv/gen_input/RV32F.core_desc index a5324fd..a950f7b 100644 --- a/riscv/gen_input/RV32F.core_desc +++ b/riscv/gen_input/RV32F.core_desc @@ -1,294 +1,294 @@ import "RV32IBase.core_desc" InsructionSet RV32F extends RV32IBase{ - constants { - FLEN, FFLAG_MASK := 0x1f - } - registers { - [31:0] F[FLEN], FCSR[32] - } - instructions{ - FLW { - encoding: imm[11:0]s | rs1[4:0] | b010 | rd[4:0] | b0000111; - args_disass:"f%rd$d, %imm%(x%rs1$d)"; - val offs[XLEN] <= X[rs1]+imm; - val res[32] <= MEM[offs]{32}; - if(FLEN==32) - F[rd] <= res; - else { // NaN boxing - val upper[FLEN] <= -1; - F[rd] <= (upper<<32) | zext(res, FLEN); - } - } - FSW { - encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b010 | imm[4:0]s | b0100111; - args_disass:"f%rs2$d, %imm%(x%rs1$d)"; - val offs[XLEN] <= X[rs1]+imm; - MEM[offs]{32}<=F[rs2]{32}; - } - FMADD.S { - encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1000011; - args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d"; - //F[rd]f<= F[rs1]f * F[rs2]f + F[rs3]f; - val res[32] <= fdispatch_fmadd_s(F[rs1]{32}, F[rs2]{32}, F[rs3]{32}, zext(0, 32), choose(rm<7, rm{8}, FCSR{8})); - if(FLEN==32) - F[rd] <= res; - else { // NaN boxing - val upper[FLEN] <= -1; - F[rd] <= (upper<<32) | zext(res, FLEN); - } - val flags[32] <= fdispatch_fget_flags(); - FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; - } - FMSUB.S { - encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1000111; - args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d"; - //F[rd]f<=F[rs1]f * F[rs2]f - F[rs3]f; - val res[32] <= fdispatch_fmadd_s(F[rs1]{32}, F[rs2]{32}, F[rs3]{32}, zext(1, 32), choose(rm<7, rm{8}, FCSR{8})); - if(FLEN==32) - F[rd] <= res; - else { // NaN boxing - val upper[FLEN] <= -1; - F[rd] <= (upper<<32) | zext(res, FLEN); - } - val flags[32] <= fdispatch_fget_flags(); - FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; - } - FNMADD.S { - encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1001111; - args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d"; - //F[rd]f<=-F[rs1]f * F[rs2]f + F[rs3]f; - val res[32] <= fdispatch_fmadd_s(F[rs1]{32}, F[rs2]{32}, F[rs3]{32}, zext(2, 32), choose(rm<7, rm{8}, FCSR{8})); - if(FLEN==32) - F[rd] <= res; - else { // NaN boxing - val upper[FLEN] <= -1; - F[rd] <= (upper<<32) | zext(res, FLEN); - } - val flags[32] <= fdispatch_fget_flags(); - FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; - } - FNMSUB.S { - encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1001011; - args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d"; - //F[rd]f<=-F[rs1]f * F[rs2]f - F[rs3]f; - val res[32] <= fdispatch_fmadd_s(F[rs1]{32}, F[rs2]{32}, F[rs3]{32}, zext(3, 32), choose(rm<7, rm{8}, FCSR{8})); - if(FLEN==32) - F[rd] <= res; - else { // NaN boxing - val upper[FLEN] <= -1; - F[rd] <= (upper<<32) | zext(res, FLEN); - } - val flags[32] <= fdispatch_fget_flags(); - FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; - } - FADD.S { - encoding: b0000000 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; - args_disass:"f%rd$d, f%rs1$d, f%rs2$d"; - // F[rd]f <= F[rs1]f + F[rs2]f; - val res[32] <= fdispatch_fadd_s(F[rs1]{32}, F[rs2]{32}, choose(rm<7, rm{8}, FCSR{8})); - if(FLEN==32) - F[rd] <= res; - else { // NaN boxing - val upper[FLEN] <= -1; - F[rd] <= (upper<<32) | zext(res, FLEN); - } - val flags[32] <= fdispatch_fget_flags(); - FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; - } - FSUB.S { - encoding: b0000100 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; - args_disass:"f%rd$d, f%rs1$d, f%rs2$d"; - // F[rd]f <= F[rs1]f - F[rs2]f; - val res[32] <= fdispatch_fsub_s(F[rs1]{32}, F[rs2]{32}, choose(rm<7, rm{8}, FCSR{8})); - if(FLEN==32) - F[rd] <= res; - else { // NaN boxing - val upper[FLEN] <= -1; - F[rd] <= (upper<<32) | zext(res, FLEN); - } - val flags[32] <= fdispatch_fget_flags(); - FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; - } - FMUL.S { - encoding: b0001000 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; - args_disass:"f%rd$d, f%rs1$d, f%rs2$d"; - // F[rd]f <= F[rs1]f * F[rs2]f; - val res[32] <= fdispatch_fmul_s(F[rs1]{32}, F[rs2]{32}, choose(rm<7, rm{8}, FCSR{8})); - if(FLEN==32) - F[rd] <= res; - else { // NaN boxing - val upper[FLEN] <= -1; - F[rd] <= (upper<<32) | zext(res, FLEN); - } - val flags[32] <= fdispatch_fget_flags(); - FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; - } - FDIV.S { - encoding: b0001100 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; - args_disass:"f%rd$d, f%rs1$d, f%rs2$d"; - // F[rd]f <= F[rs1]f / F[rs2]f; - val res[32] <= fdispatch_fdiv_s(F[rs1]{32}, F[rs2]{32}, choose(rm<7, rm{8}, FCSR{8})); - if(FLEN==32) - F[rd] <= res; - else { // NaN boxing - val upper[FLEN] <= -1; - F[rd] <= (upper<<32) | zext(res, FLEN); - } - val flags[32] <= fdispatch_fget_flags(); - FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; - } - FSQRT.S { - encoding: b0101100 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; - args_disass:"f%rd$d, f%rs1$d"; - //F[rd]f<=sqrt(F[rs1]f); - val res[32] <= fdispatch_fsqrt_s(F[rs1]{32}, choose(rm<7, rm{8}, FCSR{8})); - if(FLEN==32) - F[rd] <= res; - else { // NaN boxing - val upper[FLEN] <= -1; - F[rd] <= (upper<<32) | zext(res, FLEN); - } - val flags[32] <= fdispatch_fget_flags(); - FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; - } - FSGNJ.S { - encoding: b0010000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011; - args_disass:"f%rd$d, f%rs1$d, f%rs2$d"; - val res[32] <= (F[rs1]{32} & 0x7fffffff) | (F[rs2]{32} & 0x80000000); - if(FLEN==32) - F[rd] <= res; - else { // NaN boxing - val upper[FLEN] <= -1; - F[rd] <= (upper<<32) | zext(res, FLEN); - } - } - FSGNJN.S { - encoding: b0010000 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011; - args_disass:"f%rd$d, f%rs1$d, f%rs2$d"; - val res[32] <= (F[rs1]{32} & 0x7fffffff) | (~F[rs2]{32} & 0x80000000); - if(FLEN==32) - F[rd] <= res; - else { // NaN boxing - val upper[FLEN] <= -1; - F[rd] <= (upper<<32) | zext(res, FLEN); - } - } - FSGNJX.S { - encoding: b0010000 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b1010011; - args_disass:"f%rd$d, f%rs1$d, f%rs2$d"; - val res[32] <= F[rs1]{32} ^ (F[rs2]{32} & 0x80000000); - if(FLEN==32) - F[rd] <= res; - else { // NaN boxing - val upper[FLEN] <= -1; - F[rd] <= (upper<<32) | zext(res, FLEN); - } - } - FMIN.S { - encoding: b0010100 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011; - args_disass:"f%rd$d, f%rs1$d, f%rs2$d"; - //F[rd]f<= choose(F[rs1]fF[rs2]f, F[rs1]f, F[rs2]f); - val res[32] <= fdispatch_fsel_s(F[rs1]{32}, F[rs2]{32}, zext(1, 32)); - if(FLEN==32) - F[rd] <= res; - else { // NaN boxing - val upper[FLEN] <= -1; - F[rd] <= (upper<<32) | zext(res, FLEN); - } - val flags[32] <= fdispatch_fget_flags(); - FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; - } - FCVT.W.S { - encoding: b1100000 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; - args_disass:"x%rd$d, f%rs1$d"; - X[rd]<= sext(fdispatch_fcvt_s(F[rs1]{32}, zext(0, 32), rm{8}), XLEN); - val flags[32] <= fdispatch_fget_flags(); - FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; - } - FCVT.WU.S { - encoding: b1100000 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; - args_disass:"x%rd$d, f%rs1$d"; - X[rd]<= zext(fdispatch_fcvt_s(F[rs1]{32}, zext(1, 32), rm{8}), XLEN); - val flags[32] <= fdispatch_fget_flags(); - FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; - } - FEQ.S { - encoding: b1010000 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b1010011; - args_disass:"x%rd$d, f%rs1$d, f%rs2$d"; - X[rd]<=fdispatch_fcmp_s(F[rs1]{32}, F[rs2]{32}, zext(0, 32)); - val flags[32] <= fdispatch_fget_flags(); - FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; - } - FLT.S { - encoding: b1010000 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011; - args_disass:"x%rd$d, f%rs1$d, f%rs2$d"; - X[rd]<=fdispatch_fcmp_s(F[rs1]{32}, F[rs2]{32}, zext(2, 32)); - val flags[32] <= fdispatch_fget_flags(); - FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; - } - FLE.S { - encoding: b1010000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011; - args_disass:"x%rd$d, f%rs1$d, f%rs2$d"; - X[rd]<=fdispatch_fcmp_s(F[rs1]{32}, F[rs2]{32}, zext(1, 32)); - val flags[32] <= fdispatch_fget_flags(); - FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; - } - FCLASS.S { - encoding: b1110000 | b00000 | rs1[4:0] | b001 | rd[4:0] | b1010011; - args_disass:"x%rd$d, f%rs1$d"; - X[rd]<=fdispatch_fclass_s(F[rs1]{32}); - } - FCVT.S.W { - encoding: b1101000 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; - args_disass:"f%rd$d, x%rs1$d"; - val res[32] <= fdispatch_fcvt_s(X[rs1]{32}, zext(2, 32), rm{8}); - if(FLEN==32) - F[rd] <= res; - else { // NaN boxing - val upper[FLEN] <= -1; - F[rd] <= (upper<<32) | zext(res, FLEN); - } - } - FCVT.S.WU { - encoding: b1101000 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; - args_disass:"f%rd$d, x%rs1$d"; - val res[32] <=fdispatch_fcvt_s(X[rs1]{32}, zext(3,32), rm{8}); - if(FLEN==32) - F[rd] <= res; - else { // NaN boxing - val upper[FLEN] <= -1; - F[rd] <= (upper<<32) | zext(res, FLEN); - } - } - FMV.X.W { - encoding: b1110000 | b00000 | rs1[4:0] | b000 | rd[4:0] | b1010011; - args_disass:"x%rd$d, f%rs1$d"; - X[rd]<=sext(F[rs1]{32}); - } - FMV.W.X { - encoding: b1111000 | b00000 | rs1[4:0] | b000 | rd[4:0] | b1010011; - args_disass:"f%rd$d, x%rs1$d"; - if(FLEN==32) - F[rd] <= X[rs1]; - else { // NaN boxing - val upper[FLEN] <= -1; - F[rd] <= (upper<<32) | zext(X[rs1], FLEN); - } - } - } + constants { + FLEN, FFLAG_MASK := 0x1f + } + registers { + [31:0] F[FLEN], FCSR[32] + } + instructions{ + FLW { + encoding: imm[11:0]s | rs1[4:0] | b010 | rd[4:0] | b0000111; + args_disass:"f%rd$d, %imm%(x%rs1$d)"; + val offs[XLEN] <= X[rs1]+imm; + val res[32] <= MEM[offs]{32}; + if(FLEN==32) + F[rd] <= res; + else { // NaN boxing + val upper[FLEN] <= -1; + F[rd] <= (upper<<32) | zext(res, FLEN); + } + } + FSW { + encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b010 | imm[4:0]s | b0100111; + args_disass:"f%rs2$d, %imm%(x%rs1$d)"; + val offs[XLEN] <= X[rs1]+imm; + MEM[offs]{32}<=F[rs2]{32}; + } + FMADD.S { + encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1000011; + args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d"; + //F[rd]f<= F[rs1]f * F[rs2]f + F[rs3]f; + val res[32] <= fdispatch_fmadd_s(F[rs1]{32}, F[rs2]{32}, F[rs3]{32}, zext(0, 32), choose(rm<7, rm{8}, FCSR{8})); + if(FLEN==32) + F[rd] <= res; + else { // NaN boxing + val upper[FLEN] <= -1; + F[rd] <= (upper<<32) | zext(res, FLEN); + } + val flags[32] <= fdispatch_fget_flags(); + FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; + } + FMSUB.S { + encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1000111; + args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d"; + //F[rd]f<=F[rs1]f * F[rs2]f - F[rs3]f; + val res[32] <= fdispatch_fmadd_s(F[rs1]{32}, F[rs2]{32}, F[rs3]{32}, zext(1, 32), choose(rm<7, rm{8}, FCSR{8})); + if(FLEN==32) + F[rd] <= res; + else { // NaN boxing + val upper[FLEN] <= -1; + F[rd] <= (upper<<32) | zext(res, FLEN); + } + val flags[32] <= fdispatch_fget_flags(); + FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; + } + FNMADD.S { + encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1001111; + args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d"; + //F[rd]f<=-F[rs1]f * F[rs2]f + F[rs3]f; + val res[32] <= fdispatch_fmadd_s(F[rs1]{32}, F[rs2]{32}, F[rs3]{32}, zext(2, 32), choose(rm<7, rm{8}, FCSR{8})); + if(FLEN==32) + F[rd] <= res; + else { // NaN boxing + val upper[FLEN] <= -1; + F[rd] <= (upper<<32) | zext(res, FLEN); + } + val flags[32] <= fdispatch_fget_flags(); + FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; + } + FNMSUB.S { + encoding: rs3[4:0] | b00 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1001011; + args_disass:"x%rd$d, f%rs1$d, f%rs2$d, f%rs3$d"; + //F[rd]f<=-F[rs1]f * F[rs2]f - F[rs3]f; + val res[32] <= fdispatch_fmadd_s(F[rs1]{32}, F[rs2]{32}, F[rs3]{32}, zext(3, 32), choose(rm<7, rm{8}, FCSR{8})); + if(FLEN==32) + F[rd] <= res; + else { // NaN boxing + val upper[FLEN] <= -1; + F[rd] <= (upper<<32) | zext(res, FLEN); + } + val flags[32] <= fdispatch_fget_flags(); + FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; + } + FADD.S { + encoding: b0000000 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; + args_disass:"f%rd$d, f%rs1$d, f%rs2$d"; + // F[rd]f <= F[rs1]f + F[rs2]f; + val res[32] <= fdispatch_fadd_s(F[rs1]{32}, F[rs2]{32}, choose(rm<7, rm{8}, FCSR{8})); + if(FLEN==32) + F[rd] <= res; + else { // NaN boxing + val upper[FLEN] <= -1; + F[rd] <= (upper<<32) | zext(res, FLEN); + } + val flags[32] <= fdispatch_fget_flags(); + FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; + } + FSUB.S { + encoding: b0000100 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; + args_disass:"f%rd$d, f%rs1$d, f%rs2$d"; + // F[rd]f <= F[rs1]f - F[rs2]f; + val res[32] <= fdispatch_fsub_s(F[rs1]{32}, F[rs2]{32}, choose(rm<7, rm{8}, FCSR{8})); + if(FLEN==32) + F[rd] <= res; + else { // NaN boxing + val upper[FLEN] <= -1; + F[rd] <= (upper<<32) | zext(res, FLEN); + } + val flags[32] <= fdispatch_fget_flags(); + FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; + } + FMUL.S { + encoding: b0001000 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; + args_disass:"f%rd$d, f%rs1$d, f%rs2$d"; + // F[rd]f <= F[rs1]f * F[rs2]f; + val res[32] <= fdispatch_fmul_s(F[rs1]{32}, F[rs2]{32}, choose(rm<7, rm{8}, FCSR{8})); + if(FLEN==32) + F[rd] <= res; + else { // NaN boxing + val upper[FLEN] <= -1; + F[rd] <= (upper<<32) | zext(res, FLEN); + } + val flags[32] <= fdispatch_fget_flags(); + FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; + } + FDIV.S { + encoding: b0001100 | rs2[4:0] | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; + args_disass:"f%rd$d, f%rs1$d, f%rs2$d"; + // F[rd]f <= F[rs1]f / F[rs2]f; + val res[32] <= fdispatch_fdiv_s(F[rs1]{32}, F[rs2]{32}, choose(rm<7, rm{8}, FCSR{8})); + if(FLEN==32) + F[rd] <= res; + else { // NaN boxing + val upper[FLEN] <= -1; + F[rd] <= (upper<<32) | zext(res, FLEN); + } + val flags[32] <= fdispatch_fget_flags(); + FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; + } + FSQRT.S { + encoding: b0101100 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; + args_disass:"f%rd$d, f%rs1$d"; + //F[rd]f<=sqrt(F[rs1]f); + val res[32] <= fdispatch_fsqrt_s(F[rs1]{32}, choose(rm<7, rm{8}, FCSR{8})); + if(FLEN==32) + F[rd] <= res; + else { // NaN boxing + val upper[FLEN] <= -1; + F[rd] <= (upper<<32) | zext(res, FLEN); + } + val flags[32] <= fdispatch_fget_flags(); + FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; + } + FSGNJ.S { + encoding: b0010000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011; + args_disass:"f%rd$d, f%rs1$d, f%rs2$d"; + val res[32] <= (F[rs1]{32} & 0x7fffffff) | (F[rs2]{32} & 0x80000000); + if(FLEN==32) + F[rd] <= res; + else { // NaN boxing + val upper[FLEN] <= -1; + F[rd] <= (upper<<32) | zext(res, FLEN); + } + } + FSGNJN.S { + encoding: b0010000 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011; + args_disass:"f%rd$d, f%rs1$d, f%rs2$d"; + val res[32] <= (F[rs1]{32} & 0x7fffffff) | (~F[rs2]{32} & 0x80000000); + if(FLEN==32) + F[rd] <= res; + else { // NaN boxing + val upper[FLEN] <= -1; + F[rd] <= (upper<<32) | zext(res, FLEN); + } + } + FSGNJX.S { + encoding: b0010000 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b1010011; + args_disass:"f%rd$d, f%rs1$d, f%rs2$d"; + val res[32] <= F[rs1]{32} ^ (F[rs2]{32} & 0x80000000); + if(FLEN==32) + F[rd] <= res; + else { // NaN boxing + val upper[FLEN] <= -1; + F[rd] <= (upper<<32) | zext(res, FLEN); + } + } + FMIN.S { + encoding: b0010100 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011; + args_disass:"f%rd$d, f%rs1$d, f%rs2$d"; + //F[rd]f<= choose(F[rs1]fF[rs2]f, F[rs1]f, F[rs2]f); + val res[32] <= fdispatch_fsel_s(F[rs1]{32}, F[rs2]{32}, zext(1, 32)); + if(FLEN==32) + F[rd] <= res; + else { // NaN boxing + val upper[FLEN] <= -1; + F[rd] <= (upper<<32) | zext(res, FLEN); + } + val flags[32] <= fdispatch_fget_flags(); + FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; + } + FCVT.W.S { + encoding: b1100000 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; + args_disass:"x%rd$d, f%rs1$d"; + X[rd]<= sext(fdispatch_fcvt_s(F[rs1]{32}, zext(0, 32), rm{8}), XLEN); + val flags[32] <= fdispatch_fget_flags(); + FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; + } + FCVT.WU.S { + encoding: b1100000 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; + args_disass:"x%rd$d, f%rs1$d"; + X[rd]<= zext(fdispatch_fcvt_s(F[rs1]{32}, zext(1, 32), rm{8}), XLEN); + val flags[32] <= fdispatch_fget_flags(); + FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; + } + FEQ.S { + encoding: b1010000 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b1010011; + args_disass:"x%rd$d, f%rs1$d, f%rs2$d"; + X[rd]<=fdispatch_fcmp_s(F[rs1]{32}, F[rs2]{32}, zext(0, 32)); + val flags[32] <= fdispatch_fget_flags(); + FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; + } + FLT.S { + encoding: b1010000 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b1010011; + args_disass:"x%rd$d, f%rs1$d, f%rs2$d"; + X[rd]<=fdispatch_fcmp_s(F[rs1]{32}, F[rs2]{32}, zext(2, 32)); + val flags[32] <= fdispatch_fget_flags(); + FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; + } + FLE.S { + encoding: b1010000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b1010011; + args_disass:"x%rd$d, f%rs1$d, f%rs2$d"; + X[rd]<=fdispatch_fcmp_s(F[rs1]{32}, F[rs2]{32}, zext(1, 32)); + val flags[32] <= fdispatch_fget_flags(); + FCSR <= (FCSR & ~FFLAG_MASK) + flags{5}; + } + FCLASS.S { + encoding: b1110000 | b00000 | rs1[4:0] | b001 | rd[4:0] | b1010011; + args_disass:"x%rd$d, f%rs1$d"; + X[rd]<=fdispatch_fclass_s(F[rs1]{32}); + } + FCVT.S.W { + encoding: b1101000 | b00000 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; + args_disass:"f%rd$d, x%rs1$d"; + val res[32] <= fdispatch_fcvt_s(X[rs1]{32}, zext(2, 32), rm{8}); + if(FLEN==32) + F[rd] <= res; + else { // NaN boxing + val upper[FLEN] <= -1; + F[rd] <= (upper<<32) | zext(res, FLEN); + } + } + FCVT.S.WU { + encoding: b1101000 | b00001 | rs1[4:0] | rm[2:0] | rd[4:0] | b1010011; + args_disass:"f%rd$d, x%rs1$d"; + val res[32] <=fdispatch_fcvt_s(X[rs1]{32}, zext(3,32), rm{8}); + if(FLEN==32) + F[rd] <= res; + else { // NaN boxing + val upper[FLEN] <= -1; + F[rd] <= (upper<<32) | zext(res, FLEN); + } + } + FMV.X.W { + encoding: b1110000 | b00000 | rs1[4:0] | b000 | rd[4:0] | b1010011; + args_disass:"x%rd$d, f%rs1$d"; + X[rd]<=sext(F[rs1]{32}); + } + FMV.W.X { + encoding: b1111000 | b00000 | rs1[4:0] | b000 | rd[4:0] | b1010011; + args_disass:"f%rd$d, x%rs1$d"; + if(FLEN==32) + F[rd] <= X[rs1]; + else { // NaN boxing + val upper[FLEN] <= -1; + F[rd] <= (upper<<32) | zext(X[rs1], FLEN); + } + } + } } \ No newline at end of file diff --git a/riscv/gen_input/RV32IBase.core_desc b/riscv/gen_input/RV32IBase.core_desc index 22f02f7..cfea414 100644 --- a/riscv/gen_input/RV32IBase.core_desc +++ b/riscv/gen_input/RV32IBase.core_desc @@ -1,325 +1,326 @@ InsructionSet RV32IBase { - constants { - XLEN, - PCLEN, - XLEN_BIT_MASK:=0x1f, + constants { + XLEN, + PCLEN, + XLEN_BIT_MASK:=0x1f, fence:=0, fencei:=1, fencevmal:=2, fencevmau:=3 - } - - address_spaces { - MEM[8], CSR[XLEN], FENCE[XLEN] - } - - registers { - [31:0] X[XLEN], - PC[XLEN](is_pc) - } - - instructions { - LUI{ - encoding: imm[31:12]s | rd[4:0] | b0110111; - args_disass: "x%rd$d, 0x%imm$05x"; - if(rd!=0) X[rd] <= imm; - } - AUIPC{ - encoding: imm[31:12]s | rd[4:0] | b0010111; - args_disass: "x%rd%, 0x%imm$08x"; - if(rd!=0) X[rd] <= PC+imm; - } - JAL(no_cont){ - encoding: imm[20:20]s | imm[10:1]s | imm[11:11]s | imm[19:12]s | rd[4:0] | b1101111; - args_disass: "x%rd$d, 0x%imm$x"; - if(rd!=0) X[rd] <= PC+4; - PC<=PC+imm; - } - JALR(no_cont){ - encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b1100111; - args_disass: "x%rd$d, x%rs1$d, 0x%imm$x"; + } + + address_spaces { + MEM[8], CSR[XLEN], FENCE[XLEN] + } + + registers { + [31:0] X[XLEN], + PC[XLEN](is_pc), + alias ZERO[XLEN] is X[0] + } + + instructions { + LUI{ + encoding: imm[31:12]s | rd[4:0] | b0110111; + args_disass: "x%rd$d, 0x%imm$05x"; + if(rd!=0) X[rd] <= imm; + } + AUIPC{ + encoding: imm[31:12]s | rd[4:0] | b0010111; + args_disass: "x%rd%, 0x%imm$08x"; + if(rd!=0) X[rd] <= PC+imm; + } + JAL(no_cont){ + encoding: imm[20:20]s | imm[10:1]s | imm[11:11]s | imm[19:12]s | rd[4:0] | b1101111; + args_disass: "x%rd$d, 0x%imm$x"; + if(rd!=0) X[rd] <= PC+4; + PC<=PC+imm; + } + JALR(no_cont){ + encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b1100111; + args_disass: "x%rd$d, x%rs1$d, 0x%imm$x"; val new_pc[XLEN] <= X[rs1]+ imm; val align[XLEN] <= new_pc & 0x2; - if(align != 0){ - raise(0, 0); - } else { - if(rd!=0) X[rd] <= PC+4; - PC<=new_pc & ~0x1; - } - } - BEQ(no_cont,cond){ - encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b000 | imm[4:1]s | imm[11:11]s | b1100011; - args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x"; - PC<=choose(X[rs1]==X[rs2], PC+imm, PC+4); - } - BNE(no_cont,cond){ - encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b001 | imm[4:1]s | imm[11:11]s | b1100011; - args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x"; - PC<=choose(X[rs1]!=X[rs2], PC+imm, PC+4); - } - BLT(no_cont,cond){ - encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b100 | imm[4:1]s | imm[11:11]s | b1100011; - args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x"; - PC<=choose(X[rs1]s=X[rs2]s, PC+imm, PC+4); - } - BLTU(no_cont,cond) { - encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b110 | imm[4:1]s | imm[11:11]s | b1100011; - args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x"; - PC<=choose(X[rs1]=X[rs2], PC+imm, PC+4); - } - LB { - encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b0000011; - args_disass:"x%rd$d, %imm%(x%rs1$d)"; - val offs[XLEN] <= X[rs1]+imm; - if(rd!=0) X[rd]<=sext(MEM[offs]); - } - LH { - encoding: imm[11:0]s | rs1[4:0] | b001 | rd[4:0] | b0000011; - args_disass:"x%rd$d, %imm%(x%rs1$d)"; - val offs[XLEN] <= X[rs1]+imm; - if(rd!=0) X[rd]<=sext(MEM[offs]{16}); - } - LW { - encoding: imm[11:0]s | rs1[4:0] | b010 | rd[4:0] | b0000011; - args_disass:"x%rd$d, %imm%(x%rs1$d)"; - val offs[XLEN] <= X[rs1]+imm; - if(rd!=0) X[rd]<=sext(MEM[offs]{32}); - } - LBU { - encoding: imm[11:0]s | rs1[4:0] | b100 | rd[4:0] | b0000011; - args_disass:"x%rd$d, %imm%(x%rs1$d)"; - val offs[XLEN] <= X[rs1]+imm; - if(rd!=0) X[rd]<=zext(MEM[offs]); - } - LHU { - encoding: imm[11:0]s | rs1[4:0] | b101 | rd[4:0] | b0000011; - args_disass:"x%rd$d, %imm%(x%rs1$d)"; - val offs[XLEN] <= X[rs1]+imm; - if(rd!=0) X[rd]<=zext(MEM[offs]{16}); - } - SB { - encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b000 | imm[4:0]s | b0100011; - args_disass:"x%rs2$d, %imm%(x%rs1$d)"; - val offs[XLEN] <= X[rs1] + imm; - MEM[offs] <= X[rs2]; - } - SH { - encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b001 | imm[4:0]s | b0100011; - args_disass:"x%rs2$d, %imm%(x%rs1$d)"; - val offs[XLEN] <= X[rs1] + imm; - MEM[offs]{16} <= X[rs2]; - } - SW { - encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b010 | imm[4:0]s | b0100011; - args_disass:"x%rs2$d, %imm%(x%rs1$d)"; - val offs[XLEN] <= X[rs1] + imm; - MEM[offs]{32} <= X[rs2]; - } - ADDI { - encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b0010011; - args_disass:"x%rd$d, x%rs1$d, %imm%"; - if(rd != 0) X[rd] <= X[rs1] + imm; - } - SLTI { - encoding: imm[11:0]s | rs1[4:0] | b010 | rd[4:0] | b0010011; - args_disass:"x%rd$d, x%rs1$d, %imm%"; - if (rd != 0) X[rd] <= choose(X[rs1]s < imm's, 1, 0); //TODO: needs fix - } - SLTIU { - encoding: imm[11:0]s | rs1[4:0] | b011 | rd[4:0] | b0010011; - args_disass:"x%rd$d, x%rs1$d, %imm%"; - val full_imm[XLEN] <= imm's; - if (rd != 0) X[rd] <= choose(X[rs1]'u < full_imm'u, 1, 0); - } - XORI { - encoding: imm[11:0]s | rs1[4:0] | b100 | rd[4:0] | b0010011; - args_disass:"x%rd$d, x%rs1$d, %imm%"; - if(rd != 0) X[rd] <= X[rs1] ^ imm; - } - ORI { - encoding: imm[11:0]s | rs1[4:0] | b110 | rd[4:0] | b0010011; - args_disass:"x%rd$d, x%rs1$d, %imm%"; - if(rd != 0) X[rd] <= X[rs1] | imm; - } - ANDI { - encoding: imm[11:0]s | rs1[4:0] | b111 | rd[4:0] | b0010011; - args_disass:"x%rd$d, x%rs1$d, %imm%"; - if(rd != 0) X[rd] <= X[rs1] & imm; - } - SLLI { - encoding: b0000000 | shamt[4:0] | rs1[4:0] | b001 | rd[4:0] | b0010011; - args_disass:"x%rd$d, x%rs1$d, %shamt%"; - if(shamt > 31){ - raise(0,0); - } else { - if(rd != 0) X[rd] <= shll(X[rs1], shamt); - } - } - SRLI { - encoding: b0000000 | shamt[4:0] | rs1[4:0] | b101 | rd[4:0] | b0010011; - args_disass:"x%rd$d, x%rs1$d, %shamt%"; + if(align != 0){ + raise(0, 0); + } else { + if(rd!=0) X[rd] <= PC+4; + PC<=new_pc & ~0x1; + } + } + BEQ(no_cont,cond){ + encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b000 | imm[4:1]s | imm[11:11]s | b1100011; + args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x"; + PC<=choose(X[rs1]==X[rs2], PC+imm, PC+4); + } + BNE(no_cont,cond){ + encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b001 | imm[4:1]s | imm[11:11]s | b1100011; + args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x"; + PC<=choose(X[rs1]!=X[rs2], PC+imm, PC+4); + } + BLT(no_cont,cond){ + encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b100 | imm[4:1]s | imm[11:11]s | b1100011; + args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x"; + PC<=choose(X[rs1]s=X[rs2]s, PC+imm, PC+4); + } + BLTU(no_cont,cond) { + encoding: imm[12:12]s |imm[10:5]s | rs2[4:0] | rs1[4:0] | b110 | imm[4:1]s | imm[11:11]s | b1100011; + args_disass:"x%rs1$d, x%rs2$d, 0x%imm$x"; + PC<=choose(X[rs1]=X[rs2], PC+imm, PC+4); + } + LB { + encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b0000011; + args_disass:"x%rd$d, %imm%(x%rs1$d)"; + val offs[XLEN] <= X[rs1]+imm; + if(rd!=0) X[rd]<=sext(MEM[offs]); + } + LH { + encoding: imm[11:0]s | rs1[4:0] | b001 | rd[4:0] | b0000011; + args_disass:"x%rd$d, %imm%(x%rs1$d)"; + val offs[XLEN] <= X[rs1]+imm; + if(rd!=0) X[rd]<=sext(MEM[offs]{16}); + } + LW { + encoding: imm[11:0]s | rs1[4:0] | b010 | rd[4:0] | b0000011; + args_disass:"x%rd$d, %imm%(x%rs1$d)"; + val offs[XLEN] <= X[rs1]+imm; + if(rd!=0) X[rd]<=sext(MEM[offs]{32}); + } + LBU { + encoding: imm[11:0]s | rs1[4:0] | b100 | rd[4:0] | b0000011; + args_disass:"x%rd$d, %imm%(x%rs1$d)"; + val offs[XLEN] <= X[rs1]+imm; + if(rd!=0) X[rd]<=zext(MEM[offs]); + } + LHU { + encoding: imm[11:0]s | rs1[4:0] | b101 | rd[4:0] | b0000011; + args_disass:"x%rd$d, %imm%(x%rs1$d)"; + val offs[XLEN] <= X[rs1]+imm; + if(rd!=0) X[rd]<=zext(MEM[offs]{16}); + } + SB { + encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b000 | imm[4:0]s | b0100011; + args_disass:"x%rs2$d, %imm%(x%rs1$d)"; + val offs[XLEN] <= X[rs1] + imm; + MEM[offs] <= X[rs2]; + } + SH { + encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b001 | imm[4:0]s | b0100011; + args_disass:"x%rs2$d, %imm%(x%rs1$d)"; + val offs[XLEN] <= X[rs1] + imm; + MEM[offs]{16} <= X[rs2]; + } + SW { + encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b010 | imm[4:0]s | b0100011; + args_disass:"x%rs2$d, %imm%(x%rs1$d)"; + val offs[XLEN] <= X[rs1] + imm; + MEM[offs]{32} <= X[rs2]; + } + ADDI { + encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b0010011; + args_disass:"x%rd$d, x%rs1$d, %imm%"; + if(rd != 0) X[rd] <= X[rs1] + imm; + } + SLTI { + encoding: imm[11:0]s | rs1[4:0] | b010 | rd[4:0] | b0010011; + args_disass:"x%rd$d, x%rs1$d, %imm%"; + if (rd != 0) X[rd] <= choose(X[rs1]s < imm's, 1, 0); + } + SLTIU { + encoding: imm[11:0]s | rs1[4:0] | b011 | rd[4:0] | b0010011; + args_disass:"x%rd$d, x%rs1$d, %imm%"; + val full_imm[XLEN] <= imm's; + if (rd != 0) X[rd] <= choose(X[rs1]'u < full_imm'u, 1, 0); + } + XORI { + encoding: imm[11:0]s | rs1[4:0] | b100 | rd[4:0] | b0010011; + args_disass:"x%rd$d, x%rs1$d, %imm%"; + if(rd != 0) X[rd] <= X[rs1] ^ imm; + } + ORI { + encoding: imm[11:0]s | rs1[4:0] | b110 | rd[4:0] | b0010011; + args_disass:"x%rd$d, x%rs1$d, %imm%"; + if(rd != 0) X[rd] <= X[rs1] | imm; + } + ANDI { + encoding: imm[11:0]s | rs1[4:0] | b111 | rd[4:0] | b0010011; + args_disass:"x%rd$d, x%rs1$d, %imm%"; + if(rd != 0) X[rd] <= X[rs1] & imm; + } + SLLI { + encoding: b0000000 | shamt[4:0] | rs1[4:0] | b001 | rd[4:0] | b0010011; + args_disass:"x%rd$d, x%rs1$d, %shamt%"; if(shamt > 31){ raise(0,0); } else { - if(rd != 0) X[rd] <= shrl(X[rs1], shamt); - } - } - SRAI { - encoding: b0100000 | shamt[4:0] | rs1[4:0] | b101 | rd[4:0] | b0010011; - args_disass:"x%rd$d, x%rs1$d, %shamt%"; - if(shamt > 31){ + if(rd != 0) X[rd] <= shll(X[rs1], shamt); + } + } + SRLI { + encoding: b0000000 | shamt[4:0] | rs1[4:0] | b101 | rd[4:0] | b0010011; + args_disass:"x%rd$d, x%rs1$d, %shamt%"; + if(shamt > 31){ raise(0,0); } else { - if(rd != 0) X[rd] <= shra(X[rs1], shamt); - } - } - ADD { - encoding: b0000000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0110011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; - if(rd != 0) X[rd] <= X[rs1] + X[rs2]; - } - SUB { - encoding: b0100000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0110011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; - if(rd != 0) X[rd] <= X[rs1] - X[rs2]; - } - SLL { - encoding: b0000000 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b0110011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; - if(rd != 0) X[rd] <= shll(X[rs1], X[rs2]&XLEN_BIT_MASK); - } - SLT { - encoding: b0000000 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0110011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; - if (rd != 0) X[rd] <= choose(X[rs1]s < X[rs2]s, 1, 0); - } - SLTU { - encoding: b0000000 | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0110011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; - if (rd != 0) X[rd] <= choose(zext(X[rs1]) < zext(X[rs2]), 1, 0); - } - XOR { - encoding: b0000000 | rs2[4:0] | rs1[4:0] | b100 | rd[4:0] | b0110011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; - if(rd != 0) X[rd] <= X[rs1] ^ X[rs2]; - } - SRL { - encoding: b0000000 | rs2[4:0] | rs1[4:0] | b101 | rd[4:0] | b0110011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; - if(rd != 0) X[rd] <= shrl(X[rs1], X[rs2]&XLEN_BIT_MASK); - } - SRA { - encoding: b0100000 | rs2[4:0] | rs1[4:0] | b101 | rd[4:0] | b0110011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; - if(rd != 0) X[rd] <= shra(X[rs1], X[rs2]&XLEN_BIT_MASK); - } - OR { - encoding: b0000000 | rs2[4:0] | rs1[4:0] | b110 | rd[4:0] | b0110011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; - if(rd != 0) X[rd] <= X[rs1] | X[rs2]; - } - AND { - encoding: b0000000 | rs2[4:0] | rs1[4:0] | b111 | rd[4:0] | b0110011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; - if(rd != 0) X[rd] <= X[rs1] & X[rs2]; - } - FENCE { - encoding: b0000 | pred[3:0] | succ[3:0] | rs1[4:0] | b000 | rd[4:0] | b0001111; - FENCE[fence] <= pred<<4 | succ; - } - FENCE_I(flush) { - encoding: imm[11:0] | rs1[4:0] | b001 | rd[4:0] | b0001111 ; - FENCE[fencei] <= imm; - } - ECALL(no_cont) { - encoding: b000000000000 | b00000 | b000 | b00000 | b1110011; - raise(0, 11); - } - EBREAK(no_cont) { - encoding: b000000000001 | b00000 | b000 | b00000 | b1110011; - raise(0, 3); - } - URET(no_cont) { - encoding: b0000000 | b00010 | b00000 | b000 | b00000 | b1110011; - leave(0); - } - SRET(no_cont) { - encoding: b0001000 | b00010 | b00000 | b000 | b00000 | b1110011; - leave(1); - } - MRET(no_cont) { - encoding: b0011000 | b00010 | b00000 | b000 | b00000 | b1110011; - leave(3); - } - WFI { - encoding: b0001000 | b00101 | b00000 | b000 | b00000 | b1110011; - wait(1); - } - SFENCE.VMA { - encoding: b0001001 | rs2[4:0] | rs1[4:0] | b000 | b00000 | b1110011; - FENCE[fencevmal] <= rs1; - FENCE[fencevmau] <= rs2; - } - CSRRW { - encoding: csr[11:0] | rs1[4:0] | b001 | rd[4:0] | b1110011; - args_disass:"x%rd$d, %csr$d, x%rs1$d"; + if(rd != 0) X[rd] <= shrl(X[rs1], shamt); + } + } + SRAI { + encoding: b0100000 | shamt[4:0] | rs1[4:0] | b101 | rd[4:0] | b0010011; + args_disass:"x%rd$d, x%rs1$d, %shamt%"; + if(shamt > 31){ + raise(0,0); + } else { + if(rd != 0) X[rd] <= shra(X[rs1], shamt); + } + } + ADD { + encoding: b0000000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0110011; + args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + if(rd != 0) X[rd] <= X[rs1] + X[rs2]; + } + SUB { + encoding: b0100000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0110011; + args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + if(rd != 0) X[rd] <= X[rs1] - X[rs2]; + } + SLL { + encoding: b0000000 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b0110011; + args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + if(rd != 0) X[rd] <= shll(X[rs1], X[rs2]&XLEN_BIT_MASK); + } + SLT { + encoding: b0000000 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0110011; + args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + if (rd != 0) X[rd] <= choose(X[rs1]s < X[rs2]s, 1, 0); + } + SLTU { + encoding: b0000000 | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0110011; + args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + if (rd != 0) X[rd] <= choose(zext(X[rs1]) < zext(X[rs2]), 1, 0); + } + XOR { + encoding: b0000000 | rs2[4:0] | rs1[4:0] | b100 | rd[4:0] | b0110011; + args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + if(rd != 0) X[rd] <= X[rs1] ^ X[rs2]; + } + SRL { + encoding: b0000000 | rs2[4:0] | rs1[4:0] | b101 | rd[4:0] | b0110011; + args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + if(rd != 0) X[rd] <= shrl(X[rs1], X[rs2]&XLEN_BIT_MASK); + } + SRA { + encoding: b0100000 | rs2[4:0] | rs1[4:0] | b101 | rd[4:0] | b0110011; + args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + if(rd != 0) X[rd] <= shra(X[rs1], X[rs2]&XLEN_BIT_MASK); + } + OR { + encoding: b0000000 | rs2[4:0] | rs1[4:0] | b110 | rd[4:0] | b0110011; + args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + if(rd != 0) X[rd] <= X[rs1] | X[rs2]; + } + AND { + encoding: b0000000 | rs2[4:0] | rs1[4:0] | b111 | rd[4:0] | b0110011; + args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + if(rd != 0) X[rd] <= X[rs1] & X[rs2]; + } + FENCE { + encoding: b0000 | pred[3:0] | succ[3:0] | rs1[4:0] | b000 | rd[4:0] | b0001111; + FENCE[fence] <= pred<<4 | succ; + } + FENCE_I(flush) { + encoding: imm[11:0] | rs1[4:0] | b001 | rd[4:0] | b0001111 ; + FENCE[fencei] <= imm; + } + ECALL(no_cont) { + encoding: b000000000000 | b00000 | b000 | b00000 | b1110011; + raise(0, 11); + } + EBREAK(no_cont) { + encoding: b000000000001 | b00000 | b000 | b00000 | b1110011; + raise(0, 3); + } + URET(no_cont) { + encoding: b0000000 | b00010 | b00000 | b000 | b00000 | b1110011; + leave(0); + } + SRET(no_cont) { + encoding: b0001000 | b00010 | b00000 | b000 | b00000 | b1110011; + leave(1); + } + MRET(no_cont) { + encoding: b0011000 | b00010 | b00000 | b000 | b00000 | b1110011; + leave(3); + } + WFI { + encoding: b0001000 | b00101 | b00000 | b000 | b00000 | b1110011; + wait(1); + } + SFENCE.VMA { + encoding: b0001001 | rs2[4:0] | rs1[4:0] | b000 | b00000 | b1110011; + FENCE[fencevmal] <= rs1; + FENCE[fencevmau] <= rs2; + } + CSRRW { + encoding: csr[11:0] | rs1[4:0] | b001 | rd[4:0] | b1110011; + args_disass:"x%rd$d, %csr$d, x%rs1$d"; val rs_val[XLEN] <= X[rs1]; - if(rd!=0){ - val csr_val[XLEN] <= CSR[csr]; + if(rd!=0){ + val csr_val[XLEN] <= CSR[csr]; CSR[csr] <= rs_val; // make sure Xrd is updated once CSR write succeeds - X[rd] <= csr_val; - } else { - CSR[csr] <= rs_val; - } - } - CSRRS { - encoding: csr[11:0] | rs1[4:0] | b010 | rd[4:0] | b1110011; - args_disass:"x%rd$d, %csr$d, x%rs1$d"; - val xrd[XLEN] <= CSR[csr]; - val xrs1[XLEN] <= X[rs1]; - if(rd!=0) X[rd] <= xrd; - if(rs1!=0) CSR[csr] <= xrd | xrs1; - } - CSRRC { - encoding: csr[11:0] | rs1[4:0] | b011 | rd[4:0] | b1110011; - args_disass:"x%rd$d, %csr$d, x%rs1$d"; - val xrd[XLEN] <= CSR[csr]; - val xrs1[XLEN] <= X[rs1]; - if(rd!=0) X[rd] <= xrd; - if(rs1!=0) CSR[csr] <= xrd & ~xrs1; - } - CSRRWI { - encoding: csr[11:0] | zimm[4:0] | b101 | rd[4:0] | b1110011; - args_disass:"x%rd$d, %csr$d, 0x%zimm$x"; - if(rd!=0) X[rd] <= CSR[csr]; - CSR[csr] <= zext(zimm); - } - CSRRSI { - encoding: csr[11:0] | zimm[4:0] | b110 | rd[4:0] | b1110011; - args_disass:"x%rd$d, %csr$d, 0x%zimm$x"; - val res[XLEN] <= CSR[csr]; - if(zimm!=0) CSR[csr] <= res | zext(zimm); - // make sure rd is written after csr write succeeds + X[rd] <= csr_val; + } else { + CSR[csr] <= rs_val; + } + } + CSRRS { + encoding: csr[11:0] | rs1[4:0] | b010 | rd[4:0] | b1110011; + args_disass:"x%rd$d, %csr$d, x%rs1$d"; + val xrd[XLEN] <= CSR[csr]; + val xrs1[XLEN] <= X[rs1]; + if(rd!=0) X[rd] <= xrd; + if(rs1!=0) CSR[csr] <= xrd | xrs1; + } + CSRRC { + encoding: csr[11:0] | rs1[4:0] | b011 | rd[4:0] | b1110011; + args_disass:"x%rd$d, %csr$d, x%rs1$d"; + val xrd[XLEN] <= CSR[csr]; + val xrs1[XLEN] <= X[rs1]; + if(rd!=0) X[rd] <= xrd; + if(rs1!=0) CSR[csr] <= xrd & ~xrs1; + } + CSRRWI { + encoding: csr[11:0] | zimm[4:0] | b101 | rd[4:0] | b1110011; + args_disass:"x%rd$d, %csr$d, 0x%zimm$x"; + if(rd!=0) X[rd] <= CSR[csr]; + CSR[csr] <= zext(zimm); + } + CSRRSI { + encoding: csr[11:0] | zimm[4:0] | b110 | rd[4:0] | b1110011; + args_disass:"x%rd$d, %csr$d, 0x%zimm$x"; + val res[XLEN] <= CSR[csr]; + if(zimm!=0) CSR[csr] <= res | zext(zimm); + // make sure rd is written after csr write succeeds if(rd!=0) X[rd] <= res; - } - CSRRCI { - encoding: csr[11:0] | zimm[4:0] | b111 | rd[4:0] | b1110011; - args_disass:"x%rd$d, %csr$d, 0x%zimm$x"; - val res[XLEN] <= CSR[csr]; - if(rd!=0) X[rd] <= res; - if(zimm!=0) CSR[csr] <= res & ~zext(zimm, XLEN); - } - } + } + CSRRCI { + encoding: csr[11:0] | zimm[4:0] | b111 | rd[4:0] | b1110011; + args_disass:"x%rd$d, %csr$d, 0x%zimm$x"; + val res[XLEN] <= CSR[csr]; + if(rd!=0) X[rd] <= res; + if(zimm!=0) CSR[csr] <= res & ~zext(zimm, XLEN); + } + } } diff --git a/riscv/gen_input/RV32M.core_desc b/riscv/gen_input/RV32M.core_desc index 2296923..a115295 100644 --- a/riscv/gen_input/RV32M.core_desc +++ b/riscv/gen_input/RV32M.core_desc @@ -1,97 +1,97 @@ import "RV32IBase.core_desc" InsructionSet RV32M extends RV32IBase { - constants { - MAXLEN:=128 - } - instructions{ - MUL{ - encoding: b0000001 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0110011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; - if(rd != 0){ - val res[MAXLEN] <= zext(X[rs1], MAXLEN) * zext(X[rs2], MAXLEN); - X[rd]<= zext(res , XLEN); - } - } - MULH { - encoding: b0000001 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b0110011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; - if(rd != 0){ - val res[MAXLEN] <= sext(X[rs1], MAXLEN) * sext(X[rs2], MAXLEN); + constants { + MAXLEN:=128 + } + instructions{ + MUL{ + encoding: b0000001 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0110011; + args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + if(rd != 0){ + val res[MAXLEN] <= zext(X[rs1], MAXLEN) * zext(X[rs2], MAXLEN); + X[rd]<= zext(res , XLEN); + } + } + MULH { + encoding: b0000001 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b0110011; + args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + if(rd != 0){ + val res[MAXLEN] <= sext(X[rs1], MAXLEN) * sext(X[rs2], MAXLEN); X[rd]<= zext(res >> XLEN, XLEN); - } - } - MULHSU { - encoding: b0000001 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0110011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; - if(rd != 0){ + } + } + MULHSU { + encoding: b0000001 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0110011; + args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + if(rd != 0){ val res[MAXLEN] <= sext(X[rs1], MAXLEN) * zext(X[rs2], MAXLEN); X[rd]<= zext(res >> XLEN, XLEN); - } - } - MULHU { - encoding: b0000001 | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0110011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; - if(rd != 0){ + } + } + MULHU { + encoding: b0000001 | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0110011; + args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + if(rd != 0){ val res[MAXLEN] <= zext(X[rs1], MAXLEN) * zext(X[rs2], MAXLEN); X[rd]<= zext(res >> XLEN, XLEN); - } - } - DIV { - encoding: b0000001 | rs2[4:0] | rs1[4:0] | b100 | rd[4:0] | b0110011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; - if(rd != 0){ - if(X[rs2]!=0){ - val M1[XLEN] <= -1; - val MMIN[XLEN] <= -1<<(XLEN-1); - if(X[rs1]s==MMIN's) - if(X[rs2]s==M1's) - X[rd]<=MMIN; - else - X[rd] <= X[rs1]s / X[rs2]s; - else - X[rd] <= X[rs1]s / X[rs2]s; - }else - X[rd] <= -1; - } - } - DIVU { - encoding: b0000001 | rs2[4:0] | rs1[4:0] | b101 | rd[4:0] | b0110011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; - if(rd != 0){ - if(X[rs2]!=0) - X[rd] <= zext(X[rs1], 32) / zext(X[rs2], 32); - else - X[rd] <= -1; - } - } - REM { - encoding: b0000001 | rs2[4:0] | rs1[4:0] | b110 | rd[4:0] | b0110011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; - if(rd != 0){ - if(X[rs2]!=0) { - val M1[XLEN] <= -1; - val MMIN[XLEN] <= -1<<(XLEN-1); - if(X[rs1]s==MMIN's) - if(X[rs2]s==M1's) - X[rd] <= 0; - else - X[rd] <= sext(X[rs1], 32) % sext(X[rs2], 32); - else - X[rd] <= sext(X[rs1], 32) % sext(X[rs2], 32); - } else - X[rd] <= X[rs1]; - } - } - REMU { - encoding: b0000001 | rs2[4:0] | rs1[4:0] | b111 | rd[4:0] | b0110011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; - if(rd != 0){ - if(X[rs2]!=0) - X[rd] <= zext(X[rs1], 32) % zext(X[rs2], 32); - else - X[rd] <= X[rs1]; - } - } - } + } + } + DIV { + encoding: b0000001 | rs2[4:0] | rs1[4:0] | b100 | rd[4:0] | b0110011; + args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + if(rd != 0){ + if(X[rs2]!=0){ + val M1[XLEN] <= -1; + val MMIN[XLEN] <= -1<<(XLEN-1); + if(X[rs1]s==MMIN's) + if(X[rs2]s==M1's) + X[rd]<=MMIN; + else + X[rd] <= X[rs1]s / X[rs2]s; + else + X[rd] <= X[rs1]s / X[rs2]s; + }else + X[rd] <= -1; + } + } + DIVU { + encoding: b0000001 | rs2[4:0] | rs1[4:0] | b101 | rd[4:0] | b0110011; + args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + if(rd != 0){ + if(X[rs2]!=0) + X[rd] <= zext(X[rs1], 32) / zext(X[rs2], 32); + else + X[rd] <= -1; + } + } + REM { + encoding: b0000001 | rs2[4:0] | rs1[4:0] | b110 | rd[4:0] | b0110011; + args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + if(rd != 0){ + if(X[rs2]!=0) { + val M1[XLEN] <= -1; + val MMIN[XLEN] <= -1<<(XLEN-1); + if(X[rs1]s==MMIN's) + if(X[rs2]s==M1's) + X[rd] <= 0; + else + X[rd] <= sext(X[rs1], 32) % sext(X[rs2], 32); + else + X[rd] <= sext(X[rs1], 32) % sext(X[rs2], 32); + } else + X[rd] <= X[rs1]; + } + } + REMU { + encoding: b0000001 | rs2[4:0] | rs1[4:0] | b111 | rd[4:0] | b0110011; + args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + if(rd != 0){ + if(X[rs2]!=0) + X[rd] <= zext(X[rs1], 32) % zext(X[rs2], 32); + else + X[rd] <= X[rs1]; + } + } + } } \ No newline at end of file diff --git a/riscv/gen_input/RV64A.core_desc b/riscv/gen_input/RV64A.core_desc index 91ffb3d..5080d11 100644 --- a/riscv/gen_input/RV64A.core_desc +++ b/riscv/gen_input/RV64A.core_desc @@ -2,111 +2,111 @@ import "RV64IBase.core_desc" import "RV32A.core_desc" InsructionSet RV64A extends RV64IBase { - - address_spaces { - RES[8] - } - - instructions{ - LR.D { - encoding: b00010 | aq[0:0] | rl[0:0] | b00000 | rs1[4:0] | b011 | rd[4:0] | b0101111; - args_disass: "x%rd$d, x%rs1$d"; - if(rd!=0){ - val offs[XLEN] <= X[rs1]; - X[rd]<= sext(MEM[offs]{64}, XLEN); - RES[offs]{64}<=sext(-1, 64); - } - } - SC.D { - encoding: b00011 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111; - args_disass: "x%rd$d, x%rs1$d, x%rs2$d"; - val offs[XLEN] <= X[rs1]; - val res[64] <= RES[offs]; - if(res!=0){ - MEM[offs]{64} <= X[rs2]; - if(rd!=0) X[rd]<=0; - } else{ - if(rd!=0) X[rd]<= 1; - } - } - AMOSWAP.D{ - encoding: b00001 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111; - args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%a,rel=%rl)"; - val offs[XLEN] <= X[rs1]; - if(rd!=0) X[rd] <= sext(MEM[offs]{64}); - MEM[offs]{64} <= X[rs2]; - } - AMOADD.D{ - encoding: b00000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111; - args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%a,rel=%rl)"; - val offs[XLEN] <= X[rs1]; - val res[XLEN] <= sext(MEM[offs]{64}); - if(rd!=0) X[rd]<=res; - val res2[XLEN] <= res + X[rs2]; - MEM[offs]{64}<=res2; - } - AMOXOR.D{ - encoding: b00100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111; - args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%a,rel=%rl)"; - val offs[XLEN] <= X[rs1]; - val res[XLEN] <= sext(MEM[offs]{64}); - if(rd!=0) X[rd] <= res; - val res2[XLEN] <= res ^ X[rs2]; - MEM[offs]{64} <= res2; - } - AMOAND.D{ - encoding: b01100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111; - args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%a,rel=%rl)"; - val offs[XLEN] <= X[rs1]; - val res[XLEN] <= sext(MEM[offs]{64}); - if(rd!=0) X[rd] <= res; - val res2[XLEN] <= res & X[rs2]; - MEM[offs]{64} <= res2; - } - AMOOR.D { - encoding: b01000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111; - args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%a,rel=%rl)"; - val offs[XLEN] <= X[rs1]; - val res[XLEN] <= sext(MEM[offs]{64}); - if(rd!=0) X[rd] <= res; - val res2[XLEN] <= res | X[rs2]; - MEM[offs]{64} <= res2; - } - AMOMIN.D{ - encoding: b10000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111; - args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%a,rel=%rl)"; - val offs[XLEN] <= X[rs1]; - val res[XLEN] <= sext(MEM[offs]{64}); - if(rd!=0) X[rd] <= res; - val res2[XLEN] <= choose(res s > X[rs2]s, X[rs2], res); - MEM[offs]{64} <= res; - } - AMOMAX.D{ - encoding: b10100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111; - args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%a,rel=%rl)"; - val offs[XLEN] <= X[rs1]; - val res[XLEN] <= sext(MEM[offs]{64}); - if(rd!=0) X[rd] <= res; - val res2[XLEN] <= choose(res s < X[rs2]s, X[rs2], res); - MEM[offs]{64} <= res2; - } - AMOMINU.D{ - encoding: b11000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111; - args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%a,rel=%rl)"; - val offs[XLEN] <= X[rs1]; - val res[XLEN] <= zext(MEM[offs]{64}); - if(rd!=0) X[rd] <= res; - val res2[XLEN] <= choose(res > X[rs2], X[rs2], res); - MEM[offs]{64} <= res2; - } - AMOMAXU.D{ - encoding: b11100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111; - args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%a,rel=%rl)"; - val offs[XLEN] <= X[rs1]; - val res[XLEN] <= zext(MEM[offs]{64}); - if(rd!=0) X[rd] <= res; - val res2[XLEN] <= choose(res < X[rs2], X[rs2], res); - MEM[offs]{64} <= res2; - } - } + + address_spaces { + RES[8] + } + + instructions{ + LR.D { + encoding: b00010 | aq[0:0] | rl[0:0] | b00000 | rs1[4:0] | b011 | rd[4:0] | b0101111; + args_disass: "x%rd$d, x%rs1$d"; + if(rd!=0){ + val offs[XLEN] <= X[rs1]; + X[rd]<= sext(MEM[offs]{64}, XLEN); + RES[offs]{64}<=sext(-1, 64); + } + } + SC.D { + encoding: b00011 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111; + args_disass: "x%rd$d, x%rs1$d, x%rs2$d"; + val offs[XLEN] <= X[rs1]; + val res[64] <= RES[offs]; + if(res!=0){ + MEM[offs]{64} <= X[rs2]; + if(rd!=0) X[rd]<=0; + } else{ + if(rd!=0) X[rd]<= 1; + } + } + AMOSWAP.D{ + encoding: b00001 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111; + args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%a,rel=%rl)"; + val offs[XLEN] <= X[rs1]; + if(rd!=0) X[rd] <= sext(MEM[offs]{64}); + MEM[offs]{64} <= X[rs2]; + } + AMOADD.D{ + encoding: b00000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111; + args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%a,rel=%rl)"; + val offs[XLEN] <= X[rs1]; + val res[XLEN] <= sext(MEM[offs]{64}); + if(rd!=0) X[rd]<=res; + val res2[XLEN] <= res + X[rs2]; + MEM[offs]{64}<=res2; + } + AMOXOR.D{ + encoding: b00100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111; + args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%a,rel=%rl)"; + val offs[XLEN] <= X[rs1]; + val res[XLEN] <= sext(MEM[offs]{64}); + if(rd!=0) X[rd] <= res; + val res2[XLEN] <= res ^ X[rs2]; + MEM[offs]{64} <= res2; + } + AMOAND.D{ + encoding: b01100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111; + args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%a,rel=%rl)"; + val offs[XLEN] <= X[rs1]; + val res[XLEN] <= sext(MEM[offs]{64}); + if(rd!=0) X[rd] <= res; + val res2[XLEN] <= res & X[rs2]; + MEM[offs]{64} <= res2; + } + AMOOR.D { + encoding: b01000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111; + args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%a,rel=%rl)"; + val offs[XLEN] <= X[rs1]; + val res[XLEN] <= sext(MEM[offs]{64}); + if(rd!=0) X[rd] <= res; + val res2[XLEN] <= res | X[rs2]; + MEM[offs]{64} <= res2; + } + AMOMIN.D{ + encoding: b10000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111; + args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%a,rel=%rl)"; + val offs[XLEN] <= X[rs1]; + val res[XLEN] <= sext(MEM[offs]{64}); + if(rd!=0) X[rd] <= res; + val res2[XLEN] <= choose(res s > X[rs2]s, X[rs2], res); + MEM[offs]{64} <= res; + } + AMOMAX.D{ + encoding: b10100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111; + args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%a,rel=%rl)"; + val offs[XLEN] <= X[rs1]; + val res[XLEN] <= sext(MEM[offs]{64}); + if(rd!=0) X[rd] <= res; + val res2[XLEN] <= choose(res s < X[rs2]s, X[rs2], res); + MEM[offs]{64} <= res2; + } + AMOMINU.D{ + encoding: b11000 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111; + args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%a,rel=%rl)"; + val offs[XLEN] <= X[rs1]; + val res[XLEN] <= zext(MEM[offs]{64}); + if(rd!=0) X[rd] <= res; + val res2[XLEN] <= choose(res > X[rs2], X[rs2], res); + MEM[offs]{64} <= res2; + } + AMOMAXU.D{ + encoding: b11100 | aq[0:0] | rl[0:0] | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0101111; + args_disass: "x%rd$d, x%rs1$d, x%rs2$d (aqu=%a,rel=%rl)"; + val offs[XLEN] <= X[rs1]; + val res[XLEN] <= zext(MEM[offs]{64}); + if(rd!=0) X[rd] <= res; + val res2[XLEN] <= choose(res < X[rs2], X[rs2], res); + MEM[offs]{64} <= res2; + } + } } \ No newline at end of file diff --git a/riscv/gen_input/RV64IBase.core_desc b/riscv/gen_input/RV64IBase.core_desc index 013b716..00bcaf0 100644 --- a/riscv/gen_input/RV64IBase.core_desc +++ b/riscv/gen_input/RV64IBase.core_desc @@ -1,116 +1,116 @@ import "RV32IBase.core_desc" InsructionSet RV64IBase extends RV32IBase { - instructions{ - LWU { // 80000104: 0000ef03 lwu t5,0(ra) - encoding: imm[11:0]s | rs1[4:0] | b110 | rd[4:0] | b0000011; - args_disass:"x%rd$d, %imm%(x%rs1$d)"; - val offs[XLEN] <= X[rs1]+imm; - if(rd!=0) X[rd]<=zext(MEM[offs]{32}); - } - LD{ - encoding: imm[11:0]s | rs1[4:0] | b011 | rd[4:0] | b0000011; - args_disass:"x%rd$d, %imm%(x%rs1$d)"; - val offs[XLEN] <= X[rs1]+imm; - if(rd!=0) X[rd]<=sext(MEM[offs]{64}); - } - SD{ - encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b011 | imm[4:0]s | b0100011; - args_disass:"x%rs2$d, %imm%(x%rs1$d)"; - val offs[XLEN] <= X[rs1] + imm; - MEM[offs]{64} <= X[rs2]; - } - SLLI { - encoding: b000000 | shamt[5:0] | rs1[4:0] | b001 | rd[4:0] | b0010011; - args_disass:"x%rd$d, x%rs1$d, %shamt%"; - if(rd != 0) X[rd] <= shll(X[rs1], shamt); - } - SRLI { - encoding: b000000 | shamt[5:0] | rs1[4:0] | b101 | rd[4:0] | b0010011; - args_disass:"x%rd$d, x%rs1$d, %shamt%"; - if(rd != 0) X[rd] <= shrl(X[rs1], shamt); - } - SRAI { - encoding: b010000 | shamt[5:0] | rs1[4:0] | b101 | rd[4:0] | b0010011; - args_disass:"x%rd$d, x%rs1$d, %shamt%"; - if(rd != 0) X[rd] <= shra(X[rs1], shamt); - } - ADDIW { - encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b0011011; - args_disass:"x%rd$d, x%rs1$d, %imm%"; - if(rd != 0){ - val res[32] <= X[rs1]{32} + imm; - X[rd] <= sext(res); - } - } - SLLIW { - encoding: b0000000 | shamt[4:0] | rs1[4:0] | b001 | rd[4:0] | b0011011; - args_disass:"x%rd$d, x%rs1$d, %shamt%"; - if(rd != 0){ - val sh_val[32] <= shll(X[rs1]{32}, shamt); - X[rd] <= sext(sh_val); - } - } - SRLIW { - encoding: b0000000 | shamt[4:0] | rs1[4:0] | b101 | rd[4:0] | b0011011; - args_disass:"x%rd$d, x%rs1$d, %shamt%"; - if(rd != 0){ - val sh_val[32] <= shrl(X[rs1]{32}, shamt); - X[rd] <= sext(sh_val); - } - } - SRAIW { - encoding: b0100000 | shamt[4:0] | rs1[4:0] | b101 | rd[4:0] | b0011011; - args_disass:"x%rd$d, x%rs1$d, %shamt%"; - if(rd != 0){ - val sh_val[32] <= shra(X[rs1]{32}, shamt); - X[rd] <= sext(sh_val); - } - } - ADDW { - encoding: b0000000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0111011; - if(rd != 0){ - val res[32] <= X[rs1]{32} + X[rs2]{32}; - X[rd] <= sext(res); - } - } - SUBW { - encoding: b0100000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0111011; - if(rd != 0){ - val res[32] <= X[rs1]{32} - X[rs2]{32}; - X[rd] <= sext(res); - } - } - SLLW { - encoding: b0000000 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b0111011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; - if(rd != 0){ - val mask[32] <= 0x1f; - val count[32] <= X[rs2]{32} & mask; - val sh_val[32] <= shll(X[rs1]{32}, count); - X[rd] <= sext(sh_val); - } - } - SRLW { - encoding: b0000000 | rs2[4:0] | rs1[4:0] | b101 | rd[4:0] | b0111011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; - if(rd != 0){ + instructions{ + LWU { // 80000104: 0000ef03 lwu t5,0(ra) + encoding: imm[11:0]s | rs1[4:0] | b110 | rd[4:0] | b0000011; + args_disass:"x%rd$d, %imm%(x%rs1$d)"; + val offs[XLEN] <= X[rs1]+imm; + if(rd!=0) X[rd]<=zext(MEM[offs]{32}); + } + LD{ + encoding: imm[11:0]s | rs1[4:0] | b011 | rd[4:0] | b0000011; + args_disass:"x%rd$d, %imm%(x%rs1$d)"; + val offs[XLEN] <= X[rs1]+imm; + if(rd!=0) X[rd]<=sext(MEM[offs]{64}); + } + SD{ + encoding: imm[11:5]s | rs2[4:0] | rs1[4:0] | b011 | imm[4:0]s | b0100011; + args_disass:"x%rs2$d, %imm%(x%rs1$d)"; + val offs[XLEN] <= X[rs1] + imm; + MEM[offs]{64} <= X[rs2]; + } + SLLI { + encoding: b000000 | shamt[5:0] | rs1[4:0] | b001 | rd[4:0] | b0010011; + args_disass:"x%rd$d, x%rs1$d, %shamt%"; + if(rd != 0) X[rd] <= shll(X[rs1], shamt); + } + SRLI { + encoding: b000000 | shamt[5:0] | rs1[4:0] | b101 | rd[4:0] | b0010011; + args_disass:"x%rd$d, x%rs1$d, %shamt%"; + if(rd != 0) X[rd] <= shrl(X[rs1], shamt); + } + SRAI { + encoding: b010000 | shamt[5:0] | rs1[4:0] | b101 | rd[4:0] | b0010011; + args_disass:"x%rd$d, x%rs1$d, %shamt%"; + if(rd != 0) X[rd] <= shra(X[rs1], shamt); + } + ADDIW { + encoding: imm[11:0]s | rs1[4:0] | b000 | rd[4:0] | b0011011; + args_disass:"x%rd$d, x%rs1$d, %imm%"; + if(rd != 0){ + val res[32] <= X[rs1]{32} + imm; + X[rd] <= sext(res); + } + } + SLLIW { + encoding: b0000000 | shamt[4:0] | rs1[4:0] | b001 | rd[4:0] | b0011011; + args_disass:"x%rd$d, x%rs1$d, %shamt%"; + if(rd != 0){ + val sh_val[32] <= shll(X[rs1]{32}, shamt); + X[rd] <= sext(sh_val); + } + } + SRLIW { + encoding: b0000000 | shamt[4:0] | rs1[4:0] | b101 | rd[4:0] | b0011011; + args_disass:"x%rd$d, x%rs1$d, %shamt%"; + if(rd != 0){ + val sh_val[32] <= shrl(X[rs1]{32}, shamt); + X[rd] <= sext(sh_val); + } + } + SRAIW { + encoding: b0100000 | shamt[4:0] | rs1[4:0] | b101 | rd[4:0] | b0011011; + args_disass:"x%rd$d, x%rs1$d, %shamt%"; + if(rd != 0){ + val sh_val[32] <= shra(X[rs1]{32}, shamt); + X[rd] <= sext(sh_val); + } + } + ADDW { + encoding: b0000000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0111011; + if(rd != 0){ + val res[32] <= X[rs1]{32} + X[rs2]{32}; + X[rd] <= sext(res); + } + } + SUBW { + encoding: b0100000 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0111011; + if(rd != 0){ + val res[32] <= X[rs1]{32} - X[rs2]{32}; + X[rd] <= sext(res); + } + } + SLLW { + encoding: b0000000 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b0111011; + args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + if(rd != 0){ val mask[32] <= 0x1f; val count[32] <= X[rs2]{32} & mask; - val sh_val[32] <= shrl(X[rs1]{32}, count); - X[rd] <= sext(sh_val); - } - } - SRAW { - encoding: b0100000 | rs2[4:0] | rs1[4:0] | b101 | rd[4:0] | b0111011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; - if(rd != 0){ + val sh_val[32] <= shll(X[rs1]{32}, count); + X[rd] <= sext(sh_val); + } + } + SRLW { + encoding: b0000000 | rs2[4:0] | rs1[4:0] | b101 | rd[4:0] | b0111011; + args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + if(rd != 0){ val mask[32] <= 0x1f; val count[32] <= X[rs2]{32} & mask; - val sh_val[32] <= shra(X[rs1]{32}, count); - X[rd] <= sext(sh_val); - } - } - } + val sh_val[32] <= shrl(X[rs1]{32}, count); + X[rd] <= sext(sh_val); + } + } + SRAW { + encoding: b0100000 | rs2[4:0] | rs1[4:0] | b101 | rd[4:0] | b0111011; + args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + if(rd != 0){ + val mask[32] <= 0x1f; + val count[32] <= X[rs2]{32} & mask; + val sh_val[32] <= shra(X[rs1]{32}, count); + X[rd] <= sext(sh_val); + } + } + } } diff --git a/riscv/gen_input/RV64M.core_desc b/riscv/gen_input/RV64M.core_desc index 32728bb..cb53da9 100644 --- a/riscv/gen_input/RV64M.core_desc +++ b/riscv/gen_input/RV64M.core_desc @@ -1,41 +1,41 @@ import "RV64IBase.core_desc" InsructionSet RV64M extends RV64IBase { - instructions{ - MULW{ - encoding: b0000001 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0111011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; - if(rd != 0){ - X[rd]<= X[rs1] * X[rs2]; - } - } - DIVW { - encoding: b0000001 | rs2[4:0] | rs1[4:0] | b100 | rd[4:0] | b0111011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; - if(rd != 0){ - X[rd] <= X[rs1]s / X[rs2]s; - } - } - DIVUW { - encoding: b0000001 | rs2[4:0] | rs1[4:0] | b101 | rd[4:0] | b0111011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; - if(rd != 0){ - X[rd] <= X[rs1] / X[rs2]; - } - } - REMW { - encoding: b0000001 | rs2[4:0] | rs1[4:0] | b110 | rd[4:0] | b0111011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; - if(rd != 0){ - X[rd] <= X[rs1]s % X[rs2]s; - } - } - REMUW { - encoding: b0000001 | rs2[4:0] | rs1[4:0] | b111 | rd[4:0] | b0111011; - args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; - if(rd != 0){ - X[rd] <= X[rs1] % X[rs2]; - } - } - } + instructions{ + MULW{ + encoding: b0000001 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0111011; + args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + if(rd != 0){ + X[rd]<= X[rs1] * X[rs2]; + } + } + DIVW { + encoding: b0000001 | rs2[4:0] | rs1[4:0] | b100 | rd[4:0] | b0111011; + args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + if(rd != 0){ + X[rd] <= X[rs1]s / X[rs2]s; + } + } + DIVUW { + encoding: b0000001 | rs2[4:0] | rs1[4:0] | b101 | rd[4:0] | b0111011; + args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + if(rd != 0){ + X[rd] <= X[rs1] / X[rs2]; + } + } + REMW { + encoding: b0000001 | rs2[4:0] | rs1[4:0] | b110 | rd[4:0] | b0111011; + args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + if(rd != 0){ + X[rd] <= X[rs1]s % X[rs2]s; + } + } + REMUW { + encoding: b0000001 | rs2[4:0] | rs1[4:0] | b111 | rd[4:0] | b0111011; + args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; + if(rd != 0){ + X[rd] <= X[rs1] % X[rs2]; + } + } + } } \ No newline at end of file diff --git a/riscv/gen_input/minres_rv.core_desc b/riscv/gen_input/minres_rv.core_desc index b5d82fe..c0cb5f2 100644 --- a/riscv/gen_input/minres_rv.core_desc +++ b/riscv/gen_input/minres_rv.core_desc @@ -8,7 +8,6 @@ import "RV64IBase.core_desc" //import "RV64M.core_desc" import "RV64A.core_desc" - Core RV32IMAC provides RV32IBase, RV32M, RV32A, RV32IC { template:"vm_riscv.in.cpp"; constants { @@ -17,8 +16,8 @@ Core RV32IMAC provides RV32IBase, RV32M, RV32A, RV32IC { // definitions for the architecture wrapper // XL ZYXWVUTSRQPONMLKJIHGFEDCBA MISA_VAL:=0b01000000000101000001000100000101; - PGSIZE := 4096; //1 << 12; - PGMASK := 4095; //PGSIZE-1 + PGSIZE := 0x1000; //1 << 12; + PGMASK := 0xfff; //PGSIZE-1 } } @@ -30,8 +29,8 @@ Core RV32GC provides RV32IBase, RV32M, RV32A, RV32IC, RV32F, RV32FC, RV32D, RV32 // definitions for the architecture wrapper // XL ZYXWVUTSRQPONMLKJIHGFEDCBA MISA_VAL:=0b01000000000101000001000100101101; - PGSIZE := 4096; //1 << 12; - PGMASK := 4095; //PGSIZE-1 + PGSIZE := 0x1000; //1 << 12; + PGMASK := 0xfff; //PGSIZE-1 } } @@ -44,7 +43,7 @@ Core RV64IA provides RV64IBase, RV64A, RV32A { // definitions for the architecture wrapper // XL ZYXWVUTSRQPONMLKJIHGFEDCBA MISA_VAL:=0b10000000000001000000000100000001; - PGSIZE := 4096; //1 << 12; - PGMASK := 4095; //PGSIZE-1 + PGSIZE := 0x1000; //1 << 12; + PGMASK := 0xfff; //PGSIZE-1 } } diff --git a/riscv/gen_input/templates/incl-CORENAME.h.gtl b/riscv/gen_input/templates/incl-CORENAME.h.gtl index 5e53476..0b5ecb0 100644 --- a/riscv/gen_input/templates/incl-CORENAME.h.gtl +++ b/riscv/gen_input/templates/incl-CORENAME.h.gtl @@ -80,6 +80,8 @@ struct traits<${coreDef.name.toLowerCase()}> { using addr_t = uint${addrDataWidth}_t; + using code_word_t = uint${addrDataWidth}_t; //TODO: check removal + using virt_addr_t = iss::typed_addr_t; using phys_addr_t = iss::typed_addr_t; diff --git a/riscv/gen_input/templates/vm-vm_CORENAME.cpp.gtl b/riscv/gen_input/templates/vm-vm_CORENAME.cpp.gtl index d4552cc..6233125 100644 --- a/riscv/gen_input/templates/vm-vm_CORENAME.cpp.gtl +++ b/riscv/gen_input/templates/vm-vm_CORENAME.cpp.gtl @@ -320,6 +320,8 @@ template inline void vm_impl::gen_trap_check(llvm::BasicBl bb, this->trap_blk, 1); } +} // namespace ${coreDef.name.toLowerCase()} + template <> std::unique_ptr create(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) { std::unique_ptr<${coreDef.name.toLowerCase()}::vm_impl> ret = diff --git a/riscv/incl/iss/arch/rv32gc.h b/riscv/incl/iss/arch/rv32gc.h index 0f9d93e..6fbc025 100644 --- a/riscv/incl/iss/arch/rv32gc.h +++ b/riscv/incl/iss/arch/rv32gc.h @@ -48,7 +48,7 @@ struct traits { constexpr static char const* const core_type = "RV32GC"; - enum constants {XLEN=32, FLEN=64, PCLEN=32, MISA_VAL=1075056941, PGSIZE=4096, PGMASK=4095}; + enum constants {XLEN=32, FLEN=64, PCLEN=32, MISA_VAL=0b1000000000101000001000100101101, PGSIZE=0x1000, PGMASK=0xfff}; constexpr static unsigned FP_REGS_SIZE = 64; diff --git a/riscv/incl/iss/arch/rv32imac.h b/riscv/incl/iss/arch/rv32imac.h index 571b758..923d16e 100644 --- a/riscv/incl/iss/arch/rv32imac.h +++ b/riscv/incl/iss/arch/rv32imac.h @@ -48,7 +48,7 @@ struct traits { constexpr static char const* const core_type = "RV32IMAC"; - enum constants {XLEN=32, PCLEN=32, MISA_VAL=1075056901, PGSIZE=4096, PGMASK=4095}; + enum constants {XLEN=32, PCLEN=32, MISA_VAL=0b1000000000101000001000100000101, PGSIZE=0x1000, PGMASK=0xfff}; constexpr static unsigned FP_REGS_SIZE = 0; diff --git a/riscv/incl/iss/arch/rv64ia.h b/riscv/incl/iss/arch/rv64ia.h index 10a8989..51fc774 100644 --- a/riscv/incl/iss/arch/rv64ia.h +++ b/riscv/incl/iss/arch/rv64ia.h @@ -48,7 +48,7 @@ struct traits { constexpr static char const* const core_type = "RV64IA"; - enum constants {XLEN=64, PCLEN=64, MISA_VAL=2147746049, PGSIZE=4096, PGMASK=4095}; + enum constants {XLEN=64, PCLEN=64, MISA_VAL=0b10000000000001000000000100000001, PGSIZE=0x1000, PGMASK=0xfff}; constexpr static unsigned FP_REGS_SIZE = 0; diff --git a/riscv/src/internal/vm_rv32gc.cpp b/riscv/src/internal/vm_rv32gc.cpp index 5514005..d33bf1b 100644 --- a/riscv/src/internal/vm_rv32gc.cpp +++ b/riscv/src/internal/vm_rv32gc.cpp @@ -112,15 +112,10 @@ protected: void gen_trap_check(llvm::BasicBlock *bb); - inline llvm::Value *gen_reg_load(unsigned i, unsigned level = 0) { return this->builder.CreateLoad(get_reg_ptr(i), false); } - llvm::Value* gen_fdispatch(std::string fname, const std::vector& args); - - llvm::Value* gen_dispatch(std::string name, llvm::Value*, llvm::Value*, llvm::Value*); - inline void gen_set_pc(virt_addr_t pc, unsigned reg_num) { llvm::Value *next_pc_v = this->builder.CreateSExtOrTrunc(this->gen_const(traits::XLEN, pc.val), this->get_type(traits::XLEN)); @@ -541,8 +536,8 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->gen_const(32U, fld_imm_val); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = this->gen_const(32U, fld_imm_val); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 0); @@ -575,10 +570,10 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateAdd( + Value* Xtmp0_val = this->builder.CreateAdd( cur_pc_val, this->gen_const(32U, fld_imm_val)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 1); @@ -611,10 +606,10 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateAdd( + Value* Xtmp0_val = this->builder.CreateAdd( cur_pc_val, this->gen_const(32U, 4)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } Value* PC_val = this->builder.CreateAdd( cur_pc_val, @@ -650,17 +645,17 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateAdd( + Value* Xtmp0_val = this->builder.CreateAdd( cur_pc_val, this->gen_const(32U, 4)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } Value* ret_val = this->builder.CreateAdd( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(32U, fld_imm_val)); Value* PC_val = this->builder.CreateAnd( ret_val, - this->builder.CreateNot(this->gen_const(32U, 1))); + this->builder.CreateNot(this->gen_const(32U, 0x1))); this->builder.CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); this->gen_sync(iss::POST_SYNC, 3); this->gen_trap_check(this->leave_blk); @@ -955,11 +950,11 @@ private: this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(32U, fld_imm_val)); if(fld_rd_val != 0){ - Value* X_rd_val = this->gen_ext( + Value* Xtmp0_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 8/8), 32, true); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 10); @@ -996,11 +991,11 @@ private: this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(32U, fld_imm_val)); if(fld_rd_val != 0){ - Value* X_rd_val = this->gen_ext( + Value* Xtmp0_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 16/8), 32, true); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 11); @@ -1037,11 +1032,11 @@ private: this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(32U, fld_imm_val)); if(fld_rd_val != 0){ - Value* X_rd_val = this->gen_ext( + Value* Xtmp0_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 32/8), 32, true); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 12); @@ -1078,11 +1073,11 @@ private: this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(32U, fld_imm_val)); if(fld_rd_val != 0){ - Value* X_rd_val = this->gen_ext( + Value* Xtmp0_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 8/8), 32, false); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 13); @@ -1119,11 +1114,11 @@ private: this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(32U, fld_imm_val)); if(fld_rd_val != 0){ - Value* X_rd_val = this->gen_ext( + Value* Xtmp0_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 16/8), 32, false); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 14); @@ -1159,11 +1154,11 @@ private: Value* offs_val = this->builder.CreateAdd( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(32U, fld_imm_val)); - Value* MEM_offs_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); + Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(8))); + this->builder.CreateZExtOrTrunc(MEMtmp0_val,this->get_type(8))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 15); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -1198,11 +1193,11 @@ private: Value* offs_val = this->builder.CreateAdd( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(32U, fld_imm_val)); - Value* MEM_offs_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); + Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(16))); + this->builder.CreateZExtOrTrunc(MEMtmp0_val,this->get_type(16))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 16); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -1237,11 +1232,11 @@ private: Value* offs_val = this->builder.CreateAdd( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(32U, fld_imm_val)); - Value* MEM_offs_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); + Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); + this->builder.CreateZExtOrTrunc(MEMtmp0_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 17); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -1274,10 +1269,10 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateAdd( + Value* Xtmp0_val = this->builder.CreateAdd( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(32U, fld_imm_val)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 18); @@ -1311,7 +1306,7 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->gen_choose( + Value* Xtmp0_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_SLT, this->gen_ext( @@ -1321,7 +1316,7 @@ private: this->gen_const(32U, 1), this->gen_const(32U, 0), 32); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 19); @@ -1356,7 +1351,7 @@ private: int32_t full_imm_val = fld_imm_val; if(fld_rd_val != 0){ - Value* X_rd_val = this->gen_choose( + Value* Xtmp0_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_ULT, this->gen_reg_load(fld_rs1_val + traits::X0, 0), @@ -1364,7 +1359,7 @@ private: this->gen_const(32U, 1), this->gen_const(32U, 0), 32); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 20); @@ -1398,10 +1393,10 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateXor( + Value* Xtmp0_val = this->builder.CreateXor( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(32U, fld_imm_val)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 21); @@ -1435,10 +1430,10 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateOr( + Value* Xtmp0_val = this->builder.CreateOr( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(32U, fld_imm_val)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 22); @@ -1472,10 +1467,10 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateAnd( + Value* Xtmp0_val = this->builder.CreateAnd( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(32U, fld_imm_val)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 23); @@ -1512,10 +1507,10 @@ private: this->gen_raise_trap(0, 0); } else { if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateShl( + Value* Xtmp0_val = this->builder.CreateShl( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(32U, fld_shamt_val)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } } this->gen_set_pc(pc, traits::NEXT_PC); @@ -1553,10 +1548,10 @@ private: this->gen_raise_trap(0, 0); } else { if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateLShr( + Value* Xtmp0_val = this->builder.CreateLShr( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(32U, fld_shamt_val)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } } this->gen_set_pc(pc, traits::NEXT_PC); @@ -1594,10 +1589,10 @@ private: this->gen_raise_trap(0, 0); } else { if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateAShr( + Value* Xtmp0_val = this->builder.CreateAShr( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(32U, fld_shamt_val)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } } this->gen_set_pc(pc, traits::NEXT_PC); @@ -1632,10 +1627,10 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateAdd( + Value* Xtmp0_val = this->builder.CreateAdd( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_reg_load(fld_rs2_val + traits::X0, 0)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 27); @@ -1669,10 +1664,10 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateSub( + Value* Xtmp0_val = this->builder.CreateSub( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_reg_load(fld_rs2_val + traits::X0, 0)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 28); @@ -1706,12 +1701,12 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateShl( + Value* Xtmp0_val = this->builder.CreateShl( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->builder.CreateAnd( this->gen_reg_load(fld_rs2_val + traits::X0, 0), - this->gen_const(32U, 31))); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_const(32U, 0x1f))); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 29); @@ -1745,7 +1740,7 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->gen_choose( + Value* Xtmp0_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_SLT, this->gen_ext( @@ -1757,7 +1752,7 @@ private: this->gen_const(32U, 1), this->gen_const(32U, 0), 32); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 30); @@ -1791,7 +1786,7 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->gen_choose( + Value* Xtmp0_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_ULT, this->gen_ext( @@ -1805,7 +1800,7 @@ private: this->gen_const(32U, 1), this->gen_const(32U, 0), 32); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 31); @@ -1839,10 +1834,10 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateXor( + Value* Xtmp0_val = this->builder.CreateXor( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_reg_load(fld_rs2_val + traits::X0, 0)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 32); @@ -1876,12 +1871,12 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateLShr( + Value* Xtmp0_val = this->builder.CreateLShr( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->builder.CreateAnd( this->gen_reg_load(fld_rs2_val + traits::X0, 0), - this->gen_const(32U, 31))); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_const(32U, 0x1f))); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 33); @@ -1915,12 +1910,12 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateAShr( + Value* Xtmp0_val = this->builder.CreateAShr( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->builder.CreateAnd( this->gen_reg_load(fld_rs2_val + traits::X0, 0), - this->gen_const(32U, 31))); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_const(32U, 0x1f))); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 34); @@ -1954,10 +1949,10 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateOr( + Value* Xtmp0_val = this->builder.CreateOr( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_reg_load(fld_rs2_val + traits::X0, 0)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 35); @@ -1991,10 +1986,10 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateAnd( + Value* Xtmp0_val = this->builder.CreateAnd( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_reg_load(fld_rs2_val + traits::X0, 0)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 36); @@ -2026,15 +2021,15 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* FENCE_fence_val = this->builder.CreateOr( + Value* FENCEtmp0_val = this->builder.CreateOr( this->builder.CreateShl( this->gen_const(32U, fld_pred_val), this->gen_const(32U, 4)), this->gen_const(32U, fld_succ_val)); this->gen_write_mem( traits::FENCE, - (uint64_t)0, - this->builder.CreateZExtOrTrunc(FENCE_fence_val,this->get_type(32))); + this->gen_const(64U, 0), + this->builder.CreateZExtOrTrunc(FENCEtmp0_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 37); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -2064,11 +2059,11 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* FENCE_fencei_val = this->gen_const(32U, fld_imm_val); + Value* FENCEtmp0_val = this->gen_const(32U, fld_imm_val); this->gen_write_mem( traits::FENCE, - (uint64_t)1, - this->builder.CreateZExtOrTrunc(FENCE_fencei_val,this->get_type(32))); + this->gen_const(64U, 1), + this->builder.CreateZExtOrTrunc(FENCEtmp0_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 38); this->gen_trap_check(this->leave_blk); @@ -2254,16 +2249,16 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* FENCE_fencevmal_val = this->gen_const(32U, fld_rs1_val); + Value* FENCEtmp0_val = this->gen_const(32U, fld_rs1_val); this->gen_write_mem( traits::FENCE, - (uint64_t)2, - this->builder.CreateZExtOrTrunc(FENCE_fencevmal_val,this->get_type(32))); - Value* FENCE_fencevmau_val = this->gen_const(32U, fld_rs2_val); + this->gen_const(64U, 2), + this->builder.CreateZExtOrTrunc(FENCEtmp0_val,this->get_type(32))); + Value* FENCEtmp1_val = this->gen_const(32U, fld_rs2_val); this->gen_write_mem( traits::FENCE, - (uint64_t)3, - this->builder.CreateZExtOrTrunc(FENCE_fencevmau_val,this->get_type(32))); + this->gen_const(64U, 3), + this->builder.CreateZExtOrTrunc(FENCEtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 45); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -2297,20 +2292,20 @@ private: Value* rs_val_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); if(fld_rd_val != 0){ - Value* csr_val_val = this->gen_read_mem(traits::CSR, fld_csr_val, 32/8); - Value* CSR_csr_val = rs_val_val; + Value* csr_val_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, fld_csr_val), 32/8); + Value* CSRtmp0_val = rs_val_val; this->gen_write_mem( traits::CSR, - fld_csr_val, - this->builder.CreateZExtOrTrunc(CSR_csr_val,this->get_type(32))); - Value* X_rd_val = csr_val_val; - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_const(16U, fld_csr_val), + this->builder.CreateZExtOrTrunc(CSRtmp0_val,this->get_type(32))); + Value* Xtmp1_val = csr_val_val; + this->builder.CreateStore(Xtmp1_val, get_reg_ptr(fld_rd_val + traits::X0), false); } else { - Value* CSR_csr_val = rs_val_val; + Value* CSRtmp2_val = rs_val_val; this->gen_write_mem( traits::CSR, - fld_csr_val, - this->builder.CreateZExtOrTrunc(CSR_csr_val,this->get_type(32))); + this->gen_const(16U, fld_csr_val), + this->builder.CreateZExtOrTrunc(CSRtmp2_val,this->get_type(32))); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 46); @@ -2343,20 +2338,20 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* xrd_val = this->gen_read_mem(traits::CSR, fld_csr_val, 32/8); + Value* xrd_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, fld_csr_val), 32/8); Value* xrs1_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); if(fld_rd_val != 0){ - Value* X_rd_val = xrd_val; - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = xrd_val; + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } if(fld_rs1_val != 0){ - Value* CSR_csr_val = this->builder.CreateOr( + Value* CSRtmp1_val = this->builder.CreateOr( xrd_val, xrs1_val); this->gen_write_mem( traits::CSR, - fld_csr_val, - this->builder.CreateZExtOrTrunc(CSR_csr_val,this->get_type(32))); + this->gen_const(16U, fld_csr_val), + this->builder.CreateZExtOrTrunc(CSRtmp1_val,this->get_type(32))); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 47); @@ -2389,20 +2384,20 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* xrd_val = this->gen_read_mem(traits::CSR, fld_csr_val, 32/8); + Value* xrd_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, fld_csr_val), 32/8); Value* xrs1_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); if(fld_rd_val != 0){ - Value* X_rd_val = xrd_val; - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = xrd_val; + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } if(fld_rs1_val != 0){ - Value* CSR_csr_val = this->builder.CreateAnd( + Value* CSRtmp1_val = this->builder.CreateAnd( xrd_val, this->builder.CreateNot(xrs1_val)); this->gen_write_mem( traits::CSR, - fld_csr_val, - this->builder.CreateZExtOrTrunc(CSR_csr_val,this->get_type(32))); + this->gen_const(16U, fld_csr_val), + this->builder.CreateZExtOrTrunc(CSRtmp1_val,this->get_type(32))); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 48); @@ -2436,17 +2431,17 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->gen_read_mem(traits::CSR, fld_csr_val, 32/8); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, fld_csr_val), 32/8); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } - Value* CSR_csr_val = this->gen_ext( + Value* CSRtmp1_val = this->gen_ext( this->gen_const(32U, fld_zimm_val), 32, false); this->gen_write_mem( traits::CSR, - fld_csr_val, - this->builder.CreateZExtOrTrunc(CSR_csr_val,this->get_type(32))); + this->gen_const(16U, fld_csr_val), + this->builder.CreateZExtOrTrunc(CSRtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 49); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -2478,9 +2473,9 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* res_val = this->gen_read_mem(traits::CSR, fld_csr_val, 32/8); + Value* res_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, fld_csr_val), 32/8); if(fld_zimm_val != 0){ - Value* CSR_csr_val = this->builder.CreateOr( + Value* CSRtmp0_val = this->builder.CreateOr( res_val, this->gen_ext( this->gen_const(32U, fld_zimm_val), @@ -2488,12 +2483,12 @@ private: false)); this->gen_write_mem( traits::CSR, - fld_csr_val, - this->builder.CreateZExtOrTrunc(CSR_csr_val,this->get_type(32))); + this->gen_const(16U, fld_csr_val), + this->builder.CreateZExtOrTrunc(CSRtmp0_val,this->get_type(32))); } if(fld_rd_val != 0){ - Value* X_rd_val = res_val; - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp1_val = res_val; + this->builder.CreateStore(Xtmp1_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 50); @@ -2526,13 +2521,13 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* res_val = this->gen_read_mem(traits::CSR, fld_csr_val, 32/8); + Value* res_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, fld_csr_val), 32/8); if(fld_rd_val != 0){ - Value* X_rd_val = res_val; - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = res_val; + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } if(fld_zimm_val != 0){ - Value* CSR_csr_val = this->builder.CreateAnd( + Value* CSRtmp1_val = this->builder.CreateAnd( res_val, this->builder.CreateNot(this->gen_ext( this->gen_const(32U, fld_zimm_val), @@ -2540,8 +2535,8 @@ private: false))); this->gen_write_mem( traits::CSR, - fld_csr_val, - this->builder.CreateZExtOrTrunc(CSR_csr_val,this->get_type(32))); + this->gen_const(16U, fld_csr_val), + this->builder.CreateZExtOrTrunc(CSRtmp1_val,this->get_type(32))); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 51); @@ -2584,11 +2579,11 @@ private: this->gen_reg_load(fld_rs2_val + traits::X0, 0), 128, false)); - Value* X_rd_val = this->gen_ext( + Value* Xtmp0_val = this->gen_ext( res_val, 32, false); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 52); @@ -2631,13 +2626,13 @@ private: this->gen_reg_load(fld_rs2_val + traits::X0, 0), 128, true)); - Value* X_rd_val = this->gen_ext( + Value* Xtmp0_val = this->gen_ext( this->builder.CreateLShr( res_val, this->gen_const(32U, 32)), 32, false); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 53); @@ -2680,13 +2675,13 @@ private: this->gen_reg_load(fld_rs2_val + traits::X0, 0), 128, false)); - Value* X_rd_val = this->gen_ext( + Value* Xtmp0_val = this->gen_ext( this->builder.CreateLShr( res_val, this->gen_const(32U, 32)), 32, false); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 54); @@ -2729,13 +2724,13 @@ private: this->gen_reg_load(fld_rs2_val + traits::X0, 0), 128, false)); - Value* X_rd_val = this->gen_ext( + Value* Xtmp0_val = this->gen_ext( this->builder.CreateLShr( res_val, this->gen_const(32U, 32)), 32, false); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 55); @@ -2769,95 +2764,101 @@ private: pc=pc+4; if(fld_rd_val != 0){ - llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); - llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); - llvm::BasicBlock* bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); - // this->builder.SetInsertPoint(bb); - this->gen_cond_branch(this->builder.CreateICmp( - ICmpInst::ICMP_NE, - this->gen_reg_load(fld_rs2_val + traits::X0, 0), - this->gen_const(32U, 0)), - bb_then, - bb_else); - this->builder.SetInsertPoint(bb_then); { - uint32_t M1_val = (-1); - uint32_t MMIN_val = (-1) << (32 - 1); llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); llvm::BasicBlock* bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); // this->builder.SetInsertPoint(bb); this->gen_cond_branch(this->builder.CreateICmp( - ICmpInst::ICMP_EQ, - this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 1), - 32, true), - this->gen_ext( - this->gen_const(32U, MMIN_val), - 32, true)), + ICmpInst::ICMP_NE, + this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_const(32U, 0)), bb_then, bb_else); this->builder.SetInsertPoint(bb_then); { - llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); - llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); - llvm::BasicBlock* bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); - // this->builder.SetInsertPoint(bb); - this->gen_cond_branch(this->builder.CreateICmp( - ICmpInst::ICMP_EQ, - this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 2), - 32, true), - this->gen_ext( - this->gen_const(32U, M1_val), - 32, true)), - bb_then, - bb_else); - this->builder.SetInsertPoint(bb_then); + int32_t M1_val = (-1); + uint32_t MMIN_val = (-1) << (32 - 1); { - Value* X_rd_val = this->gen_const(32U, MMIN_val); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); - } - this->builder.CreateBr(bbnext); - this->builder.SetInsertPoint(bb_else); - { - Value* X_rd_val = this->builder.CreateSDiv( + llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); + llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); + llvm::BasicBlock* bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); + // this->builder.SetInsertPoint(bb); + this->gen_cond_branch(this->builder.CreateICmp( + ICmpInst::ICMP_EQ, this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 3), + this->gen_reg_load(fld_rs1_val + traits::X0, 1), 32, true), this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 3), - 32, true)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_const(32U, MMIN_val), + 32, true)), + bb_then, + bb_else); + this->builder.SetInsertPoint(bb_then); + { + { + llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); + llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); + llvm::BasicBlock* bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); + // this->builder.SetInsertPoint(bb); + this->gen_cond_branch(this->builder.CreateICmp( + ICmpInst::ICMP_EQ, + this->gen_ext( + this->gen_reg_load(fld_rs2_val + traits::X0, 2), + 32, true), + this->gen_ext( + this->gen_const(32U, M1_val), + 32, true)), + bb_then, + bb_else); + this->builder.SetInsertPoint(bb_then); + { + Value* Xtmp0_val = this->gen_const(32U, MMIN_val); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + } + this->builder.CreateBr(bbnext); + this->builder.SetInsertPoint(bb_else); + { + Value* Xtmp1_val = this->builder.CreateSDiv( + this->gen_ext( + this->gen_reg_load(fld_rs1_val + traits::X0, 3), + 32, true), + this->gen_ext( + this->gen_reg_load(fld_rs2_val + traits::X0, 3), + 32, true)); + this->builder.CreateStore(Xtmp1_val, get_reg_ptr(fld_rd_val + traits::X0), false); + } + this->builder.CreateBr(bbnext); + bb=bbnext; + } + this->builder.SetInsertPoint(bb); + } + this->builder.CreateBr(bbnext); + this->builder.SetInsertPoint(bb_else); + { + Value* Xtmp2_val = this->builder.CreateSDiv( + this->gen_ext( + this->gen_reg_load(fld_rs1_val + traits::X0, 2), + 32, true), + this->gen_ext( + this->gen_reg_load(fld_rs2_val + traits::X0, 2), + 32, true)); + this->builder.CreateStore(Xtmp2_val, get_reg_ptr(fld_rd_val + traits::X0), false); + } + this->builder.CreateBr(bbnext); + bb=bbnext; } - this->builder.CreateBr(bbnext); - bb=bbnext; this->builder.SetInsertPoint(bb); } this->builder.CreateBr(bbnext); this->builder.SetInsertPoint(bb_else); { - Value* X_rd_val = this->builder.CreateSDiv( - this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 2), - 32, true), - this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 2), - 32, true)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp3_val = this->builder.CreateNeg(this->gen_const(32U, 1)); + this->builder.CreateStore(Xtmp3_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->builder.CreateBr(bbnext); bb=bbnext; - this->builder.SetInsertPoint(bb); } - this->builder.CreateBr(bbnext); - this->builder.SetInsertPoint(bb_else); - { - Value* X_rd_val = this->builder.CreateNeg(this->gen_const(32U, 1)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); - } - this->builder.CreateBr(bbnext); - bb=bbnext; this->builder.SetInsertPoint(bb); } this->gen_set_pc(pc, traits::NEXT_PC); @@ -2892,37 +2893,39 @@ private: pc=pc+4; if(fld_rd_val != 0){ - llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); - llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); - llvm::BasicBlock* bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); - // this->builder.SetInsertPoint(bb); - this->gen_cond_branch(this->builder.CreateICmp( - ICmpInst::ICMP_NE, - this->gen_reg_load(fld_rs2_val + traits::X0, 0), - this->gen_const(32U, 0)), - bb_then, - bb_else); - this->builder.SetInsertPoint(bb_then); { - Value* X_rd_val = this->builder.CreateUDiv( - this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 1), - 32, - false), - this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 1), - 32, - false)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); + llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); + llvm::BasicBlock* bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); + // this->builder.SetInsertPoint(bb); + this->gen_cond_branch(this->builder.CreateICmp( + ICmpInst::ICMP_NE, + this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_const(32U, 0)), + bb_then, + bb_else); + this->builder.SetInsertPoint(bb_then); + { + Value* Xtmp0_val = this->builder.CreateUDiv( + this->gen_ext( + this->gen_reg_load(fld_rs1_val + traits::X0, 1), + 32, + false), + this->gen_ext( + this->gen_reg_load(fld_rs2_val + traits::X0, 1), + 32, + false)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + } + this->builder.CreateBr(bbnext); + this->builder.SetInsertPoint(bb_else); + { + Value* Xtmp1_val = this->builder.CreateNeg(this->gen_const(32U, 1)); + this->builder.CreateStore(Xtmp1_val, get_reg_ptr(fld_rd_val + traits::X0), false); + } + this->builder.CreateBr(bbnext); + bb=bbnext; } - this->builder.CreateBr(bbnext); - this->builder.SetInsertPoint(bb_else); - { - Value* X_rd_val = this->builder.CreateNeg(this->gen_const(32U, 1)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); - } - this->builder.CreateBr(bbnext); - bb=bbnext; this->builder.SetInsertPoint(bb); } this->gen_set_pc(pc, traits::NEXT_PC); @@ -2957,99 +2960,105 @@ private: pc=pc+4; if(fld_rd_val != 0){ - llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); - llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); - llvm::BasicBlock* bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); - // this->builder.SetInsertPoint(bb); - this->gen_cond_branch(this->builder.CreateICmp( - ICmpInst::ICMP_NE, - this->gen_reg_load(fld_rs2_val + traits::X0, 0), - this->gen_const(32U, 0)), - bb_then, - bb_else); - this->builder.SetInsertPoint(bb_then); { - uint32_t M1_val = (-1); - uint32_t MMIN_val = (-1) << (32 - 1); llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); llvm::BasicBlock* bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); // this->builder.SetInsertPoint(bb); this->gen_cond_branch(this->builder.CreateICmp( - ICmpInst::ICMP_EQ, - this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 1), - 32, true), - this->gen_ext( - this->gen_const(32U, MMIN_val), - 32, true)), + ICmpInst::ICMP_NE, + this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_const(32U, 0)), bb_then, bb_else); this->builder.SetInsertPoint(bb_then); { - llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); - llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); - llvm::BasicBlock* bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); - // this->builder.SetInsertPoint(bb); - this->gen_cond_branch(this->builder.CreateICmp( - ICmpInst::ICMP_EQ, - this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 2), - 32, true), - this->gen_ext( - this->gen_const(32U, M1_val), - 32, true)), - bb_then, - bb_else); - this->builder.SetInsertPoint(bb_then); + int32_t M1_val = (-1); + uint32_t MMIN_val = (-1) << (32 - 1); { - Value* X_rd_val = this->gen_const(32U, 0); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); - } - this->builder.CreateBr(bbnext); - this->builder.SetInsertPoint(bb_else); - { - Value* X_rd_val = this->builder.CreateSRem( + llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); + llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); + llvm::BasicBlock* bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); + // this->builder.SetInsertPoint(bb); + this->gen_cond_branch(this->builder.CreateICmp( + ICmpInst::ICMP_EQ, this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 3), - 32, - true), + this->gen_reg_load(fld_rs1_val + traits::X0, 1), + 32, true), this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 3), - 32, - true)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_const(32U, MMIN_val), + 32, true)), + bb_then, + bb_else); + this->builder.SetInsertPoint(bb_then); + { + { + llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); + llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); + llvm::BasicBlock* bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); + // this->builder.SetInsertPoint(bb); + this->gen_cond_branch(this->builder.CreateICmp( + ICmpInst::ICMP_EQ, + this->gen_ext( + this->gen_reg_load(fld_rs2_val + traits::X0, 2), + 32, true), + this->gen_ext( + this->gen_const(32U, M1_val), + 32, true)), + bb_then, + bb_else); + this->builder.SetInsertPoint(bb_then); + { + Value* Xtmp0_val = this->gen_const(32U, 0); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + } + this->builder.CreateBr(bbnext); + this->builder.SetInsertPoint(bb_else); + { + Value* Xtmp1_val = this->builder.CreateSRem( + this->gen_ext( + this->gen_reg_load(fld_rs1_val + traits::X0, 3), + 32, + true), + this->gen_ext( + this->gen_reg_load(fld_rs2_val + traits::X0, 3), + 32, + true)); + this->builder.CreateStore(Xtmp1_val, get_reg_ptr(fld_rd_val + traits::X0), false); + } + this->builder.CreateBr(bbnext); + bb=bbnext; + } + this->builder.SetInsertPoint(bb); + } + this->builder.CreateBr(bbnext); + this->builder.SetInsertPoint(bb_else); + { + Value* Xtmp2_val = this->builder.CreateSRem( + this->gen_ext( + this->gen_reg_load(fld_rs1_val + traits::X0, 2), + 32, + true), + this->gen_ext( + this->gen_reg_load(fld_rs2_val + traits::X0, 2), + 32, + true)); + this->builder.CreateStore(Xtmp2_val, get_reg_ptr(fld_rd_val + traits::X0), false); + } + this->builder.CreateBr(bbnext); + bb=bbnext; } - this->builder.CreateBr(bbnext); - bb=bbnext; this->builder.SetInsertPoint(bb); } this->builder.CreateBr(bbnext); this->builder.SetInsertPoint(bb_else); { - Value* X_rd_val = this->builder.CreateSRem( - this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 2), - 32, - true), - this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 2), - 32, - true)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp3_val = this->gen_reg_load(fld_rs1_val + traits::X0, 1); + this->builder.CreateStore(Xtmp3_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->builder.CreateBr(bbnext); bb=bbnext; - this->builder.SetInsertPoint(bb); } - this->builder.CreateBr(bbnext); - this->builder.SetInsertPoint(bb_else); - { - Value* X_rd_val = this->gen_reg_load(fld_rs1_val + traits::X0, 1); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); - } - this->builder.CreateBr(bbnext); - bb=bbnext; this->builder.SetInsertPoint(bb); } this->gen_set_pc(pc, traits::NEXT_PC); @@ -3084,37 +3093,39 @@ private: pc=pc+4; if(fld_rd_val != 0){ - llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); - llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); - llvm::BasicBlock* bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); - // this->builder.SetInsertPoint(bb); - this->gen_cond_branch(this->builder.CreateICmp( - ICmpInst::ICMP_NE, - this->gen_reg_load(fld_rs2_val + traits::X0, 0), - this->gen_const(32U, 0)), - bb_then, - bb_else); - this->builder.SetInsertPoint(bb_then); { - Value* X_rd_val = this->builder.CreateURem( - this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 1), - 32, - false), - this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 1), - 32, - false)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); + llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); + llvm::BasicBlock* bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); + // this->builder.SetInsertPoint(bb); + this->gen_cond_branch(this->builder.CreateICmp( + ICmpInst::ICMP_NE, + this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_const(32U, 0)), + bb_then, + bb_else); + this->builder.SetInsertPoint(bb_then); + { + Value* Xtmp0_val = this->builder.CreateURem( + this->gen_ext( + this->gen_reg_load(fld_rs1_val + traits::X0, 1), + 32, + false), + this->gen_ext( + this->gen_reg_load(fld_rs2_val + traits::X0, 1), + 32, + false)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + } + this->builder.CreateBr(bbnext); + this->builder.SetInsertPoint(bb_else); + { + Value* Xtmp1_val = this->gen_reg_load(fld_rs1_val + traits::X0, 1); + this->builder.CreateStore(Xtmp1_val, get_reg_ptr(fld_rd_val + traits::X0), false); + } + this->builder.CreateBr(bbnext); + bb=bbnext; } - this->builder.CreateBr(bbnext); - this->builder.SetInsertPoint(bb_else); - { - Value* X_rd_val = this->gen_reg_load(fld_rs1_val + traits::X0, 1); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); - } - this->builder.CreateBr(bbnext); - bb=bbnext; this->builder.SetInsertPoint(bb); } this->gen_set_pc(pc, traits::NEXT_PC); @@ -3151,19 +3162,19 @@ private: if(fld_rd_val != 0){ Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); - Value* X_rd_val = this->gen_ext( + Value* Xtmp0_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 32/8), 32, true); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); - Value* RES_offs_val = this->gen_ext( + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* REStmp1_val = this->gen_ext( this->builder.CreateNeg(this->gen_const(8U, 1)), 32, true); this->gen_write_mem( traits::RES, offs_val, - this->builder.CreateZExtOrTrunc(RES_offs_val,this->get_type(32))); + this->builder.CreateZExtOrTrunc(REStmp1_val,this->get_type(32))); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 60); @@ -3200,28 +3211,30 @@ private: Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); Value* res1_val = this->gen_read_mem(traits::RES, offs_val, 32/8); - llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); - llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); - // this->builder.SetInsertPoint(bb); - this->gen_cond_branch(this->builder.CreateICmp( - ICmpInst::ICMP_NE, - res1_val, - this->gen_const(32U, 0)), - bb_then, - bbnext); - this->builder.SetInsertPoint(bb_then); { - Value* MEM_offs_val = this->gen_reg_load(fld_rs2_val + traits::X0, 1); - this->gen_write_mem( - traits::MEM, - offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); + llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); + llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); + // this->builder.SetInsertPoint(bb); + this->gen_cond_branch(this->builder.CreateICmp( + ICmpInst::ICMP_NE, + res1_val, + this->gen_const(32U, 0)), + bb_then, + bbnext); + this->builder.SetInsertPoint(bb_then); + { + Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits::X0, 1); + this->gen_write_mem( + traits::MEM, + offs_val, + this->builder.CreateZExtOrTrunc(MEMtmp0_val,this->get_type(32))); + } + this->builder.CreateBr(bbnext); + bb=bbnext; } - this->builder.CreateBr(bbnext); - bb=bbnext; this->builder.SetInsertPoint(bb); if(fld_rd_val != 0){ - Value* X_rd_val = this->gen_choose( + Value* Xtmp1_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_NE, res1_val, @@ -3229,7 +3242,7 @@ private: this->gen_const(32U, 0), this->gen_const(32U, 1), 32); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp1_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 61); @@ -3266,17 +3279,17 @@ private: Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); if(fld_rd_val != 0){ - Value* X_rd_val = this->gen_ext( + Value* Xtmp0_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 32/8), 32, true); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } - Value* MEM_offs_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); + Value* MEMtmp1_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); + this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 62); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -3316,17 +3329,17 @@ private: 32, true); if(fld_rd_val != 0){ - Value* X_rd_val = res1_val; - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = res1_val; + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } Value* res2_val = this->builder.CreateAdd( res1_val, this->gen_reg_load(fld_rs2_val + traits::X0, 0)); - Value* MEM_offs_val = res2_val; + Value* MEMtmp1_val = res2_val; this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); + this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 63); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -3366,17 +3379,17 @@ private: 32, true); if(fld_rd_val != 0){ - Value* X_rd_val = res1_val; - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = res1_val; + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } Value* res2_val = this->builder.CreateXor( res1_val, this->gen_reg_load(fld_rs2_val + traits::X0, 0)); - Value* MEM_offs_val = res2_val; + Value* MEMtmp1_val = res2_val; this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); + this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 64); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -3416,17 +3429,17 @@ private: 32, true); if(fld_rd_val != 0){ - Value* X_rd_val = res1_val; - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = res1_val; + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } Value* res2_val = this->builder.CreateAnd( res1_val, this->gen_reg_load(fld_rs2_val + traits::X0, 0)); - Value* MEM_offs_val = res2_val; + Value* MEMtmp1_val = res2_val; this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); + this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 65); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -3466,17 +3479,17 @@ private: 32, true); if(fld_rd_val != 0){ - Value* X_rd_val = res1_val; - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = res1_val; + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } Value* res2_val = this->builder.CreateOr( res1_val, this->gen_reg_load(fld_rs2_val + traits::X0, 0)); - Value* MEM_offs_val = res2_val; + Value* MEMtmp1_val = res2_val; this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); + this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 66); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -3516,8 +3529,8 @@ private: 32, true); if(fld_rd_val != 0){ - Value* X_rd_val = res1_val; - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = res1_val; + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } Value* res2_val = this->gen_choose( this->builder.CreateICmp( @@ -3531,11 +3544,11 @@ private: this->gen_reg_load(fld_rs2_val + traits::X0, 0), res1_val, 32); - Value* MEM_offs_val = res2_val; + Value* MEMtmp1_val = res2_val; this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); + this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 67); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -3575,8 +3588,8 @@ private: 32, true); if(fld_rd_val != 0){ - Value* X_rd_val = res1_val; - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = res1_val; + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } Value* res2_val = this->gen_choose( this->builder.CreateICmp( @@ -3590,11 +3603,11 @@ private: this->gen_reg_load(fld_rs2_val + traits::X0, 0), res1_val, 32); - Value* MEM_offs_val = res2_val; + Value* MEMtmp1_val = res2_val; this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); + this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 68); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -3634,8 +3647,8 @@ private: 32, false); if(fld_rd_val != 0){ - Value* X_rd_val = res1_val; - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = res1_val; + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } Value* res2_val = this->gen_choose( this->builder.CreateICmp( @@ -3645,11 +3658,11 @@ private: this->gen_reg_load(fld_rs2_val + traits::X0, 0), res1_val, 32); - Value* MEM_offs_val = res2_val; + Value* MEMtmp1_val = res2_val; this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); + this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 69); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -3689,8 +3702,8 @@ private: 32, false); if(fld_rd_val != 0){ - Value* X_rd_val = res1_val; - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = res1_val; + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } Value* res2_val = this->gen_choose( this->builder.CreateICmp( @@ -3700,11 +3713,11 @@ private: this->gen_reg_load(fld_rs2_val + traits::X0, 0), res1_val, 32); - Value* MEM_offs_val = res2_val; + Value* MEMtmp1_val = res2_val; this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); + this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 70); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -3738,12 +3751,10 @@ private: if(fld_imm_val == 0){ this->gen_raise_trap(0, 2); } - uint8_t rd_idx_val = (fld_rd_val + 8); - uint8_t x2_idx_val = 2; - Value* X_rd_idx_val = this->builder.CreateAdd( - this->gen_reg_load(x2_idx_val + traits::X0, 0), + Value* Xtmp0_val = this->builder.CreateAdd( + this->gen_reg_load(2 + traits::X0, 0), this->gen_const(32U, fld_imm_val)); - this->builder.CreateStore(X_rd_idx_val, get_reg_ptr(rd_idx_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr((fld_rd_val + 8) + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 71); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -3775,13 +3786,11 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - uint8_t rs1_idx_val = (fld_rs1_val + 8); - uint8_t rd_idx_val = (fld_rd_val + 8); Value* offs_val = this->builder.CreateAdd( - this->gen_reg_load(rs1_idx_val + traits::X0, 0), + this->gen_reg_load((fld_rs1_val + 8) + traits::X0, 0), this->gen_const(32U, fld_uimm_val)); - Value* X_rd_idx_val = this->gen_read_mem(traits::MEM, offs_val, 32/8); - this->builder.CreateStore(X_rd_idx_val, get_reg_ptr(rd_idx_val + traits::X0), false); + Value* Xtmp0_val = this->gen_read_mem(traits::MEM, offs_val, 32/8); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr((fld_rd_val + 8) + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 72); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -3813,16 +3822,14 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - uint8_t rs1_idx_val = (fld_rs1_val + 8); - uint8_t rs2_idx_val = (fld_rs2_val + 8); Value* offs_val = this->builder.CreateAdd( - this->gen_reg_load(rs1_idx_val + traits::X0, 0), + this->gen_reg_load((fld_rs1_val + 8) + traits::X0, 0), this->gen_const(32U, fld_uimm_val)); - Value* MEM_offs_val = this->gen_reg_load(rs2_idx_val + traits::X0, 0); + Value* MEMtmp0_val = this->gen_reg_load((fld_rs2_val + 8) + traits::X0, 0); this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); + this->builder.CreateZExtOrTrunc(MEMtmp0_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 73); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -3853,10 +3860,10 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - Value* X_rs1_val = this->builder.CreateAdd( + Value* Xtmp0_val = this->builder.CreateAdd( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(32U, fld_imm_val)); - this->builder.CreateStore(X_rs1_val, get_reg_ptr(fld_rs1_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rs1_val + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 74); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -3914,11 +3921,10 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - uint8_t rd_val = 1; - Value* X_rd_val = this->builder.CreateAdd( + Value* Xtmp0_val = this->builder.CreateAdd( cur_pc_val, this->gen_const(32U, 2)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(1 + traits::X0), false); Value* PC_val = this->builder.CreateAdd( cur_pc_val, this->gen_const(32U, fld_imm_val)); @@ -3954,8 +3960,8 @@ private: if(fld_rd_val == 0){ this->gen_raise_trap(0, 2); } - Value* X_rd_val = this->gen_const(32U, fld_imm_val); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = this->gen_const(32U, fld_imm_val); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 77); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -3992,8 +3998,8 @@ private: if(fld_imm_val == 0){ this->gen_raise_trap(0, 2); } - Value* X_rd_val = this->gen_const(32U, fld_imm_val); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = this->gen_const(32U, fld_imm_val); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 78); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -4023,13 +4029,12 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - uint8_t x2_idx_val = 2; - Value* X_x2_idx_val = this->builder.CreateAdd( + Value* Xtmp0_val = this->builder.CreateAdd( this->gen_ext( - this->gen_reg_load(x2_idx_val + traits::X0, 0), + this->gen_reg_load(2 + traits::X0, 0), 32, true), this->gen_const(32U, fld_imm_val)); - this->builder.CreateStore(X_x2_idx_val, get_reg_ptr(x2_idx_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(2 + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 79); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -4061,10 +4066,10 @@ private: pc=pc+2; uint8_t rs1_idx_val = (fld_rs1_val + 8); - Value* X_rs1_idx_val = this->builder.CreateLShr( + Value* Xtmp0_val = this->builder.CreateLShr( this->gen_reg_load(rs1_idx_val + traits::X0, 0), this->gen_const(32U, fld_shamt_val)); - this->builder.CreateStore(X_rs1_idx_val, get_reg_ptr(rs1_idx_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rs1_idx_val + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 80); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -4096,10 +4101,10 @@ private: pc=pc+2; uint8_t rs1_idx_val = (fld_rs1_val + 8); - Value* X_rs1_idx_val = this->builder.CreateAShr( + Value* Xtmp0_val = this->builder.CreateAShr( this->gen_reg_load(rs1_idx_val + traits::X0, 0), this->gen_const(32U, fld_shamt_val)); - this->builder.CreateStore(X_rs1_idx_val, get_reg_ptr(rs1_idx_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rs1_idx_val + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 81); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -4131,10 +4136,10 @@ private: pc=pc+2; uint8_t rs1_idx_val = (fld_rs1_val + 8); - Value* X_rs1_idx_val = this->builder.CreateAnd( + Value* Xtmp0_val = this->builder.CreateAnd( this->gen_reg_load(rs1_idx_val + traits::X0, 0), this->gen_const(32U, fld_imm_val)); - this->builder.CreateStore(X_rs1_idx_val, get_reg_ptr(rs1_idx_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rs1_idx_val + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 82); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -4166,11 +4171,10 @@ private: pc=pc+2; uint8_t rd_idx_val = (fld_rd_val + 8); - uint8_t rs2_idx_val = (fld_rs2_val + 8); - Value* X_rd_idx_val = this->builder.CreateSub( + Value* Xtmp0_val = this->builder.CreateSub( this->gen_reg_load(rd_idx_val + traits::X0, 0), - this->gen_reg_load(rs2_idx_val + traits::X0, 0)); - this->builder.CreateStore(X_rd_idx_val, get_reg_ptr(rd_idx_val + traits::X0), false); + this->gen_reg_load((fld_rs2_val + 8) + traits::X0, 0)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd_idx_val + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 83); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -4202,11 +4206,10 @@ private: pc=pc+2; uint8_t rd_idx_val = (fld_rd_val + 8); - uint8_t rs2_idx_val = (fld_rs2_val + 8); - Value* X_rd_idx_val = this->builder.CreateXor( + Value* Xtmp0_val = this->builder.CreateXor( this->gen_reg_load(rd_idx_val + traits::X0, 0), - this->gen_reg_load(rs2_idx_val + traits::X0, 0)); - this->builder.CreateStore(X_rd_idx_val, get_reg_ptr(rd_idx_val + traits::X0), false); + this->gen_reg_load((fld_rs2_val + 8) + traits::X0, 0)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd_idx_val + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 84); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -4238,11 +4241,10 @@ private: pc=pc+2; uint8_t rd_idx_val = (fld_rd_val + 8); - uint8_t rs2_idx_val = (fld_rs2_val + 8); - Value* X_rd_idx_val = this->builder.CreateOr( + Value* Xtmp0_val = this->builder.CreateOr( this->gen_reg_load(rd_idx_val + traits::X0, 0), - this->gen_reg_load(rs2_idx_val + traits::X0, 0)); - this->builder.CreateStore(X_rd_idx_val, get_reg_ptr(rd_idx_val + traits::X0), false); + this->gen_reg_load((fld_rs2_val + 8) + traits::X0, 0)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd_idx_val + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 85); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -4274,11 +4276,10 @@ private: pc=pc+2; uint8_t rd_idx_val = (fld_rd_val + 8); - uint8_t rs2_idx_val = (fld_rs2_val + 8); - Value* X_rd_idx_val = this->builder.CreateAnd( + Value* Xtmp0_val = this->builder.CreateAnd( this->gen_reg_load(rd_idx_val + traits::X0, 0), - this->gen_reg_load(rs2_idx_val + traits::X0, 0)); - this->builder.CreateStore(X_rd_idx_val, get_reg_ptr(rd_idx_val + traits::X0), false); + this->gen_reg_load((fld_rs2_val + 8) + traits::X0, 0)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd_idx_val + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 86); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -4340,11 +4341,10 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - uint8_t rs1_idx_val = (fld_rs1_val + 8); Value* PC_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_EQ, - this->gen_reg_load(rs1_idx_val + traits::X0, 0), + this->gen_reg_load((fld_rs1_val + 8) + traits::X0, 0), this->gen_const(32U, 0)), this->builder.CreateAdd( cur_pc_val, @@ -4382,11 +4382,10 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - uint8_t rs1_idx_val = (fld_rs1_val + 8); Value* PC_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_NE, - this->gen_reg_load(rs1_idx_val + traits::X0, 0), + this->gen_reg_load((fld_rs1_val + 8) + traits::X0, 0), this->gen_const(32U, 0)), this->builder.CreateAdd( cur_pc_val, @@ -4427,10 +4426,10 @@ private: if(fld_rs1_val == 0){ this->gen_raise_trap(0, 2); } - Value* X_rs1_val = this->builder.CreateShl( + Value* Xtmp0_val = this->builder.CreateShl( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(32U, fld_shamt_val)); - this->builder.CreateStore(X_rs1_val, get_reg_ptr(fld_rs1_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rs1_val + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 90); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -4461,12 +4460,11 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - uint8_t x2_idx_val = 2; Value* offs_val = this->builder.CreateAdd( - this->gen_reg_load(x2_idx_val + traits::X0, 0), + this->gen_reg_load(2 + traits::X0, 0), this->gen_const(32U, fld_uimm_val)); - Value* X_rd_val = this->gen_read_mem(traits::MEM, offs_val, 32/8); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = this->gen_read_mem(traits::MEM, offs_val, 32/8); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 91); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -4497,8 +4495,8 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - Value* X_rd_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 92); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -4558,10 +4556,10 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - Value* X_rd_val = this->builder.CreateAdd( + Value* Xtmp0_val = this->builder.CreateAdd( this->gen_reg_load(fld_rd_val + traits::X0, 0), this->gen_reg_load(fld_rs2_val + traits::X0, 0)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 94); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -4591,11 +4589,10 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - uint8_t r_idx_val = 1; - Value* X_r_idx_val = this->builder.CreateAdd( + Value* Xtmp0_val = this->builder.CreateAdd( cur_pc_val, this->gen_const(32U, 2)); - this->builder.CreateStore(X_r_idx_val, get_reg_ptr(r_idx_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(1 + traits::X0), false); Value* PC_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); this->builder.CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); this->gen_sync(iss::POST_SYNC, 95); @@ -4652,15 +4649,14 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - uint8_t x2_idx_val = 2; Value* offs_val = this->builder.CreateAdd( - this->gen_reg_load(x2_idx_val + traits::X0, 0), + this->gen_reg_load(2 + traits::X0, 0), this->gen_const(32U, fld_uimm_val)); - Value* MEM_offs_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); + Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); + this->builder.CreateZExtOrTrunc(MEMtmp0_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 97); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -4725,11 +4721,11 @@ private: this->gen_const(32U, fld_imm_val)); Value* res_val = this->gen_read_mem(traits::MEM, offs_val, 32/8); if(64 == 32){ - Value* F_rd_val = res_val; - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + Value* Ftmp0_val = res_val; + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); } else { - uint64_t upper_val = (-1); - Value* F_rd_val = this->builder.CreateOr( + int64_t upper_val = (-1); + Value* Ftmp1_val = this->builder.CreateOr( this->builder.CreateShl( this->gen_const(64U, upper_val), this->gen_const(64U, 32)), @@ -4737,7 +4733,7 @@ private: res_val, 64, false)); - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 99); @@ -4773,14 +4769,14 @@ private: Value* offs_val = this->builder.CreateAdd( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(32U, fld_imm_val)); - Value* MEM_offs_val = this->builder.CreateTrunc( + Value* MEMtmp0_val = this->builder.CreateTrunc( this->gen_reg_load(fld_rs2_val + traits::F0, 0), this-> get_type(32) ); this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); + this->builder.CreateZExtOrTrunc(MEMtmp0_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 100); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -4815,40 +4811,40 @@ private: pc=pc+4; Value* res_val = this->builder.CreateCall(this->mod->getFunction("fmadd_s"), std::vector{ - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), - this-> get_type(32) - ), - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), - this-> get_type(32) - ), - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs3_val + traits::F0, 0), - this-> get_type(32) - ), - this->gen_ext( - this->gen_const(64U, 0LL), - 32, - false), - this->gen_choose( - this->builder.CreateICmp( - ICmpInst::ICMP_ULT, - this->gen_const(3U, fld_rm_val), - this->gen_const(3U, 7)), - this->gen_const(8U, fld_rm_val), - this->builder.CreateTrunc( - this->gen_reg_load(traits::FCSR, 0), - this-> get_type(8) - ), - 8) + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this-> get_type(32) + ), + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this-> get_type(32) + ), + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs3_val + traits::F0, 0), + this-> get_type(32) + ), + this->gen_ext( + this->gen_const(64U, 0LL), + 32, + false), + this->gen_choose( + this->builder.CreateICmp( + ICmpInst::ICMP_ULT, + this->gen_const(8U, fld_rm_val), + this->gen_const(8U, 7)), + this->gen_const(8U, fld_rm_val), + this->builder.CreateTrunc( + this->gen_reg_load(traits::FCSR, 0), + this-> get_type(8) + ), + 8) }); if(64 == 32){ - Value* F_rd_val = res_val; - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + Value* Ftmp0_val = res_val; + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); } else { - uint64_t upper_val = (-1); - Value* F_rd_val = this->builder.CreateOr( + int64_t upper_val = (-1); + Value* Ftmp1_val = this->builder.CreateOr( this->builder.CreateShl( this->gen_const(64U, upper_val), this->gen_const(64U, 32)), @@ -4856,14 +4852,14 @@ private: res_val, 64, false)); - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); } Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); Value* FCSR_val = this->builder.CreateAdd( this->builder.CreateAnd( this->gen_reg_load(traits::FCSR, 0), - this->builder.CreateNot(this->gen_const(32U, 31))), + this->builder.CreateNot(this->gen_const(32U, 0x1f))), flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); @@ -4900,40 +4896,40 @@ private: pc=pc+4; Value* res_val = this->builder.CreateCall(this->mod->getFunction("fmadd_s"), std::vector{ - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), - this-> get_type(32) - ), - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), - this-> get_type(32) - ), - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs3_val + traits::F0, 0), - this-> get_type(32) - ), - this->gen_ext( - this->gen_const(64U, 1LL), - 32, - false), - this->gen_choose( - this->builder.CreateICmp( - ICmpInst::ICMP_ULT, - this->gen_const(3U, fld_rm_val), - this->gen_const(3U, 7)), - this->gen_const(8U, fld_rm_val), - this->builder.CreateTrunc( - this->gen_reg_load(traits::FCSR, 0), - this-> get_type(8) - ), - 8) + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this-> get_type(32) + ), + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this-> get_type(32) + ), + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs3_val + traits::F0, 0), + this-> get_type(32) + ), + this->gen_ext( + this->gen_const(64U, 1LL), + 32, + false), + this->gen_choose( + this->builder.CreateICmp( + ICmpInst::ICMP_ULT, + this->gen_const(8U, fld_rm_val), + this->gen_const(8U, 7)), + this->gen_const(8U, fld_rm_val), + this->builder.CreateTrunc( + this->gen_reg_load(traits::FCSR, 0), + this-> get_type(8) + ), + 8) }); if(64 == 32){ - Value* F_rd_val = res_val; - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + Value* Ftmp0_val = res_val; + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); } else { - uint64_t upper_val = (-1); - Value* F_rd_val = this->builder.CreateOr( + int64_t upper_val = (-1); + Value* Ftmp1_val = this->builder.CreateOr( this->builder.CreateShl( this->gen_const(64U, upper_val), this->gen_const(64U, 32)), @@ -4941,14 +4937,14 @@ private: res_val, 64, false)); - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); } Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); Value* FCSR_val = this->builder.CreateAdd( this->builder.CreateAnd( this->gen_reg_load(traits::FCSR, 0), - this->builder.CreateNot(this->gen_const(32U, 31))), + this->builder.CreateNot(this->gen_const(32U, 0x1f))), flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); @@ -4985,40 +4981,40 @@ private: pc=pc+4; Value* res_val = this->builder.CreateCall(this->mod->getFunction("fmadd_s"), std::vector{ - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), - this-> get_type(32) - ), - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), - this-> get_type(32) - ), - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs3_val + traits::F0, 0), - this-> get_type(32) - ), - this->gen_ext( - this->gen_const(64U, 2LL), - 32, - false), - this->gen_choose( - this->builder.CreateICmp( - ICmpInst::ICMP_ULT, - this->gen_const(3U, fld_rm_val), - this->gen_const(3U, 7)), - this->gen_const(8U, fld_rm_val), - this->builder.CreateTrunc( - this->gen_reg_load(traits::FCSR, 0), - this-> get_type(8) - ), - 8) + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this-> get_type(32) + ), + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this-> get_type(32) + ), + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs3_val + traits::F0, 0), + this-> get_type(32) + ), + this->gen_ext( + this->gen_const(64U, 2LL), + 32, + false), + this->gen_choose( + this->builder.CreateICmp( + ICmpInst::ICMP_ULT, + this->gen_const(8U, fld_rm_val), + this->gen_const(8U, 7)), + this->gen_const(8U, fld_rm_val), + this->builder.CreateTrunc( + this->gen_reg_load(traits::FCSR, 0), + this-> get_type(8) + ), + 8) }); if(64 == 32){ - Value* F_rd_val = res_val; - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + Value* Ftmp0_val = res_val; + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); } else { - uint64_t upper_val = (-1); - Value* F_rd_val = this->builder.CreateOr( + int64_t upper_val = (-1); + Value* Ftmp1_val = this->builder.CreateOr( this->builder.CreateShl( this->gen_const(64U, upper_val), this->gen_const(64U, 32)), @@ -5026,14 +5022,14 @@ private: res_val, 64, false)); - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); } Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); Value* FCSR_val = this->builder.CreateAdd( this->builder.CreateAnd( this->gen_reg_load(traits::FCSR, 0), - this->builder.CreateNot(this->gen_const(32U, 31))), + this->builder.CreateNot(this->gen_const(32U, 0x1f))), flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); @@ -5070,40 +5066,40 @@ private: pc=pc+4; Value* res_val = this->builder.CreateCall(this->mod->getFunction("fmadd_s"), std::vector{ - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), - this-> get_type(32) - ), - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), - this-> get_type(32) - ), - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs3_val + traits::F0, 0), - this-> get_type(32) - ), - this->gen_ext( - this->gen_const(64U, 3LL), - 32, - false), - this->gen_choose( - this->builder.CreateICmp( - ICmpInst::ICMP_ULT, - this->gen_const(3U, fld_rm_val), - this->gen_const(3U, 7)), - this->gen_const(8U, fld_rm_val), - this->builder.CreateTrunc( - this->gen_reg_load(traits::FCSR, 0), - this-> get_type(8) - ), - 8) + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this-> get_type(32) + ), + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this-> get_type(32) + ), + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs3_val + traits::F0, 0), + this-> get_type(32) + ), + this->gen_ext( + this->gen_const(64U, 3LL), + 32, + false), + this->gen_choose( + this->builder.CreateICmp( + ICmpInst::ICMP_ULT, + this->gen_const(8U, fld_rm_val), + this->gen_const(8U, 7)), + this->gen_const(8U, fld_rm_val), + this->builder.CreateTrunc( + this->gen_reg_load(traits::FCSR, 0), + this-> get_type(8) + ), + 8) }); if(64 == 32){ - Value* F_rd_val = res_val; - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + Value* Ftmp0_val = res_val; + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); } else { - uint64_t upper_val = (-1); - Value* F_rd_val = this->builder.CreateOr( + int64_t upper_val = (-1); + Value* Ftmp1_val = this->builder.CreateOr( this->builder.CreateShl( this->gen_const(64U, upper_val), this->gen_const(64U, 32)), @@ -5111,14 +5107,14 @@ private: res_val, 64, false)); - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); } Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); Value* FCSR_val = this->builder.CreateAdd( this->builder.CreateAnd( this->gen_reg_load(traits::FCSR, 0), - this->builder.CreateNot(this->gen_const(32U, 31))), + this->builder.CreateNot(this->gen_const(32U, 0x1f))), flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); @@ -5154,32 +5150,32 @@ private: pc=pc+4; Value* res_val = this->builder.CreateCall(this->mod->getFunction("fadd_s"), std::vector{ - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), - this-> get_type(32) - ), - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), - this-> get_type(32) - ), - this->gen_choose( - this->builder.CreateICmp( - ICmpInst::ICMP_ULT, - this->gen_const(3U, fld_rm_val), - this->gen_const(3U, 7)), - this->gen_const(8U, fld_rm_val), - this->builder.CreateTrunc( - this->gen_reg_load(traits::FCSR, 0), - this-> get_type(8) - ), - 8) + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this-> get_type(32) + ), + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this-> get_type(32) + ), + this->gen_choose( + this->builder.CreateICmp( + ICmpInst::ICMP_ULT, + this->gen_const(8U, fld_rm_val), + this->gen_const(8U, 7)), + this->gen_const(8U, fld_rm_val), + this->builder.CreateTrunc( + this->gen_reg_load(traits::FCSR, 0), + this-> get_type(8) + ), + 8) }); if(64 == 32){ - Value* F_rd_val = res_val; - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + Value* Ftmp0_val = res_val; + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); } else { - uint64_t upper_val = (-1); - Value* F_rd_val = this->builder.CreateOr( + int64_t upper_val = (-1); + Value* Ftmp1_val = this->builder.CreateOr( this->builder.CreateShl( this->gen_const(64U, upper_val), this->gen_const(64U, 32)), @@ -5187,14 +5183,14 @@ private: res_val, 64, false)); - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); } Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); Value* FCSR_val = this->builder.CreateAdd( this->builder.CreateAnd( this->gen_reg_load(traits::FCSR, 0), - this->builder.CreateNot(this->gen_const(32U, 31))), + this->builder.CreateNot(this->gen_const(32U, 0x1f))), flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); @@ -5230,32 +5226,32 @@ private: pc=pc+4; Value* res_val = this->builder.CreateCall(this->mod->getFunction("fsub_s"), std::vector{ - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), - this-> get_type(32) - ), - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), - this-> get_type(32) - ), - this->gen_choose( - this->builder.CreateICmp( - ICmpInst::ICMP_ULT, - this->gen_const(3U, fld_rm_val), - this->gen_const(3U, 7)), - this->gen_const(8U, fld_rm_val), - this->builder.CreateTrunc( - this->gen_reg_load(traits::FCSR, 0), - this-> get_type(8) - ), - 8) + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this-> get_type(32) + ), + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this-> get_type(32) + ), + this->gen_choose( + this->builder.CreateICmp( + ICmpInst::ICMP_ULT, + this->gen_const(8U, fld_rm_val), + this->gen_const(8U, 7)), + this->gen_const(8U, fld_rm_val), + this->builder.CreateTrunc( + this->gen_reg_load(traits::FCSR, 0), + this-> get_type(8) + ), + 8) }); if(64 == 32){ - Value* F_rd_val = res_val; - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + Value* Ftmp0_val = res_val; + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); } else { - uint64_t upper_val = (-1); - Value* F_rd_val = this->builder.CreateOr( + int64_t upper_val = (-1); + Value* Ftmp1_val = this->builder.CreateOr( this->builder.CreateShl( this->gen_const(64U, upper_val), this->gen_const(64U, 32)), @@ -5263,14 +5259,14 @@ private: res_val, 64, false)); - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); } Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); Value* FCSR_val = this->builder.CreateAdd( this->builder.CreateAnd( this->gen_reg_load(traits::FCSR, 0), - this->builder.CreateNot(this->gen_const(32U, 31))), + this->builder.CreateNot(this->gen_const(32U, 0x1f))), flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); @@ -5306,32 +5302,32 @@ private: pc=pc+4; Value* res_val = this->builder.CreateCall(this->mod->getFunction("fmul_s"), std::vector{ - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), - this-> get_type(32) - ), - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), - this-> get_type(32) - ), - this->gen_choose( - this->builder.CreateICmp( - ICmpInst::ICMP_ULT, - this->gen_const(3U, fld_rm_val), - this->gen_const(3U, 7)), - this->gen_const(8U, fld_rm_val), - this->builder.CreateTrunc( - this->gen_reg_load(traits::FCSR, 0), - this-> get_type(8) - ), - 8) + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this-> get_type(32) + ), + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this-> get_type(32) + ), + this->gen_choose( + this->builder.CreateICmp( + ICmpInst::ICMP_ULT, + this->gen_const(8U, fld_rm_val), + this->gen_const(8U, 7)), + this->gen_const(8U, fld_rm_val), + this->builder.CreateTrunc( + this->gen_reg_load(traits::FCSR, 0), + this-> get_type(8) + ), + 8) }); if(64 == 32){ - Value* F_rd_val = res_val; - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + Value* Ftmp0_val = res_val; + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); } else { - uint64_t upper_val = (-1); - Value* F_rd_val = this->builder.CreateOr( + int64_t upper_val = (-1); + Value* Ftmp1_val = this->builder.CreateOr( this->builder.CreateShl( this->gen_const(64U, upper_val), this->gen_const(64U, 32)), @@ -5339,14 +5335,14 @@ private: res_val, 64, false)); - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); } Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); Value* FCSR_val = this->builder.CreateAdd( this->builder.CreateAnd( this->gen_reg_load(traits::FCSR, 0), - this->builder.CreateNot(this->gen_const(32U, 31))), + this->builder.CreateNot(this->gen_const(32U, 0x1f))), flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); @@ -5382,32 +5378,32 @@ private: pc=pc+4; Value* res_val = this->builder.CreateCall(this->mod->getFunction("fdiv_s"), std::vector{ - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), - this-> get_type(32) - ), - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), - this-> get_type(32) - ), - this->gen_choose( - this->builder.CreateICmp( - ICmpInst::ICMP_ULT, - this->gen_const(3U, fld_rm_val), - this->gen_const(3U, 7)), - this->gen_const(8U, fld_rm_val), - this->builder.CreateTrunc( - this->gen_reg_load(traits::FCSR, 0), - this-> get_type(8) - ), - 8) + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this-> get_type(32) + ), + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this-> get_type(32) + ), + this->gen_choose( + this->builder.CreateICmp( + ICmpInst::ICMP_ULT, + this->gen_const(8U, fld_rm_val), + this->gen_const(8U, 7)), + this->gen_const(8U, fld_rm_val), + this->builder.CreateTrunc( + this->gen_reg_load(traits::FCSR, 0), + this-> get_type(8) + ), + 8) }); if(64 == 32){ - Value* F_rd_val = res_val; - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + Value* Ftmp0_val = res_val; + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); } else { - uint64_t upper_val = (-1); - Value* F_rd_val = this->builder.CreateOr( + int64_t upper_val = (-1); + Value* Ftmp1_val = this->builder.CreateOr( this->builder.CreateShl( this->gen_const(64U, upper_val), this->gen_const(64U, 32)), @@ -5415,14 +5411,14 @@ private: res_val, 64, false)); - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); } Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); Value* FCSR_val = this->builder.CreateAdd( this->builder.CreateAnd( this->gen_reg_load(traits::FCSR, 0), - this->builder.CreateNot(this->gen_const(32U, 31))), + this->builder.CreateNot(this->gen_const(32U, 0x1f))), flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); @@ -5457,28 +5453,28 @@ private: pc=pc+4; Value* res_val = this->builder.CreateCall(this->mod->getFunction("fsqrt_s"), std::vector{ - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), - this-> get_type(32) - ), - this->gen_choose( - this->builder.CreateICmp( - ICmpInst::ICMP_ULT, - this->gen_const(3U, fld_rm_val), - this->gen_const(3U, 7)), - this->gen_const(8U, fld_rm_val), - this->builder.CreateTrunc( - this->gen_reg_load(traits::FCSR, 0), - this-> get_type(8) - ), - 8) + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this-> get_type(32) + ), + this->gen_choose( + this->builder.CreateICmp( + ICmpInst::ICMP_ULT, + this->gen_const(8U, fld_rm_val), + this->gen_const(8U, 7)), + this->gen_const(8U, fld_rm_val), + this->builder.CreateTrunc( + this->gen_reg_load(traits::FCSR, 0), + this-> get_type(8) + ), + 8) }); if(64 == 32){ - Value* F_rd_val = res_val; - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + Value* Ftmp0_val = res_val; + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); } else { - uint64_t upper_val = (-1); - Value* F_rd_val = this->builder.CreateOr( + int64_t upper_val = (-1); + Value* Ftmp1_val = this->builder.CreateOr( this->builder.CreateShl( this->gen_const(64U, upper_val), this->gen_const(64U, 32)), @@ -5486,14 +5482,14 @@ private: res_val, 64, false)); - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); } Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); Value* FCSR_val = this->builder.CreateAdd( this->builder.CreateAnd( this->gen_reg_load(traits::FCSR, 0), - this->builder.CreateNot(this->gen_const(32U, 31))), + this->builder.CreateNot(this->gen_const(32U, 0x1f))), flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); @@ -5533,19 +5529,19 @@ private: this->gen_reg_load(fld_rs1_val + traits::F0, 0), this-> get_type(32) ), - this->gen_const(32U, 2147483647)), + this->gen_const(32U, 0x7fffffff)), this->builder.CreateAnd( this->builder.CreateTrunc( this->gen_reg_load(fld_rs2_val + traits::F0, 0), this-> get_type(32) ), - this->gen_const(32U, 2147483648))); + this->gen_const(32U, 0x80000000))); if(64 == 32){ - Value* F_rd_val = res_val; - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + Value* Ftmp0_val = res_val; + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); } else { - uint64_t upper_val = (-1); - Value* F_rd_val = this->builder.CreateOr( + int64_t upper_val = (-1); + Value* Ftmp1_val = this->builder.CreateOr( this->builder.CreateShl( this->gen_const(64U, upper_val), this->gen_const(64U, 32)), @@ -5553,7 +5549,7 @@ private: res_val, 64, false)); - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 110); @@ -5592,19 +5588,19 @@ private: this->gen_reg_load(fld_rs1_val + traits::F0, 0), this-> get_type(32) ), - this->gen_const(32U, 2147483647)), + this->gen_const(32U, 0x7fffffff)), this->builder.CreateAnd( this->builder.CreateNot(this->builder.CreateTrunc( this->gen_reg_load(fld_rs2_val + traits::F0, 0), this-> get_type(32) )), - this->gen_const(32U, 2147483648))); + this->gen_const(32U, 0x80000000))); if(64 == 32){ - Value* F_rd_val = res_val; - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + Value* Ftmp0_val = res_val; + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); } else { - uint64_t upper_val = (-1); - Value* F_rd_val = this->builder.CreateOr( + int64_t upper_val = (-1); + Value* Ftmp1_val = this->builder.CreateOr( this->builder.CreateShl( this->gen_const(64U, upper_val), this->gen_const(64U, 32)), @@ -5612,7 +5608,7 @@ private: res_val, 64, false)); - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 111); @@ -5655,13 +5651,13 @@ private: this->gen_reg_load(fld_rs2_val + traits::F0, 0), this-> get_type(32) ), - this->gen_const(32U, 2147483648))); + this->gen_const(32U, 0x80000000))); if(64 == 32){ - Value* F_rd_val = res_val; - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + Value* Ftmp0_val = res_val; + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); } else { - uint64_t upper_val = (-1); - Value* F_rd_val = this->builder.CreateOr( + int64_t upper_val = (-1); + Value* Ftmp1_val = this->builder.CreateOr( this->builder.CreateShl( this->gen_const(64U, upper_val), this->gen_const(64U, 32)), @@ -5669,7 +5665,7 @@ private: res_val, 64, false)); - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 112); @@ -5703,25 +5699,25 @@ private: pc=pc+4; Value* res_val = this->builder.CreateCall(this->mod->getFunction("fsel_s"), std::vector{ - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), - this-> get_type(32) - ), - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), - this-> get_type(32) - ), - this->gen_ext( - this->gen_const(64U, 0LL), - 32, - false) + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this-> get_type(32) + ), + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this-> get_type(32) + ), + this->gen_ext( + this->gen_const(64U, 0LL), + 32, + false) }); if(64 == 32){ - Value* F_rd_val = res_val; - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + Value* Ftmp0_val = res_val; + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); } else { - uint64_t upper_val = (-1); - Value* F_rd_val = this->builder.CreateOr( + int64_t upper_val = (-1); + Value* Ftmp1_val = this->builder.CreateOr( this->builder.CreateShl( this->gen_const(64U, upper_val), this->gen_const(64U, 32)), @@ -5729,14 +5725,14 @@ private: res_val, 64, false)); - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); } Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); Value* FCSR_val = this->builder.CreateAdd( this->builder.CreateAnd( this->gen_reg_load(traits::FCSR, 0), - this->builder.CreateNot(this->gen_const(32U, 31))), + this->builder.CreateNot(this->gen_const(32U, 0x1f))), flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); @@ -5771,25 +5767,25 @@ private: pc=pc+4; Value* res_val = this->builder.CreateCall(this->mod->getFunction("fsel_s"), std::vector{ - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), - this-> get_type(32) - ), - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), - this-> get_type(32) - ), - this->gen_ext( - this->gen_const(64U, 1LL), - 32, - false) + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this-> get_type(32) + ), + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this-> get_type(32) + ), + this->gen_ext( + this->gen_const(64U, 1LL), + 32, + false) }); if(64 == 32){ - Value* F_rd_val = res_val; - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + Value* Ftmp0_val = res_val; + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); } else { - uint64_t upper_val = (-1); - Value* F_rd_val = this->builder.CreateOr( + int64_t upper_val = (-1); + Value* Ftmp1_val = this->builder.CreateOr( this->builder.CreateShl( this->gen_const(64U, upper_val), this->gen_const(64U, 32)), @@ -5797,14 +5793,14 @@ private: res_val, 64, false)); - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); } Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); Value* FCSR_val = this->builder.CreateAdd( this->builder.CreateAnd( this->gen_reg_load(traits::FCSR, 0), - this->builder.CreateNot(this->gen_const(32U, 31))), + this->builder.CreateNot(this->gen_const(32U, 0x1f))), flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); @@ -5838,27 +5834,27 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* X_rd_val = this->gen_ext( + Value* Xtmp0_val = this->gen_ext( this->builder.CreateCall(this->mod->getFunction("fcvt_s"), std::vector{ - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), - this-> get_type(32) - ), - this->gen_ext( - this->gen_const(64U, 0LL), - 32, - false), - this->gen_const(8U, fld_rm_val) + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this-> get_type(32) + ), + this->gen_ext( + this->gen_const(64U, 0LL), + 32, + false), + this->gen_const(8U, fld_rm_val) }), 32, true); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); Value* FCSR_val = this->builder.CreateAdd( this->builder.CreateAnd( this->gen_reg_load(traits::FCSR, 0), - this->builder.CreateNot(this->gen_const(32U, 31))), + this->builder.CreateNot(this->gen_const(32U, 0x1f))), flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); @@ -5892,27 +5888,27 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* X_rd_val = this->gen_ext( + Value* Xtmp0_val = this->gen_ext( this->builder.CreateCall(this->mod->getFunction("fcvt_s"), std::vector{ - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), - this-> get_type(32) - ), - this->gen_ext( - this->gen_const(64U, 1LL), - 32, - false), - this->gen_const(8U, fld_rm_val) + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this-> get_type(32) + ), + this->gen_ext( + this->gen_const(64U, 1LL), + 32, + false), + this->gen_const(8U, fld_rm_val) }), 32, false); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); Value* FCSR_val = this->builder.CreateAdd( this->builder.CreateAnd( this->gen_reg_load(traits::FCSR, 0), - this->builder.CreateNot(this->gen_const(32U, 31))), + this->builder.CreateNot(this->gen_const(32U, 0x1f))), flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); @@ -5946,27 +5942,27 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* X_rd_val = this->builder.CreateCall(this->mod->getFunction("fcmp_s"), std::vector{ - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), - this-> get_type(32) - ), - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), - this-> get_type(32) - ), - this->gen_ext( - this->gen_const(64U, 0LL), - 32, - false) + Value* Xtmp0_val = this->builder.CreateCall(this->mod->getFunction("fcmp_s"), std::vector{ + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this-> get_type(32) + ), + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this-> get_type(32) + ), + this->gen_ext( + this->gen_const(64U, 0LL), + 32, + false) }); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); Value* FCSR_val = this->builder.CreateAdd( this->builder.CreateAnd( this->gen_reg_load(traits::FCSR, 0), - this->builder.CreateNot(this->gen_const(32U, 31))), + this->builder.CreateNot(this->gen_const(32U, 0x1f))), flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); @@ -6000,27 +5996,27 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* X_rd_val = this->builder.CreateCall(this->mod->getFunction("fcmp_s"), std::vector{ - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), - this-> get_type(32) - ), - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), - this-> get_type(32) - ), - this->gen_ext( - this->gen_const(64U, 2LL), - 32, - false) + Value* Xtmp0_val = this->builder.CreateCall(this->mod->getFunction("fcmp_s"), std::vector{ + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this-> get_type(32) + ), + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this-> get_type(32) + ), + this->gen_ext( + this->gen_const(64U, 2LL), + 32, + false) }); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); Value* FCSR_val = this->builder.CreateAdd( this->builder.CreateAnd( this->gen_reg_load(traits::FCSR, 0), - this->builder.CreateNot(this->gen_const(32U, 31))), + this->builder.CreateNot(this->gen_const(32U, 0x1f))), flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); @@ -6054,27 +6050,27 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* X_rd_val = this->builder.CreateCall(this->mod->getFunction("fcmp_s"), std::vector{ - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), - this-> get_type(32) - ), - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), - this-> get_type(32) - ), - this->gen_ext( - this->gen_const(64U, 1LL), - 32, - false) + Value* Xtmp0_val = this->builder.CreateCall(this->mod->getFunction("fcmp_s"), std::vector{ + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this-> get_type(32) + ), + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this-> get_type(32) + ), + this->gen_ext( + this->gen_const(64U, 1LL), + 32, + false) }); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); Value* FCSR_val = this->builder.CreateAdd( this->builder.CreateAnd( this->gen_reg_load(traits::FCSR, 0), - this->builder.CreateNot(this->gen_const(32U, 31))), + this->builder.CreateNot(this->gen_const(32U, 0x1f))), flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); @@ -6107,13 +6103,13 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* X_rd_val = this->builder.CreateCall(this->mod->getFunction("fclass_s"), std::vector{ - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), - this-> get_type(32) - ) + Value* Xtmp0_val = this->builder.CreateCall(this->mod->getFunction("fclass_s"), std::vector{ + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this-> get_type(32) + ) }); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 120); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -6146,22 +6142,22 @@ private: pc=pc+4; Value* res_val = this->builder.CreateCall(this->mod->getFunction("fcvt_s"), std::vector{ - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), - this-> get_type(32) - ), - this->gen_ext( - this->gen_const(64U, 2LL), - 32, - false), - this->gen_const(8U, fld_rm_val) + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this-> get_type(32) + ), + this->gen_ext( + this->gen_const(64U, 2LL), + 32, + false), + this->gen_const(8U, fld_rm_val) }); if(64 == 32){ - Value* F_rd_val = res_val; - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + Value* Ftmp0_val = res_val; + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); } else { - uint64_t upper_val = (-1); - Value* F_rd_val = this->builder.CreateOr( + int64_t upper_val = (-1); + Value* Ftmp1_val = this->builder.CreateOr( this->builder.CreateShl( this->gen_const(64U, upper_val), this->gen_const(64U, 32)), @@ -6169,7 +6165,7 @@ private: res_val, 64, false)); - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 121); @@ -6203,22 +6199,22 @@ private: pc=pc+4; Value* res_val = this->builder.CreateCall(this->mod->getFunction("fcvt_s"), std::vector{ - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), - this-> get_type(32) - ), - this->gen_ext( - this->gen_const(64U, 3LL), - 32, - false), - this->gen_const(8U, fld_rm_val) + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs1_val + traits::X0, 0), + this-> get_type(32) + ), + this->gen_ext( + this->gen_const(64U, 3LL), + 32, + false), + this->gen_const(8U, fld_rm_val) }); if(64 == 32){ - Value* F_rd_val = res_val; - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + Value* Ftmp0_val = res_val; + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); } else { - uint64_t upper_val = (-1); - Value* F_rd_val = this->builder.CreateOr( + int64_t upper_val = (-1); + Value* Ftmp1_val = this->builder.CreateOr( this->builder.CreateShl( this->gen_const(64U, upper_val), this->gen_const(64U, 32)), @@ -6226,7 +6222,7 @@ private: res_val, 64, false)); - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 122); @@ -6258,14 +6254,14 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* X_rd_val = this->gen_ext( + Value* Xtmp0_val = this->gen_ext( this->builder.CreateTrunc( this->gen_reg_load(fld_rs1_val + traits::F0, 0), this-> get_type(32) ), 32, true); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 123); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -6297,11 +6293,11 @@ private: pc=pc+4; if(64 == 32){ - Value* F_rd_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + Value* Ftmp0_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); } else { - uint64_t upper_val = (-1); - Value* F_rd_val = this->builder.CreateOr( + int64_t upper_val = (-1); + Value* Ftmp1_val = this->builder.CreateOr( this->builder.CreateShl( this->gen_const(64U, upper_val), this->gen_const(64U, 32)), @@ -6309,7 +6305,7 @@ private: this->gen_reg_load(fld_rs1_val + traits::X0, 0), 64, false)); - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 124); @@ -6342,18 +6338,16 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - uint8_t rs1_idx_val = (fld_rs1_val + 8); - uint8_t rd_idx_val = (fld_rd_val + 8); Value* offs_val = this->builder.CreateAdd( - this->gen_reg_load(rs1_idx_val + traits::X0, 0), + this->gen_reg_load((fld_rs1_val + 8) + traits::X0, 0), this->gen_const(32U, fld_uimm_val)); Value* res_val = this->gen_read_mem(traits::MEM, offs_val, 32/8); if(64 == 32){ - Value* F_rd_idx_val = res_val; - this->builder.CreateStore(F_rd_idx_val, get_reg_ptr(rd_idx_val + traits::F0), false); + Value* Ftmp0_val = res_val; + this->builder.CreateStore(Ftmp0_val, get_reg_ptr((fld_rd_val + 8) + traits::F0), false); } else { - uint64_t upper_val = (-1); - Value* F_rd_val = this->builder.CreateOr( + int64_t upper_val = (-1); + Value* Ftmp1_val = this->builder.CreateOr( this->builder.CreateShl( this->gen_const(64U, upper_val), this->gen_const(64U, 32)), @@ -6361,7 +6355,7 @@ private: res_val, 64, false)); - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr((fld_rd_val + 8) + traits::F0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 125); @@ -6394,19 +6388,17 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - uint8_t rs1_idx_val = (fld_rs1_val + 8); - uint8_t rs2_idx_val = (fld_rs2_val + 8); Value* offs_val = this->builder.CreateAdd( - this->gen_reg_load(rs1_idx_val + traits::X0, 0), + this->gen_reg_load((fld_rs1_val + 8) + traits::X0, 0), this->gen_const(32U, fld_uimm_val)); - Value* MEM_offs_val = this->builder.CreateTrunc( - this->gen_reg_load(rs2_idx_val + traits::F0, 0), + Value* MEMtmp0_val = this->builder.CreateTrunc( + this->gen_reg_load((fld_rs2_val + 8) + traits::F0, 0), this-> get_type(32) ); this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); + this->builder.CreateZExtOrTrunc(MEMtmp0_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 126); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -6437,17 +6429,16 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - uint8_t x2_idx_val = 2; Value* offs_val = this->builder.CreateAdd( - this->gen_reg_load(x2_idx_val + traits::X0, 0), + this->gen_reg_load(2 + traits::X0, 0), this->gen_const(32U, fld_uimm_val)); Value* res_val = this->gen_read_mem(traits::MEM, offs_val, 32/8); if(64 == 32){ - Value* F_rd_val = res_val; - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + Value* Ftmp0_val = res_val; + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); } else { - uint64_t upper_val = (-1); - Value* F_rd_val = this->builder.CreateOr( + int64_t upper_val = (-1); + Value* Ftmp1_val = this->builder.CreateOr( this->builder.CreateShl( this->gen_const(64U, upper_val), this->gen_const(64U, 32)), @@ -6455,7 +6446,7 @@ private: res_val, 64, false)); - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 127); @@ -6487,18 +6478,17 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - uint8_t x2_idx_val = 2; Value* offs_val = this->builder.CreateAdd( - this->gen_reg_load(x2_idx_val + traits::X0, 0), + this->gen_reg_load(2 + traits::X0, 0), this->gen_const(32U, fld_uimm_val)); - Value* MEM_offs_val = this->builder.CreateTrunc( + Value* MEMtmp0_val = this->builder.CreateTrunc( this->gen_reg_load(fld_rs2_val + traits::F0, 0), this-> get_type(32) ); this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); + this->builder.CreateZExtOrTrunc(MEMtmp0_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 128); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -6535,16 +6525,16 @@ private: this->gen_const(32U, fld_imm_val)); Value* res_val = this->gen_read_mem(traits::MEM, offs_val, 64/8); if(64 == 64){ - Value* F_rd_val = res_val; - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + Value* Ftmp0_val = res_val; + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); } else { - uint64_t upper_val = (-1); - Value* F_rd_val = this->builder.CreateOr( + int64_t upper_val = (-1); + Value* Ftmp1_val = this->builder.CreateOr( this->builder.CreateShl( this->gen_const(64U, upper_val), this->gen_const(64U, 64)), res_val); - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 129); @@ -6580,14 +6570,14 @@ private: Value* offs_val = this->builder.CreateAdd( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(32U, fld_imm_val)); - Value* MEM_offs_val = this->builder.CreateTrunc( + Value* MEMtmp0_val = this->builder.CreateTrunc( this->gen_reg_load(fld_rs2_val + traits::F0, 0), this-> get_type(64) ); this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(64))); + this->builder.CreateZExtOrTrunc(MEMtmp0_val,this->get_type(64))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 130); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -6622,52 +6612,52 @@ private: pc=pc+4; Value* res_val = this->builder.CreateCall(this->mod->getFunction("fmadd_d"), std::vector{ - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), - this-> get_type(64) - ), - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), - this-> get_type(64) - ), - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs3_val + traits::F0, 0), - this-> get_type(64) - ), - this->gen_ext( - this->gen_const(64U, 0LL), - 64, - false), - this->gen_choose( - this->builder.CreateICmp( - ICmpInst::ICMP_ULT, - this->gen_const(3U, fld_rm_val), - this->gen_const(3U, 7)), - this->gen_const(8U, fld_rm_val), - this->builder.CreateTrunc( - this->gen_reg_load(traits::FCSR, 0), - this-> get_type(8) - ), - 8) + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this-> get_type(64) + ), + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this-> get_type(64) + ), + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs3_val + traits::F0, 0), + this-> get_type(64) + ), + this->gen_ext( + this->gen_const(64U, 0LL), + 64, + false), + this->gen_choose( + this->builder.CreateICmp( + ICmpInst::ICMP_ULT, + this->gen_const(8U, fld_rm_val), + this->gen_const(8U, 7)), + this->gen_const(8U, fld_rm_val), + this->builder.CreateTrunc( + this->gen_reg_load(traits::FCSR, 0), + this-> get_type(8) + ), + 8) }); if(64 == 64){ - Value* F_rd_val = res_val; - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + Value* Ftmp0_val = res_val; + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); } else { - uint64_t upper_val = (-1); - Value* F_rd_val = this->builder.CreateOr( + int64_t upper_val = (-1); + Value* Ftmp1_val = this->builder.CreateOr( this->builder.CreateShl( this->gen_const(64U, upper_val), this->gen_const(64U, 64)), res_val); - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); } Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); Value* FCSR_val = this->builder.CreateAdd( this->builder.CreateAnd( this->gen_reg_load(traits::FCSR, 0), - this->builder.CreateNot(this->gen_const(32U, 31))), + this->builder.CreateNot(this->gen_const(32U, 0x1f))), flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); @@ -6704,52 +6694,52 @@ private: pc=pc+4; Value* res_val = this->builder.CreateCall(this->mod->getFunction("fmadd_d"), std::vector{ - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), - this-> get_type(64) - ), - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), - this-> get_type(64) - ), - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs3_val + traits::F0, 0), - this-> get_type(64) - ), - this->gen_ext( - this->gen_const(64U, 1LL), - 32, - false), - this->gen_choose( - this->builder.CreateICmp( - ICmpInst::ICMP_ULT, - this->gen_const(3U, fld_rm_val), - this->gen_const(3U, 7)), - this->gen_const(8U, fld_rm_val), - this->builder.CreateTrunc( - this->gen_reg_load(traits::FCSR, 0), - this-> get_type(8) - ), - 8) + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this-> get_type(64) + ), + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this-> get_type(64) + ), + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs3_val + traits::F0, 0), + this-> get_type(64) + ), + this->gen_ext( + this->gen_const(64U, 1LL), + 32, + false), + this->gen_choose( + this->builder.CreateICmp( + ICmpInst::ICMP_ULT, + this->gen_const(8U, fld_rm_val), + this->gen_const(8U, 7)), + this->gen_const(8U, fld_rm_val), + this->builder.CreateTrunc( + this->gen_reg_load(traits::FCSR, 0), + this-> get_type(8) + ), + 8) }); if(64 == 64){ - Value* F_rd_val = res_val; - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + Value* Ftmp0_val = res_val; + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); } else { - uint64_t upper_val = (-1); - Value* F_rd_val = this->builder.CreateOr( + int64_t upper_val = (-1); + Value* Ftmp1_val = this->builder.CreateOr( this->builder.CreateShl( this->gen_const(64U, upper_val), this->gen_const(64U, 64)), res_val); - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); } Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); Value* FCSR_val = this->builder.CreateAdd( this->builder.CreateAnd( this->gen_reg_load(traits::FCSR, 0), - this->builder.CreateNot(this->gen_const(32U, 31))), + this->builder.CreateNot(this->gen_const(32U, 0x1f))), flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); @@ -6786,52 +6776,52 @@ private: pc=pc+4; Value* res_val = this->builder.CreateCall(this->mod->getFunction("fmadd_d"), std::vector{ - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), - this-> get_type(64) - ), - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), - this-> get_type(64) - ), - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs3_val + traits::F0, 0), - this-> get_type(64) - ), - this->gen_ext( - this->gen_const(64U, 2LL), - 32, - false), - this->gen_choose( - this->builder.CreateICmp( - ICmpInst::ICMP_ULT, - this->gen_const(3U, fld_rm_val), - this->gen_const(3U, 7)), - this->gen_const(8U, fld_rm_val), - this->builder.CreateTrunc( - this->gen_reg_load(traits::FCSR, 0), - this-> get_type(8) - ), - 8) + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this-> get_type(64) + ), + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this-> get_type(64) + ), + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs3_val + traits::F0, 0), + this-> get_type(64) + ), + this->gen_ext( + this->gen_const(64U, 2LL), + 32, + false), + this->gen_choose( + this->builder.CreateICmp( + ICmpInst::ICMP_ULT, + this->gen_const(8U, fld_rm_val), + this->gen_const(8U, 7)), + this->gen_const(8U, fld_rm_val), + this->builder.CreateTrunc( + this->gen_reg_load(traits::FCSR, 0), + this-> get_type(8) + ), + 8) }); if(64 == 64){ - Value* F_rd_val = res_val; - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + Value* Ftmp0_val = res_val; + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); } else { - uint64_t upper_val = (-1); - Value* F_rd_val = this->builder.CreateOr( + int64_t upper_val = (-1); + Value* Ftmp1_val = this->builder.CreateOr( this->builder.CreateShl( this->gen_const(64U, upper_val), this->gen_const(64U, 64)), res_val); - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); } Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); Value* FCSR_val = this->builder.CreateAdd( this->builder.CreateAnd( this->gen_reg_load(traits::FCSR, 0), - this->builder.CreateNot(this->gen_const(32U, 31))), + this->builder.CreateNot(this->gen_const(32U, 0x1f))), flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); @@ -6868,52 +6858,52 @@ private: pc=pc+4; Value* res_val = this->builder.CreateCall(this->mod->getFunction("fmadd_d"), std::vector{ - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), - this-> get_type(64) - ), - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), - this-> get_type(64) - ), - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs3_val + traits::F0, 0), - this-> get_type(64) - ), - this->gen_ext( - this->gen_const(64U, 3LL), - 32, - false), - this->gen_choose( - this->builder.CreateICmp( - ICmpInst::ICMP_ULT, - this->gen_const(3U, fld_rm_val), - this->gen_const(3U, 7)), - this->gen_const(8U, fld_rm_val), - this->builder.CreateTrunc( - this->gen_reg_load(traits::FCSR, 0), - this-> get_type(8) - ), - 8) + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this-> get_type(64) + ), + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this-> get_type(64) + ), + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs3_val + traits::F0, 0), + this-> get_type(64) + ), + this->gen_ext( + this->gen_const(64U, 3LL), + 32, + false), + this->gen_choose( + this->builder.CreateICmp( + ICmpInst::ICMP_ULT, + this->gen_const(8U, fld_rm_val), + this->gen_const(8U, 7)), + this->gen_const(8U, fld_rm_val), + this->builder.CreateTrunc( + this->gen_reg_load(traits::FCSR, 0), + this-> get_type(8) + ), + 8) }); if(64 == 64){ - Value* F_rd_val = res_val; - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + Value* Ftmp0_val = res_val; + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); } else { - uint64_t upper_val = (-1); - Value* F_rd_val = this->builder.CreateOr( + int64_t upper_val = (-1); + Value* Ftmp1_val = this->builder.CreateOr( this->builder.CreateShl( this->gen_const(64U, upper_val), this->gen_const(64U, 64)), res_val); - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); } Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); Value* FCSR_val = this->builder.CreateAdd( this->builder.CreateAnd( this->gen_reg_load(traits::FCSR, 0), - this->builder.CreateNot(this->gen_const(32U, 31))), + this->builder.CreateNot(this->gen_const(32U, 0x1f))), flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); @@ -6949,44 +6939,44 @@ private: pc=pc+4; Value* res_val = this->builder.CreateCall(this->mod->getFunction("fadd_d"), std::vector{ - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), - this-> get_type(64) - ), - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), - this-> get_type(64) - ), - this->gen_choose( - this->builder.CreateICmp( - ICmpInst::ICMP_ULT, - this->gen_const(3U, fld_rm_val), - this->gen_const(3U, 7)), - this->gen_const(8U, fld_rm_val), - this->builder.CreateTrunc( - this->gen_reg_load(traits::FCSR, 0), - this-> get_type(8) - ), - 8) + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this-> get_type(64) + ), + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this-> get_type(64) + ), + this->gen_choose( + this->builder.CreateICmp( + ICmpInst::ICMP_ULT, + this->gen_const(8U, fld_rm_val), + this->gen_const(8U, 7)), + this->gen_const(8U, fld_rm_val), + this->builder.CreateTrunc( + this->gen_reg_load(traits::FCSR, 0), + this-> get_type(8) + ), + 8) }); if(64 == 64){ - Value* F_rd_val = res_val; - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + Value* Ftmp0_val = res_val; + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); } else { - uint64_t upper_val = (-1); - Value* F_rd_val = this->builder.CreateOr( + int64_t upper_val = (-1); + Value* Ftmp1_val = this->builder.CreateOr( this->builder.CreateShl( this->gen_const(64U, upper_val), this->gen_const(64U, 64)), res_val); - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); } Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); Value* FCSR_val = this->builder.CreateAdd( this->builder.CreateAnd( this->gen_reg_load(traits::FCSR, 0), - this->builder.CreateNot(this->gen_const(32U, 31))), + this->builder.CreateNot(this->gen_const(32U, 0x1f))), flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); @@ -7022,44 +7012,44 @@ private: pc=pc+4; Value* res_val = this->builder.CreateCall(this->mod->getFunction("fsub_d"), std::vector{ - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), - this-> get_type(64) - ), - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), - this-> get_type(64) - ), - this->gen_choose( - this->builder.CreateICmp( - ICmpInst::ICMP_ULT, - this->gen_const(3U, fld_rm_val), - this->gen_const(3U, 7)), - this->gen_const(8U, fld_rm_val), - this->builder.CreateTrunc( - this->gen_reg_load(traits::FCSR, 0), - this-> get_type(8) - ), - 8) + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this-> get_type(64) + ), + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this-> get_type(64) + ), + this->gen_choose( + this->builder.CreateICmp( + ICmpInst::ICMP_ULT, + this->gen_const(8U, fld_rm_val), + this->gen_const(8U, 7)), + this->gen_const(8U, fld_rm_val), + this->builder.CreateTrunc( + this->gen_reg_load(traits::FCSR, 0), + this-> get_type(8) + ), + 8) }); if(64 == 64){ - Value* F_rd_val = res_val; - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + Value* Ftmp0_val = res_val; + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); } else { - uint64_t upper_val = (-1); - Value* F_rd_val = this->builder.CreateOr( + int64_t upper_val = (-1); + Value* Ftmp1_val = this->builder.CreateOr( this->builder.CreateShl( this->gen_const(64U, upper_val), this->gen_const(64U, 64)), res_val); - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); } Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); Value* FCSR_val = this->builder.CreateAdd( this->builder.CreateAnd( this->gen_reg_load(traits::FCSR, 0), - this->builder.CreateNot(this->gen_const(32U, 31))), + this->builder.CreateNot(this->gen_const(32U, 0x1f))), flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); @@ -7095,44 +7085,44 @@ private: pc=pc+4; Value* res_val = this->builder.CreateCall(this->mod->getFunction("fmul_d"), std::vector{ - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), - this-> get_type(64) - ), - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), - this-> get_type(64) - ), - this->gen_choose( - this->builder.CreateICmp( - ICmpInst::ICMP_ULT, - this->gen_const(3U, fld_rm_val), - this->gen_const(3U, 7)), - this->gen_const(8U, fld_rm_val), - this->builder.CreateTrunc( - this->gen_reg_load(traits::FCSR, 0), - this-> get_type(8) - ), - 8) + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this-> get_type(64) + ), + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this-> get_type(64) + ), + this->gen_choose( + this->builder.CreateICmp( + ICmpInst::ICMP_ULT, + this->gen_const(8U, fld_rm_val), + this->gen_const(8U, 7)), + this->gen_const(8U, fld_rm_val), + this->builder.CreateTrunc( + this->gen_reg_load(traits::FCSR, 0), + this-> get_type(8) + ), + 8) }); if(64 == 64){ - Value* F_rd_val = res_val; - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + Value* Ftmp0_val = res_val; + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); } else { - uint64_t upper_val = (-1); - Value* F_rd_val = this->builder.CreateOr( + int64_t upper_val = (-1); + Value* Ftmp1_val = this->builder.CreateOr( this->builder.CreateShl( this->gen_const(64U, upper_val), this->gen_const(64U, 64)), res_val); - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); } Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); Value* FCSR_val = this->builder.CreateAdd( this->builder.CreateAnd( this->gen_reg_load(traits::FCSR, 0), - this->builder.CreateNot(this->gen_const(32U, 31))), + this->builder.CreateNot(this->gen_const(32U, 0x1f))), flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); @@ -7168,44 +7158,44 @@ private: pc=pc+4; Value* res_val = this->builder.CreateCall(this->mod->getFunction("fdiv_d"), std::vector{ - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), - this-> get_type(64) - ), - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), - this-> get_type(64) - ), - this->gen_choose( - this->builder.CreateICmp( - ICmpInst::ICMP_ULT, - this->gen_const(3U, fld_rm_val), - this->gen_const(3U, 7)), - this->gen_const(8U, fld_rm_val), - this->builder.CreateTrunc( - this->gen_reg_load(traits::FCSR, 0), - this-> get_type(8) - ), - 8) + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this-> get_type(64) + ), + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this-> get_type(64) + ), + this->gen_choose( + this->builder.CreateICmp( + ICmpInst::ICMP_ULT, + this->gen_const(8U, fld_rm_val), + this->gen_const(8U, 7)), + this->gen_const(8U, fld_rm_val), + this->builder.CreateTrunc( + this->gen_reg_load(traits::FCSR, 0), + this-> get_type(8) + ), + 8) }); if(64 == 64){ - Value* F_rd_val = res_val; - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + Value* Ftmp0_val = res_val; + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); } else { - uint64_t upper_val = (-1); - Value* F_rd_val = this->builder.CreateOr( + int64_t upper_val = (-1); + Value* Ftmp1_val = this->builder.CreateOr( this->builder.CreateShl( this->gen_const(64U, upper_val), this->gen_const(64U, 64)), res_val); - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); } Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); Value* FCSR_val = this->builder.CreateAdd( this->builder.CreateAnd( this->gen_reg_load(traits::FCSR, 0), - this->builder.CreateNot(this->gen_const(32U, 31))), + this->builder.CreateNot(this->gen_const(32U, 0x1f))), flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); @@ -7240,40 +7230,40 @@ private: pc=pc+4; Value* res_val = this->builder.CreateCall(this->mod->getFunction("fsqrt_d"), std::vector{ - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), - this-> get_type(64) - ), - this->gen_choose( - this->builder.CreateICmp( - ICmpInst::ICMP_ULT, - this->gen_const(3U, fld_rm_val), - this->gen_const(3U, 7)), - this->gen_const(8U, fld_rm_val), - this->builder.CreateTrunc( - this->gen_reg_load(traits::FCSR, 0), - this-> get_type(8) - ), - 8) + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this-> get_type(64) + ), + this->gen_choose( + this->builder.CreateICmp( + ICmpInst::ICMP_ULT, + this->gen_const(8U, fld_rm_val), + this->gen_const(8U, 7)), + this->gen_const(8U, fld_rm_val), + this->builder.CreateTrunc( + this->gen_reg_load(traits::FCSR, 0), + this-> get_type(8) + ), + 8) }); if(64 == 64){ - Value* F_rd_val = res_val; - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + Value* Ftmp0_val = res_val; + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); } else { - uint64_t upper_val = (-1); - Value* F_rd_val = this->builder.CreateOr( + int64_t upper_val = (-1); + Value* Ftmp1_val = this->builder.CreateOr( this->builder.CreateShl( this->gen_const(64U, upper_val), this->gen_const(64U, 64)), res_val); - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); } Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); Value* FCSR_val = this->builder.CreateAdd( this->builder.CreateAnd( this->gen_reg_load(traits::FCSR, 0), - this->builder.CreateNot(this->gen_const(32U, 31))), + this->builder.CreateNot(this->gen_const(32U, 0x1f))), flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); @@ -7313,24 +7303,24 @@ private: this->gen_reg_load(fld_rs1_val + traits::F0, 0), this-> get_type(64) ), - this->gen_const(64U, 2147483647)), + this->gen_const(64U, 0x7fffffff)), this->builder.CreateAnd( this->builder.CreateTrunc( this->gen_reg_load(fld_rs2_val + traits::F0, 0), this-> get_type(64) ), - this->gen_const(64U, 2147483648))); + this->gen_const(64U, 0x80000000))); if(64 == 64){ - Value* F_rd_val = res_val; - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + Value* Ftmp0_val = res_val; + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); } else { - uint64_t upper_val = (-1); - Value* F_rd_val = this->builder.CreateOr( + int64_t upper_val = (-1); + Value* Ftmp1_val = this->builder.CreateOr( this->builder.CreateShl( this->gen_const(64U, upper_val), this->gen_const(64U, 64)), res_val); - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 140); @@ -7369,24 +7359,24 @@ private: this->gen_reg_load(fld_rs1_val + traits::F0, 0), this-> get_type(64) ), - this->gen_const(64U, 2147483647)), + this->gen_const(64U, 0x7fffffff)), this->builder.CreateAnd( this->builder.CreateNot(this->builder.CreateTrunc( this->gen_reg_load(fld_rs2_val + traits::F0, 0), this-> get_type(64) )), - this->gen_const(64U, 2147483648))); + this->gen_const(64U, 0x80000000))); if(64 == 64){ - Value* F_rd_val = res_val; - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + Value* Ftmp0_val = res_val; + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); } else { - uint64_t upper_val = (-1); - Value* F_rd_val = this->builder.CreateOr( + int64_t upper_val = (-1); + Value* Ftmp1_val = this->builder.CreateOr( this->builder.CreateShl( this->gen_const(64U, upper_val), this->gen_const(64U, 64)), res_val); - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 141); @@ -7429,18 +7419,18 @@ private: this->gen_reg_load(fld_rs2_val + traits::F0, 0), this-> get_type(64) ), - this->gen_const(64U, 2147483648))); + this->gen_const(64U, 0x80000000))); if(64 == 64){ - Value* F_rd_val = res_val; - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + Value* Ftmp0_val = res_val; + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); } else { - uint64_t upper_val = (-1); - Value* F_rd_val = this->builder.CreateOr( + int64_t upper_val = (-1); + Value* Ftmp1_val = this->builder.CreateOr( this->builder.CreateShl( this->gen_const(64U, upper_val), this->gen_const(64U, 64)), res_val); - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 142); @@ -7474,37 +7464,37 @@ private: pc=pc+4; Value* res_val = this->builder.CreateCall(this->mod->getFunction("fsel_d"), std::vector{ - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), - this-> get_type(64) - ), - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), - this-> get_type(64) - ), - this->gen_ext( - this->gen_const(64U, 0LL), - 32, - false) + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this-> get_type(64) + ), + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this-> get_type(64) + ), + this->gen_ext( + this->gen_const(64U, 0LL), + 32, + false) }); if(64 == 64){ - Value* F_rd_val = res_val; - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + Value* Ftmp0_val = res_val; + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); } else { - uint64_t upper_val = (-1); - Value* F_rd_val = this->builder.CreateOr( + int64_t upper_val = (-1); + Value* Ftmp1_val = this->builder.CreateOr( this->builder.CreateShl( this->gen_const(64U, upper_val), this->gen_const(64U, 64)), res_val); - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); } Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); Value* FCSR_val = this->builder.CreateAdd( this->builder.CreateAnd( this->gen_reg_load(traits::FCSR, 0), - this->builder.CreateNot(this->gen_const(32U, 31))), + this->builder.CreateNot(this->gen_const(32U, 0x1f))), flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); @@ -7539,37 +7529,37 @@ private: pc=pc+4; Value* res_val = this->builder.CreateCall(this->mod->getFunction("fsel_d"), std::vector{ - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), - this-> get_type(64) - ), - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), - this-> get_type(64) - ), - this->gen_ext( - this->gen_const(64U, 1LL), - 32, - false) + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this-> get_type(64) + ), + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this-> get_type(64) + ), + this->gen_ext( + this->gen_const(64U, 1LL), + 32, + false) }); if(64 == 64){ - Value* F_rd_val = res_val; - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + Value* Ftmp0_val = res_val; + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); } else { - uint64_t upper_val = (-1); - Value* F_rd_val = this->builder.CreateOr( + int64_t upper_val = (-1); + Value* Ftmp1_val = this->builder.CreateOr( this->builder.CreateShl( this->gen_const(64U, upper_val), this->gen_const(64U, 64)), res_val); - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); } Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); Value* FCSR_val = this->builder.CreateAdd( this->builder.CreateAnd( this->gen_reg_load(traits::FCSR, 0), - this->builder.CreateNot(this->gen_const(32U, 31))), + this->builder.CreateNot(this->gen_const(32U, 0x1f))), flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); @@ -7604,11 +7594,11 @@ private: pc=pc+4; Value* res_val = this->builder.CreateCall(this->mod->getFunction("fconv_d2f"), std::vector{ - this->gen_reg_load(fld_rs1_val + traits::F0, 0), - this->gen_const(8U, fld_rm_val) + this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this->gen_const(8U, fld_rm_val) }); - uint64_t upper_val = (-1); - Value* F_rd_val = this->builder.CreateOr( + int64_t upper_val = (-1); + Value* Ftmp0_val = this->builder.CreateOr( this->builder.CreateShl( this->gen_const(64U, upper_val), this->gen_const(64U, 32)), @@ -7616,7 +7606,7 @@ private: res_val, 64, false)); - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 145); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -7649,23 +7639,23 @@ private: pc=pc+4; Value* res_val = this->builder.CreateCall(this->mod->getFunction("fconv_f2d"), std::vector{ - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), - this-> get_type(32) - ), - this->gen_const(8U, fld_rm_val) + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this-> get_type(32) + ), + this->gen_const(8U, fld_rm_val) }); if(64 == 64){ - Value* F_rd_val = res_val; - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + Value* Ftmp0_val = res_val; + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); } else { - uint64_t upper_val = (-1); - Value* F_rd_val = this->builder.CreateOr( + int64_t upper_val = (-1); + Value* Ftmp1_val = this->builder.CreateOr( this->builder.CreateShl( this->gen_const(64U, upper_val), this->gen_const(64U, 64)), res_val); - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 146); @@ -7698,27 +7688,27 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* X_rd_val = this->builder.CreateCall(this->mod->getFunction("fcmp_d"), std::vector{ - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), - this-> get_type(64) - ), - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), - this-> get_type(64) - ), - this->gen_ext( - this->gen_const(64U, 0LL), - 32, - false) + Value* Xtmp0_val = this->builder.CreateCall(this->mod->getFunction("fcmp_d"), std::vector{ + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this-> get_type(64) + ), + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this-> get_type(64) + ), + this->gen_ext( + this->gen_const(64U, 0LL), + 32, + false) }); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); Value* FCSR_val = this->builder.CreateAdd( this->builder.CreateAnd( this->gen_reg_load(traits::FCSR, 0), - this->builder.CreateNot(this->gen_const(32U, 31))), + this->builder.CreateNot(this->gen_const(32U, 0x1f))), flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); @@ -7752,27 +7742,27 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* X_rd_val = this->builder.CreateCall(this->mod->getFunction("fcmp_d"), std::vector{ - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), - this-> get_type(64) - ), - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), - this-> get_type(64) - ), - this->gen_ext( - this->gen_const(64U, 2LL), - 32, - false) + Value* Xtmp0_val = this->builder.CreateCall(this->mod->getFunction("fcmp_d"), std::vector{ + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this-> get_type(64) + ), + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this-> get_type(64) + ), + this->gen_ext( + this->gen_const(64U, 2LL), + 32, + false) }); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); Value* FCSR_val = this->builder.CreateAdd( this->builder.CreateAnd( this->gen_reg_load(traits::FCSR, 0), - this->builder.CreateNot(this->gen_const(32U, 31))), + this->builder.CreateNot(this->gen_const(32U, 0x1f))), flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); @@ -7806,27 +7796,27 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* X_rd_val = this->builder.CreateCall(this->mod->getFunction("fcmp_d"), std::vector{ - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), - this-> get_type(64) - ), - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs2_val + traits::F0, 0), - this-> get_type(64) - ), - this->gen_ext( - this->gen_const(64U, 1LL), - 32, - false) + Value* Xtmp0_val = this->builder.CreateCall(this->mod->getFunction("fcmp_d"), std::vector{ + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this-> get_type(64) + ), + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs2_val + traits::F0, 0), + this-> get_type(64) + ), + this->gen_ext( + this->gen_const(64U, 1LL), + 32, + false) }); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); Value* FCSR_val = this->builder.CreateAdd( this->builder.CreateAnd( this->gen_reg_load(traits::FCSR, 0), - this->builder.CreateNot(this->gen_const(32U, 31))), + this->builder.CreateNot(this->gen_const(32U, 0x1f))), flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); @@ -7859,13 +7849,13 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* X_rd_val = this->builder.CreateCall(this->mod->getFunction("fclass_d"), std::vector{ - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), - this-> get_type(64) - ) + Value* Xtmp0_val = this->builder.CreateCall(this->mod->getFunction("fclass_d"), std::vector{ + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this-> get_type(64) + ) }); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 150); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -7897,27 +7887,27 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* X_rd_val = this->gen_ext( + Value* Xtmp0_val = this->gen_ext( this->builder.CreateCall(this->mod->getFunction("fcvt_d"), std::vector{ - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), - this-> get_type(64) - ), - this->gen_ext( - this->gen_const(64U, 0LL), - 32, - false), - this->gen_const(8U, fld_rm_val) + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this-> get_type(64) + ), + this->gen_ext( + this->gen_const(64U, 0LL), + 32, + false), + this->gen_const(8U, fld_rm_val) }), 32, true); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); Value* FCSR_val = this->builder.CreateAdd( this->builder.CreateAnd( this->gen_reg_load(traits::FCSR, 0), - this->builder.CreateNot(this->gen_const(32U, 31))), + this->builder.CreateNot(this->gen_const(32U, 0x1f))), flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); @@ -7951,27 +7941,27 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* X_rd_val = this->gen_ext( + Value* Xtmp0_val = this->gen_ext( this->builder.CreateCall(this->mod->getFunction("fcvt_d"), std::vector{ - this->builder.CreateTrunc( - this->gen_reg_load(fld_rs1_val + traits::F0, 0), - this-> get_type(64) - ), - this->gen_ext( - this->gen_const(64U, 1LL), - 32, - false), - this->gen_const(8U, fld_rm_val) + this->builder.CreateTrunc( + this->gen_reg_load(fld_rs1_val + traits::F0, 0), + this-> get_type(64) + ), + this->gen_ext( + this->gen_const(64U, 1LL), + 32, + false), + this->gen_const(8U, fld_rm_val) }), 32, false); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); Value* flags_val = this->builder.CreateCall(this->mod->getFunction("fget_flags"), std::vector{ }); Value* FCSR_val = this->builder.CreateAdd( this->builder.CreateAnd( this->gen_reg_load(traits::FCSR, 0), - this->builder.CreateNot(this->gen_const(32U, 31))), + this->builder.CreateNot(this->gen_const(32U, 0x1f))), flags_val); this->builder.CreateStore(FCSR_val, get_reg_ptr(traits::FCSR), false); this->gen_set_pc(pc, traits::NEXT_PC); @@ -8006,27 +7996,27 @@ private: pc=pc+4; Value* res_val = this->builder.CreateCall(this->mod->getFunction("fcvt_d"), std::vector{ - this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), - 64, - true), - this->gen_ext( - this->gen_const(64U, 2LL), - 32, - false), - this->gen_const(8U, fld_rm_val) + this->gen_ext( + this->gen_reg_load(fld_rs1_val + traits::X0, 0), + 64, + true), + this->gen_ext( + this->gen_const(64U, 2LL), + 32, + false), + this->gen_const(8U, fld_rm_val) }); if(64 == 64){ - Value* F_rd_val = res_val; - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + Value* Ftmp0_val = res_val; + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); } else { - uint64_t upper_val = (-1); - Value* F_rd_val = this->builder.CreateOr( + int64_t upper_val = (-1); + Value* Ftmp1_val = this->builder.CreateOr( this->builder.CreateShl( this->gen_const(64U, upper_val), this->gen_const(64U, 64)), res_val); - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 153); @@ -8060,27 +8050,27 @@ private: pc=pc+4; Value* res_val = this->builder.CreateCall(this->mod->getFunction("fcvt_d"), std::vector{ - this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 0), - 64, - false), - this->gen_ext( - this->gen_const(64U, 3LL), - 32, - false), - this->gen_const(8U, fld_rm_val) + this->gen_ext( + this->gen_reg_load(fld_rs1_val + traits::X0, 0), + 64, + false), + this->gen_ext( + this->gen_const(64U, 3LL), + 32, + false), + this->gen_const(8U, fld_rm_val) }); if(64 == 64){ - Value* F_rd_val = res_val; - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + Value* Ftmp0_val = res_val; + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); } else { - uint64_t upper_val = (-1); - Value* F_rd_val = this->builder.CreateOr( + int64_t upper_val = (-1); + Value* Ftmp1_val = this->builder.CreateOr( this->builder.CreateShl( this->gen_const(64U, upper_val), this->gen_const(64U, 64)), res_val); - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 154); @@ -8113,23 +8103,21 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - uint8_t rs1_idx_val = (fld_rs1_val + 8); - uint8_t rd_idx_val = (fld_rd_val + 8); Value* offs_val = this->builder.CreateAdd( - this->gen_reg_load(rs1_idx_val + traits::X0, 0), + this->gen_reg_load((fld_rs1_val + 8) + traits::X0, 0), this->gen_const(32U, fld_uimm_val)); Value* res_val = this->gen_read_mem(traits::MEM, offs_val, 64/8); if(64 == 64){ - Value* F_rd_idx_val = res_val; - this->builder.CreateStore(F_rd_idx_val, get_reg_ptr(rd_idx_val + traits::F0), false); + Value* Ftmp0_val = res_val; + this->builder.CreateStore(Ftmp0_val, get_reg_ptr((fld_rd_val + 8) + traits::F0), false); } else { - uint64_t upper_val = (-1); - Value* F_rd_idx_val = this->builder.CreateOr( + int64_t upper_val = (-1); + Value* Ftmp1_val = this->builder.CreateOr( this->builder.CreateShl( this->gen_const(64U, upper_val), this->gen_const(64U, 64)), res_val); - this->builder.CreateStore(F_rd_idx_val, get_reg_ptr(rd_idx_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr((fld_rd_val + 8) + traits::F0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 155); @@ -8162,19 +8150,17 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - uint8_t rs1_idx_val = (fld_rs1_val + 8); - uint8_t rs2_idx_val = (fld_rs2_val + 8); Value* offs_val = this->builder.CreateAdd( - this->gen_reg_load(rs1_idx_val + traits::X0, 0), + this->gen_reg_load((fld_rs1_val + 8) + traits::X0, 0), this->gen_const(32U, fld_uimm_val)); - Value* MEM_offs_val = this->builder.CreateTrunc( - this->gen_reg_load(rs2_idx_val + traits::F0, 0), + Value* MEMtmp0_val = this->builder.CreateTrunc( + this->gen_reg_load((fld_rs2_val + 8) + traits::F0, 0), this-> get_type(64) ); this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(64))); + this->builder.CreateZExtOrTrunc(MEMtmp0_val,this->get_type(64))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 156); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -8205,17 +8191,16 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - uint8_t x2_idx_val = 2; Value* offs_val = this->builder.CreateAdd( - this->gen_reg_load(x2_idx_val + traits::X0, 0), + this->gen_reg_load(2 + traits::X0, 0), this->gen_const(32U, fld_uimm_val)); Value* res_val = this->gen_read_mem(traits::MEM, offs_val, 64/8); if(64 == 64){ - Value* F_rd_val = res_val; - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + Value* Ftmp0_val = res_val; + this->builder.CreateStore(Ftmp0_val, get_reg_ptr(fld_rd_val + traits::F0), false); } else { - uint64_t upper_val = (-1); - Value* F_rd_val = this->builder.CreateOr( + int64_t upper_val = (-1); + Value* Ftmp1_val = this->builder.CreateOr( this->builder.CreateShl( this->gen_const(64U, upper_val), this->gen_const(64U, 64)), @@ -8223,7 +8208,7 @@ private: res_val, 64, false)); - this->builder.CreateStore(F_rd_val, get_reg_ptr(fld_rd_val + traits::F0), false); + this->builder.CreateStore(Ftmp1_val, get_reg_ptr(fld_rd_val + traits::F0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 157); @@ -8255,18 +8240,17 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - uint8_t x2_idx_val = 2; Value* offs_val = this->builder.CreateAdd( - this->gen_reg_load(x2_idx_val + traits::X0, 0), + this->gen_reg_load(2 + traits::X0, 0), this->gen_const(32U, fld_uimm_val)); - Value* MEM_offs_val = this->builder.CreateTrunc( + Value* MEMtmp0_val = this->builder.CreateTrunc( this->gen_reg_load(fld_rs2_val + traits::F0, 0), this-> get_type(64) ); this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(64))); + this->builder.CreateZExtOrTrunc(MEMtmp0_val,this->get_type(64))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 158); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -8393,16 +8377,7 @@ template inline void vm_impl::gen_trap_check(llvm::BasicBl bb, this->trap_blk, 1); } -template -inline llvm::Value* vm_impl::gen_fdispatch(std::string fname, const std::vector& args) { - return this->builder.CreateCall(this->mod->getFunction(fname), args); -} - -template -inline llvm::Value* vm_impl::gen_dispatch(std::string name, llvm::Value* val1, llvm::Value* val2, llvm::Value* val3) { -} - -} // namespace rv32imacf +} // namespace rv32gc template <> std::unique_ptr create(arch::rv32gc *core, unsigned short port, bool dump) { diff --git a/riscv/src/internal/vm_rv32imac.cpp b/riscv/src/internal/vm_rv32imac.cpp index cd0cce9..9a78518 100644 --- a/riscv/src/internal/vm_rv32imac.cpp +++ b/riscv/src/internal/vm_rv32imac.cpp @@ -112,15 +112,10 @@ protected: void gen_trap_check(llvm::BasicBlock *bb); - inline llvm::Value *gen_reg_load(unsigned i, unsigned level = 0) { return this->builder.CreateLoad(get_reg_ptr(i), false); } - llvm::Value* gen_fdispatch(std::string fname, const std::vector& args); - - llvm::Value* gen_dispatch(std::string name, llvm::Value*, llvm::Value*, llvm::Value*); - inline void gen_set_pc(virt_addr_t pc, unsigned reg_num) { llvm::Value *next_pc_v = this->builder.CreateSExtOrTrunc(this->gen_const(traits::XLEN, pc.val), this->get_type(traits::XLEN)); @@ -421,8 +416,8 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->gen_const(32U, fld_imm_val); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = this->gen_const(32U, fld_imm_val); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 0); @@ -455,10 +450,10 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateAdd( + Value* Xtmp0_val = this->builder.CreateAdd( cur_pc_val, this->gen_const(32U, fld_imm_val)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 1); @@ -491,10 +486,10 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateAdd( + Value* Xtmp0_val = this->builder.CreateAdd( cur_pc_val, this->gen_const(32U, 4)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } Value* PC_val = this->builder.CreateAdd( cur_pc_val, @@ -530,17 +525,17 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateAdd( + Value* Xtmp0_val = this->builder.CreateAdd( cur_pc_val, this->gen_const(32U, 4)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } Value* ret_val = this->builder.CreateAdd( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(32U, fld_imm_val)); Value* PC_val = this->builder.CreateAnd( ret_val, - this->builder.CreateNot(this->gen_const(32U, 1))); + this->builder.CreateNot(this->gen_const(32U, 0x1))); this->builder.CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); this->gen_sync(iss::POST_SYNC, 3); this->gen_trap_check(this->leave_blk); @@ -835,11 +830,11 @@ private: this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(32U, fld_imm_val)); if(fld_rd_val != 0){ - Value* X_rd_val = this->gen_ext( + Value* Xtmp0_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 8/8), 32, true); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 10); @@ -876,11 +871,11 @@ private: this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(32U, fld_imm_val)); if(fld_rd_val != 0){ - Value* X_rd_val = this->gen_ext( + Value* Xtmp0_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 16/8), 32, true); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 11); @@ -917,11 +912,11 @@ private: this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(32U, fld_imm_val)); if(fld_rd_val != 0){ - Value* X_rd_val = this->gen_ext( + Value* Xtmp0_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 32/8), 32, true); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 12); @@ -958,11 +953,11 @@ private: this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(32U, fld_imm_val)); if(fld_rd_val != 0){ - Value* X_rd_val = this->gen_ext( + Value* Xtmp0_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 8/8), 32, false); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 13); @@ -999,11 +994,11 @@ private: this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(32U, fld_imm_val)); if(fld_rd_val != 0){ - Value* X_rd_val = this->gen_ext( + Value* Xtmp0_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 16/8), 32, false); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 14); @@ -1039,11 +1034,11 @@ private: Value* offs_val = this->builder.CreateAdd( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(32U, fld_imm_val)); - Value* MEM_offs_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); + Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(8))); + this->builder.CreateZExtOrTrunc(MEMtmp0_val,this->get_type(8))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 15); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -1078,11 +1073,11 @@ private: Value* offs_val = this->builder.CreateAdd( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(32U, fld_imm_val)); - Value* MEM_offs_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); + Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(16))); + this->builder.CreateZExtOrTrunc(MEMtmp0_val,this->get_type(16))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 16); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -1117,11 +1112,11 @@ private: Value* offs_val = this->builder.CreateAdd( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(32U, fld_imm_val)); - Value* MEM_offs_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); + Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); + this->builder.CreateZExtOrTrunc(MEMtmp0_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 17); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -1154,10 +1149,10 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateAdd( + Value* Xtmp0_val = this->builder.CreateAdd( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(32U, fld_imm_val)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 18); @@ -1191,7 +1186,7 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->gen_choose( + Value* Xtmp0_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_SLT, this->gen_ext( @@ -1201,7 +1196,7 @@ private: this->gen_const(32U, 1), this->gen_const(32U, 0), 32); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 19); @@ -1236,7 +1231,7 @@ private: int32_t full_imm_val = fld_imm_val; if(fld_rd_val != 0){ - Value* X_rd_val = this->gen_choose( + Value* Xtmp0_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_ULT, this->gen_reg_load(fld_rs1_val + traits::X0, 0), @@ -1244,7 +1239,7 @@ private: this->gen_const(32U, 1), this->gen_const(32U, 0), 32); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 20); @@ -1278,10 +1273,10 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateXor( + Value* Xtmp0_val = this->builder.CreateXor( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(32U, fld_imm_val)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 21); @@ -1315,10 +1310,10 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateOr( + Value* Xtmp0_val = this->builder.CreateOr( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(32U, fld_imm_val)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 22); @@ -1352,10 +1347,10 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateAnd( + Value* Xtmp0_val = this->builder.CreateAnd( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(32U, fld_imm_val)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 23); @@ -1392,10 +1387,10 @@ private: this->gen_raise_trap(0, 0); } else { if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateShl( + Value* Xtmp0_val = this->builder.CreateShl( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(32U, fld_shamt_val)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } } this->gen_set_pc(pc, traits::NEXT_PC); @@ -1433,10 +1428,10 @@ private: this->gen_raise_trap(0, 0); } else { if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateLShr( + Value* Xtmp0_val = this->builder.CreateLShr( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(32U, fld_shamt_val)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } } this->gen_set_pc(pc, traits::NEXT_PC); @@ -1474,10 +1469,10 @@ private: this->gen_raise_trap(0, 0); } else { if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateAShr( + Value* Xtmp0_val = this->builder.CreateAShr( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(32U, fld_shamt_val)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } } this->gen_set_pc(pc, traits::NEXT_PC); @@ -1512,10 +1507,10 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateAdd( + Value* Xtmp0_val = this->builder.CreateAdd( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_reg_load(fld_rs2_val + traits::X0, 0)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 27); @@ -1549,10 +1544,10 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateSub( + Value* Xtmp0_val = this->builder.CreateSub( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_reg_load(fld_rs2_val + traits::X0, 0)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 28); @@ -1586,12 +1581,12 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateShl( + Value* Xtmp0_val = this->builder.CreateShl( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->builder.CreateAnd( this->gen_reg_load(fld_rs2_val + traits::X0, 0), - this->gen_const(32U, 31))); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_const(32U, 0x1f))); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 29); @@ -1625,7 +1620,7 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->gen_choose( + Value* Xtmp0_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_SLT, this->gen_ext( @@ -1637,7 +1632,7 @@ private: this->gen_const(32U, 1), this->gen_const(32U, 0), 32); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 30); @@ -1671,7 +1666,7 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->gen_choose( + Value* Xtmp0_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_ULT, this->gen_ext( @@ -1685,7 +1680,7 @@ private: this->gen_const(32U, 1), this->gen_const(32U, 0), 32); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 31); @@ -1719,10 +1714,10 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateXor( + Value* Xtmp0_val = this->builder.CreateXor( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_reg_load(fld_rs2_val + traits::X0, 0)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 32); @@ -1756,12 +1751,12 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateLShr( + Value* Xtmp0_val = this->builder.CreateLShr( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->builder.CreateAnd( this->gen_reg_load(fld_rs2_val + traits::X0, 0), - this->gen_const(32U, 31))); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_const(32U, 0x1f))); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 33); @@ -1795,12 +1790,12 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateAShr( + Value* Xtmp0_val = this->builder.CreateAShr( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->builder.CreateAnd( this->gen_reg_load(fld_rs2_val + traits::X0, 0), - this->gen_const(32U, 31))); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_const(32U, 0x1f))); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 34); @@ -1834,10 +1829,10 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateOr( + Value* Xtmp0_val = this->builder.CreateOr( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_reg_load(fld_rs2_val + traits::X0, 0)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 35); @@ -1871,10 +1866,10 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateAnd( + Value* Xtmp0_val = this->builder.CreateAnd( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_reg_load(fld_rs2_val + traits::X0, 0)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 36); @@ -1906,15 +1901,15 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* FENCE_fence_val = this->builder.CreateOr( + Value* FENCEtmp0_val = this->builder.CreateOr( this->builder.CreateShl( this->gen_const(32U, fld_pred_val), this->gen_const(32U, 4)), this->gen_const(32U, fld_succ_val)); this->gen_write_mem( traits::FENCE, - (uint64_t)0, - this->builder.CreateZExtOrTrunc(FENCE_fence_val,this->get_type(32))); + this->gen_const(64U, 0), + this->builder.CreateZExtOrTrunc(FENCEtmp0_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 37); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -1944,11 +1939,11 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* FENCE_fencei_val = this->gen_const(32U, fld_imm_val); + Value* FENCEtmp0_val = this->gen_const(32U, fld_imm_val); this->gen_write_mem( traits::FENCE, - (uint64_t)1, - this->builder.CreateZExtOrTrunc(FENCE_fencei_val,this->get_type(32))); + this->gen_const(64U, 1), + this->builder.CreateZExtOrTrunc(FENCEtmp0_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 38); this->gen_trap_check(this->leave_blk); @@ -2134,16 +2129,16 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* FENCE_fencevmal_val = this->gen_const(32U, fld_rs1_val); + Value* FENCEtmp0_val = this->gen_const(32U, fld_rs1_val); this->gen_write_mem( traits::FENCE, - (uint64_t)2, - this->builder.CreateZExtOrTrunc(FENCE_fencevmal_val,this->get_type(32))); - Value* FENCE_fencevmau_val = this->gen_const(32U, fld_rs2_val); + this->gen_const(64U, 2), + this->builder.CreateZExtOrTrunc(FENCEtmp0_val,this->get_type(32))); + Value* FENCEtmp1_val = this->gen_const(32U, fld_rs2_val); this->gen_write_mem( traits::FENCE, - (uint64_t)3, - this->builder.CreateZExtOrTrunc(FENCE_fencevmau_val,this->get_type(32))); + this->gen_const(64U, 3), + this->builder.CreateZExtOrTrunc(FENCEtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 45); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -2177,20 +2172,20 @@ private: Value* rs_val_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); if(fld_rd_val != 0){ - Value* csr_val_val = this->gen_read_mem(traits::CSR, fld_csr_val, 32/8); - Value* CSR_csr_val = rs_val_val; + Value* csr_val_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, fld_csr_val), 32/8); + Value* CSRtmp0_val = rs_val_val; this->gen_write_mem( traits::CSR, - fld_csr_val, - this->builder.CreateZExtOrTrunc(CSR_csr_val,this->get_type(32))); - Value* X_rd_val = csr_val_val; - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_const(16U, fld_csr_val), + this->builder.CreateZExtOrTrunc(CSRtmp0_val,this->get_type(32))); + Value* Xtmp1_val = csr_val_val; + this->builder.CreateStore(Xtmp1_val, get_reg_ptr(fld_rd_val + traits::X0), false); } else { - Value* CSR_csr_val = rs_val_val; + Value* CSRtmp2_val = rs_val_val; this->gen_write_mem( traits::CSR, - fld_csr_val, - this->builder.CreateZExtOrTrunc(CSR_csr_val,this->get_type(32))); + this->gen_const(16U, fld_csr_val), + this->builder.CreateZExtOrTrunc(CSRtmp2_val,this->get_type(32))); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 46); @@ -2223,20 +2218,20 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* xrd_val = this->gen_read_mem(traits::CSR, fld_csr_val, 32/8); + Value* xrd_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, fld_csr_val), 32/8); Value* xrs1_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); if(fld_rd_val != 0){ - Value* X_rd_val = xrd_val; - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = xrd_val; + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } if(fld_rs1_val != 0){ - Value* CSR_csr_val = this->builder.CreateOr( + Value* CSRtmp1_val = this->builder.CreateOr( xrd_val, xrs1_val); this->gen_write_mem( traits::CSR, - fld_csr_val, - this->builder.CreateZExtOrTrunc(CSR_csr_val,this->get_type(32))); + this->gen_const(16U, fld_csr_val), + this->builder.CreateZExtOrTrunc(CSRtmp1_val,this->get_type(32))); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 47); @@ -2269,20 +2264,20 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* xrd_val = this->gen_read_mem(traits::CSR, fld_csr_val, 32/8); + Value* xrd_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, fld_csr_val), 32/8); Value* xrs1_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); if(fld_rd_val != 0){ - Value* X_rd_val = xrd_val; - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = xrd_val; + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } if(fld_rs1_val != 0){ - Value* CSR_csr_val = this->builder.CreateAnd( + Value* CSRtmp1_val = this->builder.CreateAnd( xrd_val, this->builder.CreateNot(xrs1_val)); this->gen_write_mem( traits::CSR, - fld_csr_val, - this->builder.CreateZExtOrTrunc(CSR_csr_val,this->get_type(32))); + this->gen_const(16U, fld_csr_val), + this->builder.CreateZExtOrTrunc(CSRtmp1_val,this->get_type(32))); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 48); @@ -2316,17 +2311,17 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->gen_read_mem(traits::CSR, fld_csr_val, 32/8); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, fld_csr_val), 32/8); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } - Value* CSR_csr_val = this->gen_ext( + Value* CSRtmp1_val = this->gen_ext( this->gen_const(32U, fld_zimm_val), 32, false); this->gen_write_mem( traits::CSR, - fld_csr_val, - this->builder.CreateZExtOrTrunc(CSR_csr_val,this->get_type(32))); + this->gen_const(16U, fld_csr_val), + this->builder.CreateZExtOrTrunc(CSRtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 49); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -2358,9 +2353,9 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* res_val = this->gen_read_mem(traits::CSR, fld_csr_val, 32/8); + Value* res_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, fld_csr_val), 32/8); if(fld_zimm_val != 0){ - Value* CSR_csr_val = this->builder.CreateOr( + Value* CSRtmp0_val = this->builder.CreateOr( res_val, this->gen_ext( this->gen_const(32U, fld_zimm_val), @@ -2368,12 +2363,12 @@ private: false)); this->gen_write_mem( traits::CSR, - fld_csr_val, - this->builder.CreateZExtOrTrunc(CSR_csr_val,this->get_type(32))); + this->gen_const(16U, fld_csr_val), + this->builder.CreateZExtOrTrunc(CSRtmp0_val,this->get_type(32))); } if(fld_rd_val != 0){ - Value* X_rd_val = res_val; - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp1_val = res_val; + this->builder.CreateStore(Xtmp1_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 50); @@ -2406,13 +2401,13 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+4; - Value* res_val = this->gen_read_mem(traits::CSR, fld_csr_val, 32/8); + Value* res_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, fld_csr_val), 32/8); if(fld_rd_val != 0){ - Value* X_rd_val = res_val; - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = res_val; + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } if(fld_zimm_val != 0){ - Value* CSR_csr_val = this->builder.CreateAnd( + Value* CSRtmp1_val = this->builder.CreateAnd( res_val, this->builder.CreateNot(this->gen_ext( this->gen_const(32U, fld_zimm_val), @@ -2420,8 +2415,8 @@ private: false))); this->gen_write_mem( traits::CSR, - fld_csr_val, - this->builder.CreateZExtOrTrunc(CSR_csr_val,this->get_type(32))); + this->gen_const(16U, fld_csr_val), + this->builder.CreateZExtOrTrunc(CSRtmp1_val,this->get_type(32))); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 51); @@ -2464,11 +2459,11 @@ private: this->gen_reg_load(fld_rs2_val + traits::X0, 0), 128, false)); - Value* X_rd_val = this->gen_ext( + Value* Xtmp0_val = this->gen_ext( res_val, 32, false); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 52); @@ -2511,13 +2506,13 @@ private: this->gen_reg_load(fld_rs2_val + traits::X0, 0), 128, true)); - Value* X_rd_val = this->gen_ext( + Value* Xtmp0_val = this->gen_ext( this->builder.CreateLShr( res_val, this->gen_const(32U, 32)), 32, false); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 53); @@ -2560,13 +2555,13 @@ private: this->gen_reg_load(fld_rs2_val + traits::X0, 0), 128, false)); - Value* X_rd_val = this->gen_ext( + Value* Xtmp0_val = this->gen_ext( this->builder.CreateLShr( res_val, this->gen_const(32U, 32)), 32, false); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 54); @@ -2609,13 +2604,13 @@ private: this->gen_reg_load(fld_rs2_val + traits::X0, 0), 128, false)); - Value* X_rd_val = this->gen_ext( + Value* Xtmp0_val = this->gen_ext( this->builder.CreateLShr( res_val, this->gen_const(32U, 32)), 32, false); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 55); @@ -2649,95 +2644,101 @@ private: pc=pc+4; if(fld_rd_val != 0){ - llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); - llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); - llvm::BasicBlock* bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); - // this->builder.SetInsertPoint(bb); - this->gen_cond_branch(this->builder.CreateICmp( - ICmpInst::ICMP_NE, - this->gen_reg_load(fld_rs2_val + traits::X0, 0), - this->gen_const(32U, 0)), - bb_then, - bb_else); - this->builder.SetInsertPoint(bb_then); { - uint32_t M1_val = (-1); - uint32_t MMIN_val = (-1) << (32 - 1); llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); llvm::BasicBlock* bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); // this->builder.SetInsertPoint(bb); this->gen_cond_branch(this->builder.CreateICmp( - ICmpInst::ICMP_EQ, - this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 1), - 32, true), - this->gen_ext( - this->gen_const(32U, MMIN_val), - 32, true)), + ICmpInst::ICMP_NE, + this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_const(32U, 0)), bb_then, bb_else); this->builder.SetInsertPoint(bb_then); { - llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); - llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); - llvm::BasicBlock* bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); - // this->builder.SetInsertPoint(bb); - this->gen_cond_branch(this->builder.CreateICmp( - ICmpInst::ICMP_EQ, - this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 2), - 32, true), - this->gen_ext( - this->gen_const(32U, M1_val), - 32, true)), - bb_then, - bb_else); - this->builder.SetInsertPoint(bb_then); + int32_t M1_val = (-1); + uint32_t MMIN_val = (-1) << (32 - 1); { - Value* X_rd_val = this->gen_const(32U, MMIN_val); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); - } - this->builder.CreateBr(bbnext); - this->builder.SetInsertPoint(bb_else); - { - Value* X_rd_val = this->builder.CreateSDiv( + llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); + llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); + llvm::BasicBlock* bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); + // this->builder.SetInsertPoint(bb); + this->gen_cond_branch(this->builder.CreateICmp( + ICmpInst::ICMP_EQ, this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 3), + this->gen_reg_load(fld_rs1_val + traits::X0, 1), 32, true), this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 3), - 32, true)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_const(32U, MMIN_val), + 32, true)), + bb_then, + bb_else); + this->builder.SetInsertPoint(bb_then); + { + { + llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); + llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); + llvm::BasicBlock* bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); + // this->builder.SetInsertPoint(bb); + this->gen_cond_branch(this->builder.CreateICmp( + ICmpInst::ICMP_EQ, + this->gen_ext( + this->gen_reg_load(fld_rs2_val + traits::X0, 2), + 32, true), + this->gen_ext( + this->gen_const(32U, M1_val), + 32, true)), + bb_then, + bb_else); + this->builder.SetInsertPoint(bb_then); + { + Value* Xtmp0_val = this->gen_const(32U, MMIN_val); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + } + this->builder.CreateBr(bbnext); + this->builder.SetInsertPoint(bb_else); + { + Value* Xtmp1_val = this->builder.CreateSDiv( + this->gen_ext( + this->gen_reg_load(fld_rs1_val + traits::X0, 3), + 32, true), + this->gen_ext( + this->gen_reg_load(fld_rs2_val + traits::X0, 3), + 32, true)); + this->builder.CreateStore(Xtmp1_val, get_reg_ptr(fld_rd_val + traits::X0), false); + } + this->builder.CreateBr(bbnext); + bb=bbnext; + } + this->builder.SetInsertPoint(bb); + } + this->builder.CreateBr(bbnext); + this->builder.SetInsertPoint(bb_else); + { + Value* Xtmp2_val = this->builder.CreateSDiv( + this->gen_ext( + this->gen_reg_load(fld_rs1_val + traits::X0, 2), + 32, true), + this->gen_ext( + this->gen_reg_load(fld_rs2_val + traits::X0, 2), + 32, true)); + this->builder.CreateStore(Xtmp2_val, get_reg_ptr(fld_rd_val + traits::X0), false); + } + this->builder.CreateBr(bbnext); + bb=bbnext; } - this->builder.CreateBr(bbnext); - bb=bbnext; this->builder.SetInsertPoint(bb); } this->builder.CreateBr(bbnext); this->builder.SetInsertPoint(bb_else); { - Value* X_rd_val = this->builder.CreateSDiv( - this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 2), - 32, true), - this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 2), - 32, true)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp3_val = this->builder.CreateNeg(this->gen_const(32U, 1)); + this->builder.CreateStore(Xtmp3_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->builder.CreateBr(bbnext); bb=bbnext; - this->builder.SetInsertPoint(bb); } - this->builder.CreateBr(bbnext); - this->builder.SetInsertPoint(bb_else); - { - Value* X_rd_val = this->builder.CreateNeg(this->gen_const(32U, 1)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); - } - this->builder.CreateBr(bbnext); - bb=bbnext; this->builder.SetInsertPoint(bb); } this->gen_set_pc(pc, traits::NEXT_PC); @@ -2772,37 +2773,39 @@ private: pc=pc+4; if(fld_rd_val != 0){ - llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); - llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); - llvm::BasicBlock* bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); - // this->builder.SetInsertPoint(bb); - this->gen_cond_branch(this->builder.CreateICmp( - ICmpInst::ICMP_NE, - this->gen_reg_load(fld_rs2_val + traits::X0, 0), - this->gen_const(32U, 0)), - bb_then, - bb_else); - this->builder.SetInsertPoint(bb_then); { - Value* X_rd_val = this->builder.CreateUDiv( - this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 1), - 32, - false), - this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 1), - 32, - false)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); + llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); + llvm::BasicBlock* bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); + // this->builder.SetInsertPoint(bb); + this->gen_cond_branch(this->builder.CreateICmp( + ICmpInst::ICMP_NE, + this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_const(32U, 0)), + bb_then, + bb_else); + this->builder.SetInsertPoint(bb_then); + { + Value* Xtmp0_val = this->builder.CreateUDiv( + this->gen_ext( + this->gen_reg_load(fld_rs1_val + traits::X0, 1), + 32, + false), + this->gen_ext( + this->gen_reg_load(fld_rs2_val + traits::X0, 1), + 32, + false)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + } + this->builder.CreateBr(bbnext); + this->builder.SetInsertPoint(bb_else); + { + Value* Xtmp1_val = this->builder.CreateNeg(this->gen_const(32U, 1)); + this->builder.CreateStore(Xtmp1_val, get_reg_ptr(fld_rd_val + traits::X0), false); + } + this->builder.CreateBr(bbnext); + bb=bbnext; } - this->builder.CreateBr(bbnext); - this->builder.SetInsertPoint(bb_else); - { - Value* X_rd_val = this->builder.CreateNeg(this->gen_const(32U, 1)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); - } - this->builder.CreateBr(bbnext); - bb=bbnext; this->builder.SetInsertPoint(bb); } this->gen_set_pc(pc, traits::NEXT_PC); @@ -2837,99 +2840,105 @@ private: pc=pc+4; if(fld_rd_val != 0){ - llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); - llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); - llvm::BasicBlock* bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); - // this->builder.SetInsertPoint(bb); - this->gen_cond_branch(this->builder.CreateICmp( - ICmpInst::ICMP_NE, - this->gen_reg_load(fld_rs2_val + traits::X0, 0), - this->gen_const(32U, 0)), - bb_then, - bb_else); - this->builder.SetInsertPoint(bb_then); { - uint32_t M1_val = (-1); - uint32_t MMIN_val = (-1) << (32 - 1); llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); llvm::BasicBlock* bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); // this->builder.SetInsertPoint(bb); this->gen_cond_branch(this->builder.CreateICmp( - ICmpInst::ICMP_EQ, - this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 1), - 32, true), - this->gen_ext( - this->gen_const(32U, MMIN_val), - 32, true)), + ICmpInst::ICMP_NE, + this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_const(32U, 0)), bb_then, bb_else); this->builder.SetInsertPoint(bb_then); { - llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); - llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); - llvm::BasicBlock* bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); - // this->builder.SetInsertPoint(bb); - this->gen_cond_branch(this->builder.CreateICmp( - ICmpInst::ICMP_EQ, - this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 2), - 32, true), - this->gen_ext( - this->gen_const(32U, M1_val), - 32, true)), - bb_then, - bb_else); - this->builder.SetInsertPoint(bb_then); + int32_t M1_val = (-1); + uint32_t MMIN_val = (-1) << (32 - 1); { - Value* X_rd_val = this->gen_const(32U, 0); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); - } - this->builder.CreateBr(bbnext); - this->builder.SetInsertPoint(bb_else); - { - Value* X_rd_val = this->builder.CreateSRem( + llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); + llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); + llvm::BasicBlock* bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); + // this->builder.SetInsertPoint(bb); + this->gen_cond_branch(this->builder.CreateICmp( + ICmpInst::ICMP_EQ, this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 3), - 32, - true), + this->gen_reg_load(fld_rs1_val + traits::X0, 1), + 32, true), this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 3), - 32, - true)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_const(32U, MMIN_val), + 32, true)), + bb_then, + bb_else); + this->builder.SetInsertPoint(bb_then); + { + { + llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); + llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); + llvm::BasicBlock* bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); + // this->builder.SetInsertPoint(bb); + this->gen_cond_branch(this->builder.CreateICmp( + ICmpInst::ICMP_EQ, + this->gen_ext( + this->gen_reg_load(fld_rs2_val + traits::X0, 2), + 32, true), + this->gen_ext( + this->gen_const(32U, M1_val), + 32, true)), + bb_then, + bb_else); + this->builder.SetInsertPoint(bb_then); + { + Value* Xtmp0_val = this->gen_const(32U, 0); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + } + this->builder.CreateBr(bbnext); + this->builder.SetInsertPoint(bb_else); + { + Value* Xtmp1_val = this->builder.CreateSRem( + this->gen_ext( + this->gen_reg_load(fld_rs1_val + traits::X0, 3), + 32, + true), + this->gen_ext( + this->gen_reg_load(fld_rs2_val + traits::X0, 3), + 32, + true)); + this->builder.CreateStore(Xtmp1_val, get_reg_ptr(fld_rd_val + traits::X0), false); + } + this->builder.CreateBr(bbnext); + bb=bbnext; + } + this->builder.SetInsertPoint(bb); + } + this->builder.CreateBr(bbnext); + this->builder.SetInsertPoint(bb_else); + { + Value* Xtmp2_val = this->builder.CreateSRem( + this->gen_ext( + this->gen_reg_load(fld_rs1_val + traits::X0, 2), + 32, + true), + this->gen_ext( + this->gen_reg_load(fld_rs2_val + traits::X0, 2), + 32, + true)); + this->builder.CreateStore(Xtmp2_val, get_reg_ptr(fld_rd_val + traits::X0), false); + } + this->builder.CreateBr(bbnext); + bb=bbnext; } - this->builder.CreateBr(bbnext); - bb=bbnext; this->builder.SetInsertPoint(bb); } this->builder.CreateBr(bbnext); this->builder.SetInsertPoint(bb_else); { - Value* X_rd_val = this->builder.CreateSRem( - this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 2), - 32, - true), - this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 2), - 32, - true)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp3_val = this->gen_reg_load(fld_rs1_val + traits::X0, 1); + this->builder.CreateStore(Xtmp3_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->builder.CreateBr(bbnext); bb=bbnext; - this->builder.SetInsertPoint(bb); } - this->builder.CreateBr(bbnext); - this->builder.SetInsertPoint(bb_else); - { - Value* X_rd_val = this->gen_reg_load(fld_rs1_val + traits::X0, 1); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); - } - this->builder.CreateBr(bbnext); - bb=bbnext; this->builder.SetInsertPoint(bb); } this->gen_set_pc(pc, traits::NEXT_PC); @@ -2964,37 +2973,39 @@ private: pc=pc+4; if(fld_rd_val != 0){ - llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); - llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); - llvm::BasicBlock* bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); - // this->builder.SetInsertPoint(bb); - this->gen_cond_branch(this->builder.CreateICmp( - ICmpInst::ICMP_NE, - this->gen_reg_load(fld_rs2_val + traits::X0, 0), - this->gen_const(32U, 0)), - bb_then, - bb_else); - this->builder.SetInsertPoint(bb_then); { - Value* X_rd_val = this->builder.CreateURem( - this->gen_ext( - this->gen_reg_load(fld_rs1_val + traits::X0, 1), - 32, - false), - this->gen_ext( - this->gen_reg_load(fld_rs2_val + traits::X0, 1), - 32, - false)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); + llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); + llvm::BasicBlock* bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); + // this->builder.SetInsertPoint(bb); + this->gen_cond_branch(this->builder.CreateICmp( + ICmpInst::ICMP_NE, + this->gen_reg_load(fld_rs2_val + traits::X0, 0), + this->gen_const(32U, 0)), + bb_then, + bb_else); + this->builder.SetInsertPoint(bb_then); + { + Value* Xtmp0_val = this->builder.CreateURem( + this->gen_ext( + this->gen_reg_load(fld_rs1_val + traits::X0, 1), + 32, + false), + this->gen_ext( + this->gen_reg_load(fld_rs2_val + traits::X0, 1), + 32, + false)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + } + this->builder.CreateBr(bbnext); + this->builder.SetInsertPoint(bb_else); + { + Value* Xtmp1_val = this->gen_reg_load(fld_rs1_val + traits::X0, 1); + this->builder.CreateStore(Xtmp1_val, get_reg_ptr(fld_rd_val + traits::X0), false); + } + this->builder.CreateBr(bbnext); + bb=bbnext; } - this->builder.CreateBr(bbnext); - this->builder.SetInsertPoint(bb_else); - { - Value* X_rd_val = this->gen_reg_load(fld_rs1_val + traits::X0, 1); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); - } - this->builder.CreateBr(bbnext); - bb=bbnext; this->builder.SetInsertPoint(bb); } this->gen_set_pc(pc, traits::NEXT_PC); @@ -3031,19 +3042,19 @@ private: if(fld_rd_val != 0){ Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); - Value* X_rd_val = this->gen_ext( + Value* Xtmp0_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 32/8), 32, true); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); - Value* RES_offs_val = this->gen_ext( + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* REStmp1_val = this->gen_ext( this->builder.CreateNeg(this->gen_const(8U, 1)), 32, true); this->gen_write_mem( traits::RES, offs_val, - this->builder.CreateZExtOrTrunc(RES_offs_val,this->get_type(32))); + this->builder.CreateZExtOrTrunc(REStmp1_val,this->get_type(32))); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 60); @@ -3080,28 +3091,30 @@ private: Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); Value* res1_val = this->gen_read_mem(traits::RES, offs_val, 32/8); - llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); - llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); - // this->builder.SetInsertPoint(bb); - this->gen_cond_branch(this->builder.CreateICmp( - ICmpInst::ICMP_NE, - res1_val, - this->gen_const(32U, 0)), - bb_then, - bbnext); - this->builder.SetInsertPoint(bb_then); { - Value* MEM_offs_val = this->gen_reg_load(fld_rs2_val + traits::X0, 1); - this->gen_write_mem( - traits::MEM, - offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); + llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); + llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); + // this->builder.SetInsertPoint(bb); + this->gen_cond_branch(this->builder.CreateICmp( + ICmpInst::ICMP_NE, + res1_val, + this->gen_const(32U, 0)), + bb_then, + bbnext); + this->builder.SetInsertPoint(bb_then); + { + Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits::X0, 1); + this->gen_write_mem( + traits::MEM, + offs_val, + this->builder.CreateZExtOrTrunc(MEMtmp0_val,this->get_type(32))); + } + this->builder.CreateBr(bbnext); + bb=bbnext; } - this->builder.CreateBr(bbnext); - bb=bbnext; this->builder.SetInsertPoint(bb); if(fld_rd_val != 0){ - Value* X_rd_val = this->gen_choose( + Value* Xtmp1_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_NE, res1_val, @@ -3109,7 +3122,7 @@ private: this->gen_const(32U, 0), this->gen_const(32U, 1), 32); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp1_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 61); @@ -3146,17 +3159,17 @@ private: Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); if(fld_rd_val != 0){ - Value* X_rd_val = this->gen_ext( + Value* Xtmp0_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 32/8), 32, true); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } - Value* MEM_offs_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); + Value* MEMtmp1_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); + this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 62); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -3196,17 +3209,17 @@ private: 32, true); if(fld_rd_val != 0){ - Value* X_rd_val = res1_val; - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = res1_val; + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } Value* res2_val = this->builder.CreateAdd( res1_val, this->gen_reg_load(fld_rs2_val + traits::X0, 0)); - Value* MEM_offs_val = res2_val; + Value* MEMtmp1_val = res2_val; this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); + this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 63); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -3246,17 +3259,17 @@ private: 32, true); if(fld_rd_val != 0){ - Value* X_rd_val = res1_val; - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = res1_val; + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } Value* res2_val = this->builder.CreateXor( res1_val, this->gen_reg_load(fld_rs2_val + traits::X0, 0)); - Value* MEM_offs_val = res2_val; + Value* MEMtmp1_val = res2_val; this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); + this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 64); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -3296,17 +3309,17 @@ private: 32, true); if(fld_rd_val != 0){ - Value* X_rd_val = res1_val; - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = res1_val; + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } Value* res2_val = this->builder.CreateAnd( res1_val, this->gen_reg_load(fld_rs2_val + traits::X0, 0)); - Value* MEM_offs_val = res2_val; + Value* MEMtmp1_val = res2_val; this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); + this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 65); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -3346,17 +3359,17 @@ private: 32, true); if(fld_rd_val != 0){ - Value* X_rd_val = res1_val; - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = res1_val; + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } Value* res2_val = this->builder.CreateOr( res1_val, this->gen_reg_load(fld_rs2_val + traits::X0, 0)); - Value* MEM_offs_val = res2_val; + Value* MEMtmp1_val = res2_val; this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); + this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 66); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -3396,8 +3409,8 @@ private: 32, true); if(fld_rd_val != 0){ - Value* X_rd_val = res1_val; - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = res1_val; + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } Value* res2_val = this->gen_choose( this->builder.CreateICmp( @@ -3411,11 +3424,11 @@ private: this->gen_reg_load(fld_rs2_val + traits::X0, 0), res1_val, 32); - Value* MEM_offs_val = res2_val; + Value* MEMtmp1_val = res2_val; this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); + this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 67); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -3455,8 +3468,8 @@ private: 32, true); if(fld_rd_val != 0){ - Value* X_rd_val = res1_val; - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = res1_val; + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } Value* res2_val = this->gen_choose( this->builder.CreateICmp( @@ -3470,11 +3483,11 @@ private: this->gen_reg_load(fld_rs2_val + traits::X0, 0), res1_val, 32); - Value* MEM_offs_val = res2_val; + Value* MEMtmp1_val = res2_val; this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); + this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 68); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -3514,8 +3527,8 @@ private: 32, false); if(fld_rd_val != 0){ - Value* X_rd_val = res1_val; - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = res1_val; + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } Value* res2_val = this->gen_choose( this->builder.CreateICmp( @@ -3525,11 +3538,11 @@ private: this->gen_reg_load(fld_rs2_val + traits::X0, 0), res1_val, 32); - Value* MEM_offs_val = res2_val; + Value* MEMtmp1_val = res2_val; this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); + this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 69); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -3569,8 +3582,8 @@ private: 32, false); if(fld_rd_val != 0){ - Value* X_rd_val = res1_val; - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = res1_val; + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } Value* res2_val = this->gen_choose( this->builder.CreateICmp( @@ -3580,11 +3593,11 @@ private: this->gen_reg_load(fld_rs2_val + traits::X0, 0), res1_val, 32); - Value* MEM_offs_val = res2_val; + Value* MEMtmp1_val = res2_val; this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); + this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 70); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -3618,12 +3631,10 @@ private: if(fld_imm_val == 0){ this->gen_raise_trap(0, 2); } - uint8_t rd_idx_val = (fld_rd_val + 8); - uint8_t x2_idx_val = 2; - Value* X_rd_idx_val = this->builder.CreateAdd( - this->gen_reg_load(x2_idx_val + traits::X0, 0), + Value* Xtmp0_val = this->builder.CreateAdd( + this->gen_reg_load(2 + traits::X0, 0), this->gen_const(32U, fld_imm_val)); - this->builder.CreateStore(X_rd_idx_val, get_reg_ptr(rd_idx_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr((fld_rd_val + 8) + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 71); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -3655,13 +3666,11 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - uint8_t rs1_idx_val = (fld_rs1_val + 8); - uint8_t rd_idx_val = (fld_rd_val + 8); Value* offs_val = this->builder.CreateAdd( - this->gen_reg_load(rs1_idx_val + traits::X0, 0), + this->gen_reg_load((fld_rs1_val + 8) + traits::X0, 0), this->gen_const(32U, fld_uimm_val)); - Value* X_rd_idx_val = this->gen_read_mem(traits::MEM, offs_val, 32/8); - this->builder.CreateStore(X_rd_idx_val, get_reg_ptr(rd_idx_val + traits::X0), false); + Value* Xtmp0_val = this->gen_read_mem(traits::MEM, offs_val, 32/8); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr((fld_rd_val + 8) + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 72); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -3693,16 +3702,14 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - uint8_t rs1_idx_val = (fld_rs1_val + 8); - uint8_t rs2_idx_val = (fld_rs2_val + 8); Value* offs_val = this->builder.CreateAdd( - this->gen_reg_load(rs1_idx_val + traits::X0, 0), + this->gen_reg_load((fld_rs1_val + 8) + traits::X0, 0), this->gen_const(32U, fld_uimm_val)); - Value* MEM_offs_val = this->gen_reg_load(rs2_idx_val + traits::X0, 0); + Value* MEMtmp0_val = this->gen_reg_load((fld_rs2_val + 8) + traits::X0, 0); this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); + this->builder.CreateZExtOrTrunc(MEMtmp0_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 73); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -3733,10 +3740,10 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - Value* X_rs1_val = this->builder.CreateAdd( + Value* Xtmp0_val = this->builder.CreateAdd( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(32U, fld_imm_val)); - this->builder.CreateStore(X_rs1_val, get_reg_ptr(fld_rs1_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rs1_val + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 74); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -3794,11 +3801,10 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - uint8_t rd_val = 1; - Value* X_rd_val = this->builder.CreateAdd( + Value* Xtmp0_val = this->builder.CreateAdd( cur_pc_val, this->gen_const(32U, 2)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(1 + traits::X0), false); Value* PC_val = this->builder.CreateAdd( cur_pc_val, this->gen_const(32U, fld_imm_val)); @@ -3834,8 +3840,8 @@ private: if(fld_rd_val == 0){ this->gen_raise_trap(0, 2); } - Value* X_rd_val = this->gen_const(32U, fld_imm_val); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = this->gen_const(32U, fld_imm_val); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 77); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -3872,8 +3878,8 @@ private: if(fld_imm_val == 0){ this->gen_raise_trap(0, 2); } - Value* X_rd_val = this->gen_const(32U, fld_imm_val); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = this->gen_const(32U, fld_imm_val); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 78); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -3903,13 +3909,12 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - uint8_t x2_idx_val = 2; - Value* X_x2_idx_val = this->builder.CreateAdd( + Value* Xtmp0_val = this->builder.CreateAdd( this->gen_ext( - this->gen_reg_load(x2_idx_val + traits::X0, 0), + this->gen_reg_load(2 + traits::X0, 0), 32, true), this->gen_const(32U, fld_imm_val)); - this->builder.CreateStore(X_x2_idx_val, get_reg_ptr(x2_idx_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(2 + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 79); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -3941,10 +3946,10 @@ private: pc=pc+2; uint8_t rs1_idx_val = (fld_rs1_val + 8); - Value* X_rs1_idx_val = this->builder.CreateLShr( + Value* Xtmp0_val = this->builder.CreateLShr( this->gen_reg_load(rs1_idx_val + traits::X0, 0), this->gen_const(32U, fld_shamt_val)); - this->builder.CreateStore(X_rs1_idx_val, get_reg_ptr(rs1_idx_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rs1_idx_val + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 80); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -3976,10 +3981,10 @@ private: pc=pc+2; uint8_t rs1_idx_val = (fld_rs1_val + 8); - Value* X_rs1_idx_val = this->builder.CreateAShr( + Value* Xtmp0_val = this->builder.CreateAShr( this->gen_reg_load(rs1_idx_val + traits::X0, 0), this->gen_const(32U, fld_shamt_val)); - this->builder.CreateStore(X_rs1_idx_val, get_reg_ptr(rs1_idx_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rs1_idx_val + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 81); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -4011,10 +4016,10 @@ private: pc=pc+2; uint8_t rs1_idx_val = (fld_rs1_val + 8); - Value* X_rs1_idx_val = this->builder.CreateAnd( + Value* Xtmp0_val = this->builder.CreateAnd( this->gen_reg_load(rs1_idx_val + traits::X0, 0), this->gen_const(32U, fld_imm_val)); - this->builder.CreateStore(X_rs1_idx_val, get_reg_ptr(rs1_idx_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rs1_idx_val + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 82); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -4046,11 +4051,10 @@ private: pc=pc+2; uint8_t rd_idx_val = (fld_rd_val + 8); - uint8_t rs2_idx_val = (fld_rs2_val + 8); - Value* X_rd_idx_val = this->builder.CreateSub( + Value* Xtmp0_val = this->builder.CreateSub( this->gen_reg_load(rd_idx_val + traits::X0, 0), - this->gen_reg_load(rs2_idx_val + traits::X0, 0)); - this->builder.CreateStore(X_rd_idx_val, get_reg_ptr(rd_idx_val + traits::X0), false); + this->gen_reg_load((fld_rs2_val + 8) + traits::X0, 0)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd_idx_val + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 83); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -4082,11 +4086,10 @@ private: pc=pc+2; uint8_t rd_idx_val = (fld_rd_val + 8); - uint8_t rs2_idx_val = (fld_rs2_val + 8); - Value* X_rd_idx_val = this->builder.CreateXor( + Value* Xtmp0_val = this->builder.CreateXor( this->gen_reg_load(rd_idx_val + traits::X0, 0), - this->gen_reg_load(rs2_idx_val + traits::X0, 0)); - this->builder.CreateStore(X_rd_idx_val, get_reg_ptr(rd_idx_val + traits::X0), false); + this->gen_reg_load((fld_rs2_val + 8) + traits::X0, 0)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd_idx_val + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 84); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -4118,11 +4121,10 @@ private: pc=pc+2; uint8_t rd_idx_val = (fld_rd_val + 8); - uint8_t rs2_idx_val = (fld_rs2_val + 8); - Value* X_rd_idx_val = this->builder.CreateOr( + Value* Xtmp0_val = this->builder.CreateOr( this->gen_reg_load(rd_idx_val + traits::X0, 0), - this->gen_reg_load(rs2_idx_val + traits::X0, 0)); - this->builder.CreateStore(X_rd_idx_val, get_reg_ptr(rd_idx_val + traits::X0), false); + this->gen_reg_load((fld_rs2_val + 8) + traits::X0, 0)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd_idx_val + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 85); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -4154,11 +4156,10 @@ private: pc=pc+2; uint8_t rd_idx_val = (fld_rd_val + 8); - uint8_t rs2_idx_val = (fld_rs2_val + 8); - Value* X_rd_idx_val = this->builder.CreateAnd( + Value* Xtmp0_val = this->builder.CreateAnd( this->gen_reg_load(rd_idx_val + traits::X0, 0), - this->gen_reg_load(rs2_idx_val + traits::X0, 0)); - this->builder.CreateStore(X_rd_idx_val, get_reg_ptr(rd_idx_val + traits::X0), false); + this->gen_reg_load((fld_rs2_val + 8) + traits::X0, 0)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(rd_idx_val + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 86); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -4220,11 +4221,10 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - uint8_t rs1_idx_val = (fld_rs1_val + 8); Value* PC_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_EQ, - this->gen_reg_load(rs1_idx_val + traits::X0, 0), + this->gen_reg_load((fld_rs1_val + 8) + traits::X0, 0), this->gen_const(32U, 0)), this->builder.CreateAdd( cur_pc_val, @@ -4262,11 +4262,10 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - uint8_t rs1_idx_val = (fld_rs1_val + 8); Value* PC_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_NE, - this->gen_reg_load(rs1_idx_val + traits::X0, 0), + this->gen_reg_load((fld_rs1_val + 8) + traits::X0, 0), this->gen_const(32U, 0)), this->builder.CreateAdd( cur_pc_val, @@ -4307,10 +4306,10 @@ private: if(fld_rs1_val == 0){ this->gen_raise_trap(0, 2); } - Value* X_rs1_val = this->builder.CreateShl( + Value* Xtmp0_val = this->builder.CreateShl( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(32U, fld_shamt_val)); - this->builder.CreateStore(X_rs1_val, get_reg_ptr(fld_rs1_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rs1_val + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 90); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -4341,12 +4340,11 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - uint8_t x2_idx_val = 2; Value* offs_val = this->builder.CreateAdd( - this->gen_reg_load(x2_idx_val + traits::X0, 0), + this->gen_reg_load(2 + traits::X0, 0), this->gen_const(32U, fld_uimm_val)); - Value* X_rd_val = this->gen_read_mem(traits::MEM, offs_val, 32/8); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = this->gen_read_mem(traits::MEM, offs_val, 32/8); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 91); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -4377,8 +4375,8 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - Value* X_rd_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 92); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -4438,10 +4436,10 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - Value* X_rd_val = this->builder.CreateAdd( + Value* Xtmp0_val = this->builder.CreateAdd( this->gen_reg_load(fld_rd_val + traits::X0, 0), this->gen_reg_load(fld_rs2_val + traits::X0, 0)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 94); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -4471,11 +4469,10 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - uint8_t r_idx_val = 1; - Value* X_r_idx_val = this->builder.CreateAdd( + Value* Xtmp0_val = this->builder.CreateAdd( cur_pc_val, this->gen_const(32U, 2)); - this->builder.CreateStore(X_r_idx_val, get_reg_ptr(r_idx_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(1 + traits::X0), false); Value* PC_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); this->builder.CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); this->gen_sync(iss::POST_SYNC, 95); @@ -4532,15 +4529,14 @@ private: Value* cur_pc_val = this->gen_const(32, pc.val); pc=pc+2; - uint8_t x2_idx_val = 2; Value* offs_val = this->builder.CreateAdd( - this->gen_reg_load(x2_idx_val + traits::X0, 0), + this->gen_reg_load(2 + traits::X0, 0), this->gen_const(32U, fld_uimm_val)); - Value* MEM_offs_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); + Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); + this->builder.CreateZExtOrTrunc(MEMtmp0_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 97); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -4695,16 +4691,7 @@ template inline void vm_impl::gen_trap_check(llvm::BasicBl bb, this->trap_blk, 1); } -template -inline llvm::Value* vm_impl::gen_fdispatch(std::string fname, const std::vector& args) { - return this->builder.CreateCall(this->mod->getFunction(fname), args); -} - -template -inline llvm::Value* vm_impl::gen_dispatch(std::string name, llvm::Value* val1, llvm::Value* val2, llvm::Value* val3) { -} - -} // namespace rv32imacf +} // namespace rv32imac template <> std::unique_ptr create(arch::rv32imac *core, unsigned short port, bool dump) { diff --git a/riscv/src/internal/vm_rv64ia.cpp b/riscv/src/internal/vm_rv64ia.cpp index b0329a5..fa79a0e 100644 --- a/riscv/src/internal/vm_rv64ia.cpp +++ b/riscv/src/internal/vm_rv64ia.cpp @@ -112,15 +112,10 @@ protected: void gen_trap_check(llvm::BasicBlock *bb); - inline llvm::Value *gen_reg_load(unsigned i, unsigned level = 0) { return this->builder.CreateLoad(get_reg_ptr(i), false); } - llvm::Value* gen_fdispatch(std::string fname, const std::vector& args); - - llvm::Value* gen_dispatch(std::string name, llvm::Value*, llvm::Value*, llvm::Value*); - inline void gen_set_pc(virt_addr_t pc, unsigned reg_num) { llvm::Value *next_pc_v = this->builder.CreateSExtOrTrunc(this->gen_const(traits::XLEN, pc.val), this->get_type(traits::XLEN)); @@ -399,11 +394,11 @@ private: this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(64U, fld_imm_val)); if(fld_rd_val != 0){ - Value* X_rd_val = this->gen_ext( + Value* Xtmp0_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 32/8), 64, false); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 0); @@ -440,11 +435,11 @@ private: this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(64U, fld_imm_val)); if(fld_rd_val != 0){ - Value* X_rd_val = this->gen_ext( + Value* Xtmp0_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 64/8), 64, true); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 1); @@ -480,11 +475,11 @@ private: Value* offs_val = this->builder.CreateAdd( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(64U, fld_imm_val)); - Value* MEM_offs_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); + Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(64))); + this->builder.CreateZExtOrTrunc(MEMtmp0_val,this->get_type(64))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 2); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -520,10 +515,10 @@ private: this->gen_raise_trap(0, 0); } else { if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateShl( + Value* Xtmp0_val = this->builder.CreateShl( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(64U, fld_shamt_val)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } } this->gen_set_pc(pc, traits::NEXT_PC); @@ -561,10 +556,10 @@ private: this->gen_raise_trap(0, 0); } else { if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateLShr( + Value* Xtmp0_val = this->builder.CreateLShr( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(64U, fld_shamt_val)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } } this->gen_set_pc(pc, traits::NEXT_PC); @@ -602,10 +597,10 @@ private: this->gen_raise_trap(0, 0); } else { if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateAShr( + Value* Xtmp0_val = this->builder.CreateAShr( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(64U, fld_shamt_val)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } } this->gen_set_pc(pc, traits::NEXT_PC); @@ -646,11 +641,11 @@ private: this-> get_type(32) ), this->gen_const(32U, fld_imm_val)); - Value* X_rd_val = this->gen_ext( + Value* Xtmp0_val = this->gen_ext( res_val, 64, true); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 6); @@ -690,11 +685,11 @@ private: this-> get_type(32) ), this->gen_const(32U, fld_shamt_val)); - Value* X_rd_val = this->gen_ext( + Value* Xtmp0_val = this->gen_ext( sh_val_val, 64, true); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 7); @@ -734,11 +729,11 @@ private: this-> get_type(32) ), this->gen_const(32U, fld_shamt_val)); - Value* X_rd_val = this->gen_ext( + Value* Xtmp0_val = this->gen_ext( sh_val_val, 64, true); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 8); @@ -778,11 +773,11 @@ private: this-> get_type(32) ), this->gen_const(32U, fld_shamt_val)); - Value* X_rd_val = this->gen_ext( + Value* Xtmp0_val = this->gen_ext( sh_val_val, 64, true); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 9); @@ -823,11 +818,11 @@ private: this->gen_reg_load(fld_rs2_val + traits::X0, 0), this-> get_type(32) )); - Value* X_rd_val = this->gen_ext( + Value* Xtmp0_val = this->gen_ext( res_val, 64, true); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 10); @@ -868,11 +863,11 @@ private: this->gen_reg_load(fld_rs2_val + traits::X0, 0), this-> get_type(32) )); - Value* X_rd_val = this->gen_ext( + Value* Xtmp0_val = this->gen_ext( res_val, 64, true); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 11); @@ -906,7 +901,7 @@ private: pc=pc+4; if(fld_rd_val != 0){ - uint32_t mask_val = 31; + int32_t mask_val = 0x1f; Value* count_val = this->builder.CreateAnd( this->builder.CreateTrunc( this->gen_reg_load(fld_rs2_val + traits::X0, 0), @@ -919,11 +914,11 @@ private: this-> get_type(32) ), count_val); - Value* X_rd_val = this->gen_ext( + Value* Xtmp0_val = this->gen_ext( sh_val_val, 64, true); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 12); @@ -957,7 +952,7 @@ private: pc=pc+4; if(fld_rd_val != 0){ - uint32_t mask_val = 31; + int32_t mask_val = 0x1f; Value* count_val = this->builder.CreateAnd( this->builder.CreateTrunc( this->gen_reg_load(fld_rs2_val + traits::X0, 0), @@ -970,11 +965,11 @@ private: this-> get_type(32) ), count_val); - Value* X_rd_val = this->gen_ext( + Value* Xtmp0_val = this->gen_ext( sh_val_val, 64, true); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 13); @@ -1008,7 +1003,7 @@ private: pc=pc+4; if(fld_rd_val != 0){ - uint32_t mask_val = 31; + int32_t mask_val = 0x1f; Value* count_val = this->builder.CreateAnd( this->builder.CreateTrunc( this->gen_reg_load(fld_rs2_val + traits::X0, 0), @@ -1021,11 +1016,11 @@ private: this-> get_type(32) ), count_val); - Value* X_rd_val = this->gen_ext( + Value* Xtmp0_val = this->gen_ext( sh_val_val, 64, true); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 14); @@ -1058,8 +1053,8 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->gen_const(64U, fld_imm_val); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = this->gen_const(64U, fld_imm_val); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 15); @@ -1092,10 +1087,10 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateAdd( + Value* Xtmp0_val = this->builder.CreateAdd( cur_pc_val, this->gen_const(64U, fld_imm_val)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 16); @@ -1128,10 +1123,10 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateAdd( + Value* Xtmp0_val = this->builder.CreateAdd( cur_pc_val, this->gen_const(64U, 4)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } Value* PC_val = this->builder.CreateAdd( cur_pc_val, @@ -1171,37 +1166,39 @@ private: this->gen_const(64U, fld_imm_val)); Value* align_val = this->builder.CreateAnd( new_pc_val, - this->gen_const(64U, 2)); - llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); - llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); - llvm::BasicBlock* bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); - // this->builder.SetInsertPoint(bb); - this->gen_cond_branch(this->builder.CreateICmp( - ICmpInst::ICMP_NE, - align_val, - this->gen_const(64U, 0)), - bb_then, - bb_else); - this->builder.SetInsertPoint(bb_then); + this->gen_const(64U, 0x2)); { - this->gen_raise_trap(0, 0); - } - this->builder.CreateBr(bbnext); - this->builder.SetInsertPoint(bb_else); - { - if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateAdd( - cur_pc_val, - this->gen_const(64U, 4)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); + llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); + llvm::BasicBlock* bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); + // this->builder.SetInsertPoint(bb); + this->gen_cond_branch(this->builder.CreateICmp( + ICmpInst::ICMP_NE, + align_val, + this->gen_const(64U, 0)), + bb_then, + bb_else); + this->builder.SetInsertPoint(bb_then); + { + this->gen_raise_trap(0, 0); } - Value* PC_val = this->builder.CreateAnd( - new_pc_val, - this->builder.CreateNot(this->gen_const(64U, 1))); - this->builder.CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); + this->builder.CreateBr(bbnext); + this->builder.SetInsertPoint(bb_else); + { + if(fld_rd_val != 0){ + Value* Xtmp0_val = this->builder.CreateAdd( + cur_pc_val, + this->gen_const(64U, 4)); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + } + Value* PC_val = this->builder.CreateAnd( + new_pc_val, + this->builder.CreateNot(this->gen_const(64U, 0x1))); + this->builder.CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); + } + this->builder.CreateBr(bbnext); + bb=bbnext; } - this->builder.CreateBr(bbnext); - bb=bbnext; this->builder.SetInsertPoint(bb); this->gen_sync(iss::POST_SYNC, 18); this->gen_trap_check(this->leave_blk); @@ -1496,11 +1493,11 @@ private: this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(64U, fld_imm_val)); if(fld_rd_val != 0){ - Value* X_rd_val = this->gen_ext( + Value* Xtmp0_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 8/8), 64, true); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 25); @@ -1537,11 +1534,11 @@ private: this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(64U, fld_imm_val)); if(fld_rd_val != 0){ - Value* X_rd_val = this->gen_ext( + Value* Xtmp0_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 16/8), 64, true); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 26); @@ -1578,11 +1575,11 @@ private: this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(64U, fld_imm_val)); if(fld_rd_val != 0){ - Value* X_rd_val = this->gen_ext( + Value* Xtmp0_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 32/8), 64, true); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 27); @@ -1619,11 +1616,11 @@ private: this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(64U, fld_imm_val)); if(fld_rd_val != 0){ - Value* X_rd_val = this->gen_ext( + Value* Xtmp0_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 8/8), 64, false); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 28); @@ -1660,11 +1657,11 @@ private: this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(64U, fld_imm_val)); if(fld_rd_val != 0){ - Value* X_rd_val = this->gen_ext( + Value* Xtmp0_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 16/8), 64, false); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 29); @@ -1700,11 +1697,11 @@ private: Value* offs_val = this->builder.CreateAdd( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(64U, fld_imm_val)); - Value* MEM_offs_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); + Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(8))); + this->builder.CreateZExtOrTrunc(MEMtmp0_val,this->get_type(8))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 30); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -1739,11 +1736,11 @@ private: Value* offs_val = this->builder.CreateAdd( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(64U, fld_imm_val)); - Value* MEM_offs_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); + Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(16))); + this->builder.CreateZExtOrTrunc(MEMtmp0_val,this->get_type(16))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 31); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -1778,11 +1775,11 @@ private: Value* offs_val = this->builder.CreateAdd( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(64U, fld_imm_val)); - Value* MEM_offs_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); + Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); + this->builder.CreateZExtOrTrunc(MEMtmp0_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 32); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -1815,10 +1812,10 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateAdd( + Value* Xtmp0_val = this->builder.CreateAdd( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(64U, fld_imm_val)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 33); @@ -1852,7 +1849,7 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->gen_choose( + Value* Xtmp0_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_SLT, this->gen_ext( @@ -1862,7 +1859,7 @@ private: this->gen_const(64U, 1), this->gen_const(64U, 0), 64); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 34); @@ -1897,7 +1894,7 @@ private: int64_t full_imm_val = fld_imm_val; if(fld_rd_val != 0){ - Value* X_rd_val = this->gen_choose( + Value* Xtmp0_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_ULT, this->gen_reg_load(fld_rs1_val + traits::X0, 0), @@ -1905,7 +1902,7 @@ private: this->gen_const(64U, 1), this->gen_const(64U, 0), 64); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 35); @@ -1939,10 +1936,10 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateXor( + Value* Xtmp0_val = this->builder.CreateXor( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(64U, fld_imm_val)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 36); @@ -1976,10 +1973,10 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateOr( + Value* Xtmp0_val = this->builder.CreateOr( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(64U, fld_imm_val)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 37); @@ -2013,10 +2010,10 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateAnd( + Value* Xtmp0_val = this->builder.CreateAnd( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_const(64U, fld_imm_val)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 38); @@ -2050,10 +2047,10 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateAdd( + Value* Xtmp0_val = this->builder.CreateAdd( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_reg_load(fld_rs2_val + traits::X0, 0)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 39); @@ -2087,10 +2084,10 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateSub( + Value* Xtmp0_val = this->builder.CreateSub( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_reg_load(fld_rs2_val + traits::X0, 0)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 40); @@ -2124,12 +2121,12 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateShl( + Value* Xtmp0_val = this->builder.CreateShl( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->builder.CreateAnd( this->gen_reg_load(fld_rs2_val + traits::X0, 0), - this->gen_const(64U, 31))); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_const(64U, 0x1f))); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 41); @@ -2163,7 +2160,7 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->gen_choose( + Value* Xtmp0_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_SLT, this->gen_ext( @@ -2175,7 +2172,7 @@ private: this->gen_const(64U, 1), this->gen_const(64U, 0), 64); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 42); @@ -2209,7 +2206,7 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->gen_choose( + Value* Xtmp0_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_ULT, this->gen_ext( @@ -2223,7 +2220,7 @@ private: this->gen_const(64U, 1), this->gen_const(64U, 0), 64); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 43); @@ -2257,10 +2254,10 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateXor( + Value* Xtmp0_val = this->builder.CreateXor( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_reg_load(fld_rs2_val + traits::X0, 0)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 44); @@ -2294,12 +2291,12 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateLShr( + Value* Xtmp0_val = this->builder.CreateLShr( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->builder.CreateAnd( this->gen_reg_load(fld_rs2_val + traits::X0, 0), - this->gen_const(64U, 31))); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_const(64U, 0x1f))); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 45); @@ -2333,12 +2330,12 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateAShr( + Value* Xtmp0_val = this->builder.CreateAShr( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->builder.CreateAnd( this->gen_reg_load(fld_rs2_val + traits::X0, 0), - this->gen_const(64U, 31))); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_const(64U, 0x1f))); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 46); @@ -2372,10 +2369,10 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateOr( + Value* Xtmp0_val = this->builder.CreateOr( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_reg_load(fld_rs2_val + traits::X0, 0)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 47); @@ -2409,10 +2406,10 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->builder.CreateAnd( + Value* Xtmp0_val = this->builder.CreateAnd( this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->gen_reg_load(fld_rs2_val + traits::X0, 0)); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 48); @@ -2444,15 +2441,15 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - Value* FENCE_fence_val = this->builder.CreateOr( + Value* FENCEtmp0_val = this->builder.CreateOr( this->builder.CreateShl( this->gen_const(64U, fld_pred_val), this->gen_const(64U, 4)), this->gen_const(64U, fld_succ_val)); this->gen_write_mem( traits::FENCE, - (uint64_t)0, - this->builder.CreateZExtOrTrunc(FENCE_fence_val,this->get_type(64))); + this->gen_const(64U, 0), + this->builder.CreateZExtOrTrunc(FENCEtmp0_val,this->get_type(64))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 49); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -2482,11 +2479,11 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - Value* FENCE_fencei_val = this->gen_const(64U, fld_imm_val); + Value* FENCEtmp0_val = this->gen_const(64U, fld_imm_val); this->gen_write_mem( traits::FENCE, - (uint64_t)1, - this->builder.CreateZExtOrTrunc(FENCE_fencei_val,this->get_type(64))); + this->gen_const(64U, 1), + this->builder.CreateZExtOrTrunc(FENCEtmp0_val,this->get_type(64))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 50); this->gen_trap_check(this->leave_blk); @@ -2672,16 +2669,16 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - Value* FENCE_fencevmal_val = this->gen_const(64U, fld_rs1_val); + Value* FENCEtmp0_val = this->gen_const(64U, fld_rs1_val); this->gen_write_mem( traits::FENCE, - (uint64_t)2, - this->builder.CreateZExtOrTrunc(FENCE_fencevmal_val,this->get_type(64))); - Value* FENCE_fencevmau_val = this->gen_const(64U, fld_rs2_val); + this->gen_const(64U, 2), + this->builder.CreateZExtOrTrunc(FENCEtmp0_val,this->get_type(64))); + Value* FENCEtmp1_val = this->gen_const(64U, fld_rs2_val); this->gen_write_mem( traits::FENCE, - (uint64_t)3, - this->builder.CreateZExtOrTrunc(FENCE_fencevmau_val,this->get_type(64))); + this->gen_const(64U, 3), + this->builder.CreateZExtOrTrunc(FENCEtmp1_val,this->get_type(64))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 57); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -2715,20 +2712,20 @@ private: Value* rs_val_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); if(fld_rd_val != 0){ - Value* csr_val_val = this->gen_read_mem(traits::CSR, fld_csr_val, 64/8); - Value* CSR_csr_val = rs_val_val; + Value* csr_val_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, fld_csr_val), 64/8); + Value* CSRtmp0_val = rs_val_val; this->gen_write_mem( traits::CSR, - fld_csr_val, - this->builder.CreateZExtOrTrunc(CSR_csr_val,this->get_type(64))); - Value* X_rd_val = csr_val_val; - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->gen_const(16U, fld_csr_val), + this->builder.CreateZExtOrTrunc(CSRtmp0_val,this->get_type(64))); + Value* Xtmp1_val = csr_val_val; + this->builder.CreateStore(Xtmp1_val, get_reg_ptr(fld_rd_val + traits::X0), false); } else { - Value* CSR_csr_val = rs_val_val; + Value* CSRtmp2_val = rs_val_val; this->gen_write_mem( traits::CSR, - fld_csr_val, - this->builder.CreateZExtOrTrunc(CSR_csr_val,this->get_type(64))); + this->gen_const(16U, fld_csr_val), + this->builder.CreateZExtOrTrunc(CSRtmp2_val,this->get_type(64))); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 58); @@ -2761,20 +2758,20 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - Value* xrd_val = this->gen_read_mem(traits::CSR, fld_csr_val, 64/8); + Value* xrd_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, fld_csr_val), 64/8); Value* xrs1_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); if(fld_rd_val != 0){ - Value* X_rd_val = xrd_val; - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = xrd_val; + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } if(fld_rs1_val != 0){ - Value* CSR_csr_val = this->builder.CreateOr( + Value* CSRtmp1_val = this->builder.CreateOr( xrd_val, xrs1_val); this->gen_write_mem( traits::CSR, - fld_csr_val, - this->builder.CreateZExtOrTrunc(CSR_csr_val,this->get_type(64))); + this->gen_const(16U, fld_csr_val), + this->builder.CreateZExtOrTrunc(CSRtmp1_val,this->get_type(64))); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 59); @@ -2807,20 +2804,20 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - Value* xrd_val = this->gen_read_mem(traits::CSR, fld_csr_val, 64/8); + Value* xrd_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, fld_csr_val), 64/8); Value* xrs1_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); if(fld_rd_val != 0){ - Value* X_rd_val = xrd_val; - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = xrd_val; + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } if(fld_rs1_val != 0){ - Value* CSR_csr_val = this->builder.CreateAnd( + Value* CSRtmp1_val = this->builder.CreateAnd( xrd_val, this->builder.CreateNot(xrs1_val)); this->gen_write_mem( traits::CSR, - fld_csr_val, - this->builder.CreateZExtOrTrunc(CSR_csr_val,this->get_type(64))); + this->gen_const(16U, fld_csr_val), + this->builder.CreateZExtOrTrunc(CSRtmp1_val,this->get_type(64))); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 60); @@ -2854,17 +2851,17 @@ private: pc=pc+4; if(fld_rd_val != 0){ - Value* X_rd_val = this->gen_read_mem(traits::CSR, fld_csr_val, 64/8); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, fld_csr_val), 64/8); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } - Value* CSR_csr_val = this->gen_ext( + Value* CSRtmp1_val = this->gen_ext( this->gen_const(64U, fld_zimm_val), 64, false); this->gen_write_mem( traits::CSR, - fld_csr_val, - this->builder.CreateZExtOrTrunc(CSR_csr_val,this->get_type(64))); + this->gen_const(16U, fld_csr_val), + this->builder.CreateZExtOrTrunc(CSRtmp1_val,this->get_type(64))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 61); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -2896,9 +2893,9 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - Value* res_val = this->gen_read_mem(traits::CSR, fld_csr_val, 64/8); + Value* res_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, fld_csr_val), 64/8); if(fld_zimm_val != 0){ - Value* CSR_csr_val = this->builder.CreateOr( + Value* CSRtmp0_val = this->builder.CreateOr( res_val, this->gen_ext( this->gen_const(64U, fld_zimm_val), @@ -2906,12 +2903,12 @@ private: false)); this->gen_write_mem( traits::CSR, - fld_csr_val, - this->builder.CreateZExtOrTrunc(CSR_csr_val,this->get_type(64))); + this->gen_const(16U, fld_csr_val), + this->builder.CreateZExtOrTrunc(CSRtmp0_val,this->get_type(64))); } if(fld_rd_val != 0){ - Value* X_rd_val = res_val; - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp1_val = res_val; + this->builder.CreateStore(Xtmp1_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 62); @@ -2944,13 +2941,13 @@ private: Value* cur_pc_val = this->gen_const(64, pc.val); pc=pc+4; - Value* res_val = this->gen_read_mem(traits::CSR, fld_csr_val, 64/8); + Value* res_val = this->gen_read_mem(traits::CSR, this->gen_const(16U, fld_csr_val), 64/8); if(fld_rd_val != 0){ - Value* X_rd_val = res_val; - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = res_val; + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } if(fld_zimm_val != 0){ - Value* CSR_csr_val = this->builder.CreateAnd( + Value* CSRtmp1_val = this->builder.CreateAnd( res_val, this->builder.CreateNot(this->gen_ext( this->gen_const(64U, fld_zimm_val), @@ -2958,8 +2955,8 @@ private: false))); this->gen_write_mem( traits::CSR, - fld_csr_val, - this->builder.CreateZExtOrTrunc(CSR_csr_val,this->get_type(64))); + this->gen_const(16U, fld_csr_val), + this->builder.CreateZExtOrTrunc(CSRtmp1_val,this->get_type(64))); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 63); @@ -2995,19 +2992,19 @@ private: if(fld_rd_val != 0){ Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); - Value* X_rd_val = this->gen_ext( + Value* Xtmp0_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 64/8), 64, true); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); - Value* RES_offs_val = this->gen_ext( + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* REStmp1_val = this->gen_ext( this->builder.CreateNeg(this->gen_const(8U, 1)), 64, true); this->gen_write_mem( traits::RES, offs_val, - this->builder.CreateZExtOrTrunc(RES_offs_val,this->get_type(64))); + this->builder.CreateZExtOrTrunc(REStmp1_val,this->get_type(64))); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 64); @@ -3044,37 +3041,39 @@ private: Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); Value* res_val = this->gen_read_mem(traits::RES, offs_val, 8/8); - llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); - llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); - llvm::BasicBlock* bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); - // this->builder.SetInsertPoint(bb); - this->gen_cond_branch(this->builder.CreateICmp( - ICmpInst::ICMP_NE, - res_val, - this->gen_const(64U, 0)), - bb_then, - bb_else); - this->builder.SetInsertPoint(bb_then); { - Value* MEM_offs_val = this->gen_reg_load(fld_rs2_val + traits::X0, 1); - this->gen_write_mem( - traits::MEM, - offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(64)));if(fld_rd_val != 0){ - Value* X_rd_val = this->gen_const(64U, 0); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); + llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); + llvm::BasicBlock* bb_else = llvm::BasicBlock::Create(this->mod->getContext(), "elsebr", this->func, bbnext); + // this->builder.SetInsertPoint(bb); + this->gen_cond_branch(this->builder.CreateICmp( + ICmpInst::ICMP_NE, + res_val, + this->gen_const(64U, 0)), + bb_then, + bb_else); + this->builder.SetInsertPoint(bb_then); + { + Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits::X0, 1); + this->gen_write_mem( + traits::MEM, + offs_val, + this->builder.CreateZExtOrTrunc(MEMtmp0_val,this->get_type(64)));if(fld_rd_val != 0){ + Value* Xtmp1_val = this->gen_const(64U, 0); + this->builder.CreateStore(Xtmp1_val, get_reg_ptr(fld_rd_val + traits::X0), false); + } } - } - this->builder.CreateBr(bbnext); - this->builder.SetInsertPoint(bb_else); - { - if(fld_rd_val != 0){ - Value* X_rd_val = this->gen_const(64U, 1); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateBr(bbnext); + this->builder.SetInsertPoint(bb_else); + { + if(fld_rd_val != 0){ + Value* Xtmp2_val = this->gen_const(64U, 1); + this->builder.CreateStore(Xtmp2_val, get_reg_ptr(fld_rd_val + traits::X0), false); + } } + this->builder.CreateBr(bbnext); + bb=bbnext; } - this->builder.CreateBr(bbnext); - bb=bbnext; this->builder.SetInsertPoint(bb); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 65); @@ -3111,17 +3110,17 @@ private: Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); if(fld_rd_val != 0){ - Value* X_rd_val = this->gen_ext( + Value* Xtmp0_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 64/8), 64, true); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } - Value* MEM_offs_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); + Value* MEMtmp1_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(64))); + this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(64))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 66); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -3161,17 +3160,17 @@ private: 64, true); if(fld_rd_val != 0){ - Value* X_rd_val = res_val; - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = res_val; + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } Value* res2_val = this->builder.CreateAdd( res_val, this->gen_reg_load(fld_rs2_val + traits::X0, 0)); - Value* MEM_offs_val = res2_val; + Value* MEMtmp1_val = res2_val; this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(64))); + this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(64))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 67); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -3211,17 +3210,17 @@ private: 64, true); if(fld_rd_val != 0){ - Value* X_rd_val = res_val; - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = res_val; + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } Value* res2_val = this->builder.CreateXor( res_val, this->gen_reg_load(fld_rs2_val + traits::X0, 0)); - Value* MEM_offs_val = res2_val; + Value* MEMtmp1_val = res2_val; this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(64))); + this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(64))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 68); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -3261,17 +3260,17 @@ private: 64, true); if(fld_rd_val != 0){ - Value* X_rd_val = res_val; - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = res_val; + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } Value* res2_val = this->builder.CreateAnd( res_val, this->gen_reg_load(fld_rs2_val + traits::X0, 0)); - Value* MEM_offs_val = res2_val; + Value* MEMtmp1_val = res2_val; this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(64))); + this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(64))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 69); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -3311,17 +3310,17 @@ private: 64, true); if(fld_rd_val != 0){ - Value* X_rd_val = res_val; - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = res_val; + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } Value* res2_val = this->builder.CreateOr( res_val, this->gen_reg_load(fld_rs2_val + traits::X0, 0)); - Value* MEM_offs_val = res2_val; + Value* MEMtmp1_val = res2_val; this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(64))); + this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(64))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 70); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -3361,8 +3360,8 @@ private: 64, true); if(fld_rd_val != 0){ - Value* X_rd_val = res_val; - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = res_val; + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } Value* res2_val = this->gen_choose( this->builder.CreateICmp( @@ -3376,11 +3375,11 @@ private: this->gen_reg_load(fld_rs2_val + traits::X0, 0), res_val, 64); - Value* MEM_offs_val = res_val; + Value* MEMtmp1_val = res_val; this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(64))); + this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(64))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 71); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -3420,8 +3419,8 @@ private: 64, true); if(fld_rd_val != 0){ - Value* X_rd_val = res_val; - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = res_val; + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } Value* res2_val = this->gen_choose( this->builder.CreateICmp( @@ -3435,11 +3434,11 @@ private: this->gen_reg_load(fld_rs2_val + traits::X0, 0), res_val, 64); - Value* MEM_offs_val = res2_val; + Value* MEMtmp1_val = res2_val; this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(64))); + this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(64))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 72); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -3479,8 +3478,8 @@ private: 64, false); if(fld_rd_val != 0){ - Value* X_rd_val = res_val; - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = res_val; + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } Value* res2_val = this->gen_choose( this->builder.CreateICmp( @@ -3490,11 +3489,11 @@ private: this->gen_reg_load(fld_rs2_val + traits::X0, 0), res_val, 64); - Value* MEM_offs_val = res2_val; + Value* MEMtmp1_val = res2_val; this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(64))); + this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(64))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 73); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -3534,8 +3533,8 @@ private: 64, false); if(fld_rd_val != 0){ - Value* X_rd_val = res_val; - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = res_val; + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } Value* res2_val = this->gen_choose( this->builder.CreateICmp( @@ -3545,11 +3544,11 @@ private: this->gen_reg_load(fld_rs2_val + traits::X0, 0), res_val, 64); - Value* MEM_offs_val = res2_val; + Value* MEMtmp1_val = res2_val; this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(64))); + this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(64))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 74); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -3584,19 +3583,19 @@ private: if(fld_rd_val != 0){ Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); - Value* X_rd_val = this->gen_ext( + Value* Xtmp0_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 32/8), 64, true); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); - Value* RES_offs_val = this->gen_ext( + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* REStmp1_val = this->gen_ext( this->builder.CreateNeg(this->gen_const(8U, 1)), 32, true); this->gen_write_mem( traits::RES, offs_val, - this->builder.CreateZExtOrTrunc(RES_offs_val,this->get_type(32))); + this->builder.CreateZExtOrTrunc(REStmp1_val,this->get_type(32))); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 75); @@ -3633,28 +3632,30 @@ private: Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); Value* res1_val = this->gen_read_mem(traits::RES, offs_val, 32/8); - llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); - llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); - // this->builder.SetInsertPoint(bb); - this->gen_cond_branch(this->builder.CreateICmp( - ICmpInst::ICMP_NE, - res1_val, - this->gen_const(32U, 0)), - bb_then, - bbnext); - this->builder.SetInsertPoint(bb_then); { - Value* MEM_offs_val = this->gen_reg_load(fld_rs2_val + traits::X0, 1); - this->gen_write_mem( - traits::MEM, - offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); + llvm::BasicBlock* bbnext = llvm::BasicBlock::Create(this->mod->getContext(), "endif", this->func, this->leave_blk); + llvm::BasicBlock* bb_then = llvm::BasicBlock::Create(this->mod->getContext(), "thenbr", this->func, bbnext); + // this->builder.SetInsertPoint(bb); + this->gen_cond_branch(this->builder.CreateICmp( + ICmpInst::ICMP_NE, + res1_val, + this->gen_const(32U, 0)), + bb_then, + bbnext); + this->builder.SetInsertPoint(bb_then); + { + Value* MEMtmp0_val = this->gen_reg_load(fld_rs2_val + traits::X0, 1); + this->gen_write_mem( + traits::MEM, + offs_val, + this->builder.CreateZExtOrTrunc(MEMtmp0_val,this->get_type(32))); + } + this->builder.CreateBr(bbnext); + bb=bbnext; } - this->builder.CreateBr(bbnext); - bb=bbnext; this->builder.SetInsertPoint(bb); if(fld_rd_val != 0){ - Value* X_rd_val = this->gen_choose( + Value* Xtmp1_val = this->gen_choose( this->builder.CreateICmp( ICmpInst::ICMP_NE, res1_val, @@ -3662,7 +3663,7 @@ private: this->gen_const(64U, 0), this->gen_const(64U, 1), 64); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp1_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 76); @@ -3699,17 +3700,17 @@ private: Value* offs_val = this->gen_reg_load(fld_rs1_val + traits::X0, 0); if(fld_rd_val != 0){ - Value* X_rd_val = this->gen_ext( + Value* Xtmp0_val = this->gen_ext( this->gen_read_mem(traits::MEM, offs_val, 32/8), 64, true); - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } - Value* MEM_offs_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); + Value* MEMtmp1_val = this->gen_reg_load(fld_rs2_val + traits::X0, 0); this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); + this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 77); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -3749,17 +3750,17 @@ private: 64, true); if(fld_rd_val != 0){ - Value* X_rd_val = res1_val; - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = res1_val; + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } Value* res2_val = this->builder.CreateAdd( res1_val, this->gen_reg_load(fld_rs2_val + traits::X0, 0)); - Value* MEM_offs_val = res2_val; + Value* MEMtmp1_val = res2_val; this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); + this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 78); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -3799,17 +3800,17 @@ private: 64, true); if(fld_rd_val != 0){ - Value* X_rd_val = res1_val; - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = res1_val; + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } Value* res2_val = this->builder.CreateXor( res1_val, this->gen_reg_load(fld_rs2_val + traits::X0, 0)); - Value* MEM_offs_val = res2_val; + Value* MEMtmp1_val = res2_val; this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); + this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 79); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -3849,17 +3850,17 @@ private: 64, true); if(fld_rd_val != 0){ - Value* X_rd_val = res1_val; - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = res1_val; + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } Value* res2_val = this->builder.CreateAnd( res1_val, this->gen_reg_load(fld_rs2_val + traits::X0, 0)); - Value* MEM_offs_val = res2_val; + Value* MEMtmp1_val = res2_val; this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); + this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 80); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -3899,17 +3900,17 @@ private: 64, true); if(fld_rd_val != 0){ - Value* X_rd_val = res1_val; - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = res1_val; + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } Value* res2_val = this->builder.CreateOr( res1_val, this->gen_reg_load(fld_rs2_val + traits::X0, 0)); - Value* MEM_offs_val = res2_val; + Value* MEMtmp1_val = res2_val; this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); + this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 81); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -3949,8 +3950,8 @@ private: 64, true); if(fld_rd_val != 0){ - Value* X_rd_val = res1_val; - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = res1_val; + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } Value* res2_val = this->gen_choose( this->builder.CreateICmp( @@ -3964,11 +3965,11 @@ private: this->gen_reg_load(fld_rs2_val + traits::X0, 0), res1_val, 64); - Value* MEM_offs_val = res2_val; + Value* MEMtmp1_val = res2_val; this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); + this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 82); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -4008,8 +4009,8 @@ private: 64, true); if(fld_rd_val != 0){ - Value* X_rd_val = res1_val; - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = res1_val; + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } Value* res2_val = this->gen_choose( this->builder.CreateICmp( @@ -4023,11 +4024,11 @@ private: this->gen_reg_load(fld_rs2_val + traits::X0, 0), res1_val, 64); - Value* MEM_offs_val = res2_val; + Value* MEMtmp1_val = res2_val; this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); + this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 83); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -4067,8 +4068,8 @@ private: 64, false); if(fld_rd_val != 0){ - Value* X_rd_val = res1_val; - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = res1_val; + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } Value* res2_val = this->gen_choose( this->builder.CreateICmp( @@ -4078,11 +4079,11 @@ private: this->gen_reg_load(fld_rs2_val + traits::X0, 0), res1_val, 64); - Value* MEM_offs_val = res2_val; + Value* MEMtmp1_val = res2_val; this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); + this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 84); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -4122,8 +4123,8 @@ private: 64, false); if(fld_rd_val != 0){ - Value* X_rd_val = res1_val; - this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); + Value* Xtmp0_val = res1_val; + this->builder.CreateStore(Xtmp0_val, get_reg_ptr(fld_rd_val + traits::X0), false); } Value* res2_val = this->gen_choose( this->builder.CreateICmp( @@ -4133,11 +4134,11 @@ private: this->gen_reg_load(fld_rs2_val + traits::X0, 0), res1_val, 64); - Value* MEM_offs_val = res2_val; + Value* MEMtmp1_val = res2_val; this->gen_write_mem( traits::MEM, offs_val, - this->builder.CreateZExtOrTrunc(MEM_offs_val,this->get_type(32))); + this->builder.CreateZExtOrTrunc(MEMtmp1_val,this->get_type(32))); this->gen_set_pc(pc, traits::NEXT_PC); this->gen_sync(iss::POST_SYNC, 85); bb = llvm::BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); /* create next BasicBlock in chain */ @@ -4264,16 +4265,7 @@ template inline void vm_impl::gen_trap_check(llvm::BasicBl bb, this->trap_blk, 1); } -template -inline llvm::Value* vm_impl::gen_fdispatch(std::string fname, const std::vector& args) { - return this->builder.CreateCall(this->mod->getFunction(fname), args); -} - -template -inline llvm::Value* vm_impl::gen_dispatch(std::string name, llvm::Value* val1, llvm::Value* val2, llvm::Value* val3) { -} - -} // namespace rv32imacf +} // namespace rv64ia template <> std::unique_ptr create(arch::rv64ia *core, unsigned short port, bool dump) {