2017-09-22 11:23:23 +02:00
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
2017-09-21 13:13:01 +02:00
|
|
|
// Copyright (C) 2017, MINRES Technologies GmbH
|
|
|
|
// All rights reserved.
|
|
|
|
//
|
|
|
|
// Redistribution and use in source and binary forms, with or without
|
|
|
|
// modification, are permitted provided that the following conditions are met:
|
|
|
|
//
|
|
|
|
// 1. Redistributions of source code must retain the above copyright notice,
|
|
|
|
// this list of conditions and the following disclaimer.
|
|
|
|
//
|
|
|
|
// 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
|
|
// this list of conditions and the following disclaimer in the documentation
|
|
|
|
// and/or other materials provided with the distribution.
|
|
|
|
//
|
|
|
|
// 3. Neither the name of the copyright holder nor the names of its contributors
|
|
|
|
// may be used to endorse or promote products derived from this software
|
|
|
|
// without specific prior written permission.
|
|
|
|
//
|
|
|
|
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
|
|
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
|
|
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
|
|
|
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
|
|
|
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
|
|
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
|
|
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|
|
|
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
|
|
|
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
|
|
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
|
|
// POSSIBILITY OF SUCH DAMAGE.
|
|
|
|
//
|
|
|
|
// Contributors:
|
2017-11-27 00:14:41 +01:00
|
|
|
// eyck@minres.com - initial implementation
|
2017-09-21 13:13:01 +02:00
|
|
|
//
|
|
|
|
//
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
|
|
|
|
|
|
#ifndef _SYSC_SIFIVE_FE310_H_
|
|
|
|
#define _SYSC_SIFIVE_FE310_H_
|
|
|
|
|
2017-10-12 22:41:37 +02:00
|
|
|
#include "scc/utilities.h"
|
2017-09-22 11:23:23 +02:00
|
|
|
#include <tlm>
|
2017-10-04 10:31:11 +02:00
|
|
|
#include <tlm_utils/tlm_quantumkeeper.h>
|
2018-03-27 19:49:11 +02:00
|
|
|
#include <cci_configuration>
|
2017-10-04 10:31:11 +02:00
|
|
|
#include <util/range_lut.h>
|
2017-10-12 22:41:37 +02:00
|
|
|
#include "scv4tlm/tlm_rec_initiator_socket.h"
|
2017-10-04 14:30:25 +02:00
|
|
|
#include "scc/initiator_mixin.h"
|
|
|
|
#include "scc/traceable.h"
|
2017-10-04 10:31:11 +02:00
|
|
|
|
2017-10-22 19:29:37 +02:00
|
|
|
class scv_tr_db;
|
|
|
|
class scv_tr_stream;
|
|
|
|
struct _scv_tr_generator_default_data;
|
|
|
|
template < class T_begin, class T_end> class scv_tr_generator;
|
|
|
|
|
2017-10-04 10:31:11 +02:00
|
|
|
namespace iss {
|
|
|
|
class vm_if;
|
|
|
|
namespace arch {
|
2017-10-12 22:41:37 +02:00
|
|
|
template <typename BASE> class riscv_hart_msu_vp;
|
2017-10-04 10:31:11 +02:00
|
|
|
}
|
2017-10-09 22:52:19 +02:00
|
|
|
namespace debugger {
|
2017-10-12 22:41:37 +02:00
|
|
|
class target_adapter_if;
|
2017-10-09 22:52:19 +02:00
|
|
|
}
|
2017-10-04 10:31:11 +02:00
|
|
|
}
|
2017-09-21 13:13:01 +02:00
|
|
|
|
|
|
|
namespace sysc {
|
2017-10-04 10:31:11 +02:00
|
|
|
|
|
|
|
class tlm_dmi_ext : public tlm::tlm_dmi {
|
|
|
|
public:
|
|
|
|
bool operator==(const tlm_dmi_ext &o) const {
|
|
|
|
return this->get_granted_access() == o.get_granted_access() &&
|
|
|
|
this->get_start_address() == o.get_start_address() && this->get_end_address() == o.get_end_address();
|
|
|
|
}
|
|
|
|
|
|
|
|
bool operator!=(const tlm_dmi_ext &o) const { return !operator==(o); }
|
|
|
|
};
|
|
|
|
|
2017-09-21 13:13:01 +02:00
|
|
|
namespace SiFive {
|
2017-10-04 10:31:11 +02:00
|
|
|
class core_wrapper;
|
2017-09-21 13:13:01 +02:00
|
|
|
|
2017-10-04 14:30:25 +02:00
|
|
|
class core_complex : public sc_core::sc_module, public scc::traceable {
|
2017-09-21 13:13:01 +02:00
|
|
|
public:
|
2017-10-04 10:31:11 +02:00
|
|
|
SC_HAS_PROCESS(core_complex);
|
|
|
|
|
2017-10-12 22:41:37 +02:00
|
|
|
scc::initiator_mixin<scv4tlm::tlm_rec_initiator_socket<32>> initiator;
|
2017-10-04 10:31:11 +02:00
|
|
|
|
|
|
|
sc_core::sc_in<sc_core::sc_time> clk_i;
|
2017-09-21 13:13:01 +02:00
|
|
|
|
|
|
|
sc_core::sc_in<bool> rst_i;
|
2017-10-04 10:31:11 +02:00
|
|
|
|
2017-11-10 22:40:24 +01:00
|
|
|
sc_core::sc_in<bool> global_irq_i;
|
|
|
|
|
|
|
|
sc_core::sc_in<bool> timer_irq_i;
|
|
|
|
|
|
|
|
sc_core::sc_in<bool> sw_irq_i;
|
|
|
|
|
|
|
|
sc_core::sc_vector<sc_core::sc_in<bool>> local_irq_i;
|
|
|
|
|
2018-03-27 19:49:11 +02:00
|
|
|
cci::cci_param<std::string> elf_file;
|
2017-10-04 10:31:11 +02:00
|
|
|
|
2018-03-27 19:49:11 +02:00
|
|
|
cci::cci_param<bool> enable_disass;
|
2017-10-04 10:31:11 +02:00
|
|
|
|
2018-03-27 19:49:11 +02:00
|
|
|
cci::cci_param<uint64_t> reset_address;
|
2017-10-04 10:31:11 +02:00
|
|
|
|
2018-03-27 19:49:11 +02:00
|
|
|
cci::cci_param<unsigned short> gdb_server_port;
|
2017-10-04 10:31:11 +02:00
|
|
|
|
2018-03-27 19:49:11 +02:00
|
|
|
cci::cci_param<bool> dump_ir;
|
2017-10-04 10:31:11 +02:00
|
|
|
|
2017-09-21 13:13:01 +02:00
|
|
|
core_complex(sc_core::sc_module_name name);
|
2017-10-04 10:31:11 +02:00
|
|
|
|
|
|
|
~core_complex();
|
|
|
|
|
2018-03-30 17:59:40 +02:00
|
|
|
inline void sync(uint64_t cycle) {
|
2018-07-12 15:27:36 +02:00
|
|
|
auto time = curr_clk*(cycle-last_sync_cycle);
|
|
|
|
quantum_keeper.inc(time);
|
2017-10-04 10:31:11 +02:00
|
|
|
if (quantum_keeper.need_sync()) {
|
|
|
|
wait(quantum_keeper.get_local_time());
|
|
|
|
quantum_keeper.reset();
|
|
|
|
}
|
2018-03-30 17:59:40 +02:00
|
|
|
last_sync_cycle=cycle;
|
2017-10-04 10:31:11 +02:00
|
|
|
}
|
|
|
|
|
2017-10-22 19:29:37 +02:00
|
|
|
bool read_mem(uint64_t addr, unsigned length, uint8_t *const data, bool is_fetch);
|
2017-10-04 10:31:11 +02:00
|
|
|
|
|
|
|
bool write_mem(uint64_t addr, unsigned length, const uint8_t *const data);
|
|
|
|
|
|
|
|
bool read_mem_dbg(uint64_t addr, unsigned length, uint8_t *const data);
|
|
|
|
|
|
|
|
bool write_mem_dbg(uint64_t addr, unsigned length, const uint8_t *const data);
|
|
|
|
|
|
|
|
void trace(sc_core::sc_trace_file *trf) override;
|
|
|
|
|
2017-10-22 19:29:37 +02:00
|
|
|
void disass_output(uint64_t pc, const std::string instr);
|
2017-10-04 10:31:11 +02:00
|
|
|
protected:
|
|
|
|
void before_end_of_elaboration();
|
|
|
|
void start_of_simulation();
|
|
|
|
void run();
|
|
|
|
void clk_cb();
|
2018-07-13 20:04:07 +02:00
|
|
|
void rst_cb();
|
2017-11-10 22:40:24 +01:00
|
|
|
void sw_irq_cb();
|
|
|
|
void timer_irq_cb();
|
|
|
|
void global_irq_cb();
|
2018-03-30 17:59:40 +02:00
|
|
|
uint64_t last_sync_cycle = 0;
|
2017-10-04 10:31:11 +02:00
|
|
|
util::range_lut<tlm_dmi_ext> read_lut, write_lut;
|
|
|
|
tlm_utils::tlm_quantumkeeper quantum_keeper;
|
|
|
|
std::vector<uint8_t> write_buf;
|
|
|
|
std::unique_ptr<core_wrapper> cpu;
|
|
|
|
std::unique_ptr<iss::vm_if> vm;
|
|
|
|
sc_core::sc_time curr_clk;
|
2017-10-09 22:52:19 +02:00
|
|
|
iss::debugger::target_adapter_if* tgt_adapter;
|
2017-10-22 19:29:37 +02:00
|
|
|
#ifdef WITH_SCV
|
|
|
|
//! transaction recording database
|
|
|
|
scv_tr_db *m_db;
|
|
|
|
//! blocking transaction recording stream handle
|
|
|
|
scv_tr_stream *stream_handle;
|
|
|
|
//! transaction generator handle for blocking transactions
|
|
|
|
scv_tr_generator<_scv_tr_generator_default_data,_scv_tr_generator_default_data> *instr_tr_handle;
|
|
|
|
scv_tr_generator<uint64_t,_scv_tr_generator_default_data> *fetch_tr_handle;
|
|
|
|
scv_tr_handle tr_handle;
|
|
|
|
#endif
|
|
|
|
|
2017-09-21 13:13:01 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
} /* namespace SiFive */
|
|
|
|
} /* namespace sysc */
|
|
|
|
|
|
|
|
#endif /* _SYSC_SIFIVE_FE310_H_ */
|