384 lines
12 KiB
C++
384 lines
12 KiB
C++
// -*- C++ -*- <this line is for emacs to recognize it as C++ code>
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/*****************************************************************************
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The following code is derived, directly or indirectly, from the SystemC
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source code Copyright (c) 1996-2014 by all Contributors.
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All Rights reserved.
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The contents of this file are subject to the restrictions and limitations
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set forth in the SystemC Open Source License (the "License");
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You may not use this file except in compliance with such restrictions and
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limitations. You may obtain instructions on how to receive a copy of the
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License at http://www.accellera.org/. Software distributed by Contributors
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under the License is distributed on an "AS IS" basis, WITHOUT WARRANTY OF
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ANY KIND, either express or implied. See the License for the specific
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language governing rights and limitations under the License.
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*****************************************************************************/
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#include "scv.h"
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// hack to fake a true fifo_mutex
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#define fifo_mutex sc_mutex
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const unsigned ram_size = 256;
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class rw_task_if: virtual public sc_interface {
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public:
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typedef sc_uint<8> addr_t;
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typedef sc_uint<8> data_t;
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struct write_t {
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addr_t addr;
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data_t data;
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};
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virtual data_t read(const addr_t*) = 0;
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virtual void write(const write_t*) = 0;
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};
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SCV_EXTENSIONS(rw_task_if::write_t){
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public:
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scv_extensions<rw_task_if::addr_t> addr;
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scv_extensions<rw_task_if::data_t> data;
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SCV_EXTENSIONS_CTOR(rw_task_if::write_t) {
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SCV_FIELD(addr);
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SCV_FIELD(data);
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}
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};
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class pipelined_bus_ports: public sc_module {
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public:
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sc_in<bool> clk;
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sc_inout<bool> rw;
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sc_inout<bool> addr_req;
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sc_inout<bool> addr_ack;
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sc_inout<sc_uint<8> > bus_addr;
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sc_inout<bool> data_rdy;
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sc_inout<sc_uint<8> > bus_data;
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SC_CTOR(pipelined_bus_ports) :
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clk("clk"), rw("rw"), addr_req("addr_req"), addr_ack("addr_ack"), bus_addr("bus_addr"), data_rdy("data_rdy"), bus_data(
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"bus_data") {
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}
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virtual void trace( sc_trace_file* tf ) const;
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};
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void pipelined_bus_ports::trace( sc_trace_file* tf ) const {
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sc_trace(tf, clk, clk.name());
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sc_trace(tf, rw, rw.name());
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sc_trace(tf, addr_req, addr_req.name());
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sc_trace(tf, addr_ack, addr_ack.name());
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sc_trace(tf, bus_addr, bus_addr.name());
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sc_trace(tf, data_rdy, data_rdy.name());
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sc_trace(tf, bus_data, bus_data.name());
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}
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class rw_pipelined_transactor: public rw_task_if, public pipelined_bus_ports {
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fifo_mutex addr_phase;fifo_mutex data_phase;
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scv_tr_stream pipelined_stream;
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scv_tr_stream addr_stream;
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scv_tr_stream data_stream;
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scv_tr_generator<sc_uint<8>, sc_uint<8> > read_gen;
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scv_tr_generator<sc_uint<8>, sc_uint<8> > write_gen;
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scv_tr_generator<sc_uint<8> > addr_gen;
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scv_tr_generator<_scv_tr_generator_default_data, sc_uint<8> > rdata_gen;
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scv_tr_generator<sc_uint<8> > wdata_gen;
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public:
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rw_pipelined_transactor(sc_module_name nm)
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: pipelined_bus_ports(nm)
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, addr_phase("addr_phase")
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, data_phase("data_phase")
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, pipelined_stream((std::string(name()) +".pipelined_stream").c_str(), "transactor")
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, addr_stream( (std::string(name()) +".addr_stream").c_str(), "transactor")
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, data_stream((std::string(name()) +".data_stream").c_str(), "transactor")
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, read_gen("read", pipelined_stream, "addr", "data")
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, write_gen("write", pipelined_stream, "addr", "data")
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, addr_gen("addr", addr_stream, "addr")
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, rdata_gen("rdata", data_stream, NULL, "data")
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, wdata_gen("wdata", data_stream, "data")
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{
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}
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virtual data_t read(const addr_t* p_addr);
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virtual void write(const write_t * req);
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};
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rw_task_if::data_t rw_pipelined_transactor::read(const addr_t* addr) {
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addr_phase.lock();
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scv_tr_handle h = read_gen.begin_transaction(*addr);
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h.record_attribute("data_size", sizeof(data_t));
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scv_tr_handle h1 = addr_gen.begin_transaction(*addr, "addr_phase", h);
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wait(clk->posedge_event());
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bus_addr = *addr;
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rw=false;
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addr_req = 1;
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wait(addr_ack->posedge_event());
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wait(clk->negedge_event());
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addr_req = 0;
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wait(addr_ack->negedge_event());
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addr_gen.end_transaction(h1);
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addr_phase.unlock();
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data_phase.lock();
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scv_tr_handle h2 = rdata_gen.begin_transaction("data_phase", h);
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wait(data_rdy->posedge_event());
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data_t data = bus_data.read();
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wait(data_rdy->negedge_event());
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rdata_gen.end_transaction(h2, data);
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read_gen.end_transaction(h, data);
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data_phase.unlock();
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return data;
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}
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void rw_pipelined_transactor::write(const write_t * req) {
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addr_phase.lock();
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scv_tr_handle h = write_gen.begin_transaction(req->addr);
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h.record_attribute("data_size", sizeof(data_t));
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scv_tr_handle h1 = addr_gen.begin_transaction(req->addr, "addr_phase", h);
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wait(clk->posedge_event());
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bus_addr = req->addr;
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rw=true;
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addr_req = 1;
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wait(addr_ack->posedge_event());
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wait(clk->negedge_event());
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addr_req = 0;
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wait(addr_ack->negedge_event());
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addr_gen.end_transaction(h1);
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addr_phase.unlock();
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data_phase.lock();
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scv_tr_handle h2 = wdata_gen.begin_transaction(req->data, "data_phase", h);
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bus_data=req->data;
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wait(data_rdy->posedge_event());
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wait(data_rdy->negedge_event());
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wdata_gen.end_transaction(h2);
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write_gen.end_transaction(h, req->data);
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data_phase.unlock();
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}
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class test: public sc_module {
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public:
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sc_port<rw_task_if> transactor;
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SC_HAS_PROCESS(test);
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test( ::sc_core::sc_module_name ){
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SC_THREAD(main1);
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SC_THREAD(main2);
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}
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void main1();
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void main2();
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};
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class write_constraint: virtual public scv_constraint_base {
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public:
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scv_smart_ptr<rw_task_if::write_t> write;SCV_CONSTRAINT_CTOR(write_constraint) {
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SCV_CONSTRAINT(write->addr() <= ram_size);
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SCV_CONSTRAINT(write->addr() != write->data());
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}
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};
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inline void process(scv_smart_ptr<int> data) {
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}
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inline void test::main1() {
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// simple sequential tests
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for (int i = 0; i < 3; i++) {
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rw_task_if::addr_t addr = i;
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rw_task_if::data_t data = transactor->read(&addr);
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cout << "at time " << sc_time_stamp() << ": ";
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cout << "received data : " << data << endl;
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}
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scv_smart_ptr<rw_task_if::addr_t> addr;
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for (int i = 0; i < 3; i++) {
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addr->next();
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rw_task_if::data_t data = transactor->read(addr->get_instance());
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cout << "data for address " << *addr << " is " << data << endl;
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}
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scv_smart_ptr<rw_task_if::write_t> write;
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for (int i = 0; i < 3; i++) {
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write->next();
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transactor->write(write->get_instance());
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cout << "send data : " << write->data << endl;
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}
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scv_smart_ptr<int> data;
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scv_bag<int> distribution;
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distribution.push(1, 40);
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distribution.push(2, 60);
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data->set_mode(distribution);
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for (int i = 0; i < 3; i++) {
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data->next();
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process(data);
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}
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}
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inline void test::main2() {
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// simple sequential tests
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for (int i = 0; i < 3; i++) {
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rw_task_if::addr_t addr = i;
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rw_task_if::data_t data = transactor->read(&addr);
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cout << "at time " << sc_time_stamp() << ": ";
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cout << "received data : " << data << endl;
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}
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scv_smart_ptr<rw_task_if::addr_t> addr;
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for (int i = 0; i < 3; i++) {
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addr->next();
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rw_task_if::data_t data = transactor->read(addr->get_instance());
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cout << "data for address " << *addr << " is " << data << endl;
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}
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scv_smart_ptr<rw_task_if::write_t> write;
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for (int i = 0; i < 3; i++) {
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write->next();
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transactor->write(write->get_instance());
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cout << "send data : " << write->data << endl;
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}
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scv_smart_ptr<int> data;
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scv_bag<int> distribution;
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distribution.push(1, 140);
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distribution.push(2, 160);
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data->set_mode(distribution);
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for (int i = 0; i < 3; i++) {
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data->next();
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process(data);
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}
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}
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class design: public pipelined_bus_ports {
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std::list<sc_uint<8> > outstandingAddresses;
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std::list<bool> outstandingType;
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sc_uint<8> memory[ram_size];
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public:
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SC_HAS_PROCESS(design);
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design(sc_module_name nm) :
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pipelined_bus_ports(nm) {
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for (unsigned i = 0; i < ram_size; ++i) {
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memory[i] = i;
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}
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SC_THREAD(addr_phase);
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SC_THREAD(data_phase);
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}
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void addr_phase();
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void data_phase();
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};
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inline void design::addr_phase() {
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while (1) {
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while (addr_req.read() != 1) {
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wait(addr_req->value_changed_event());
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}
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sc_uint<8> _addr = bus_addr.read();
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bool _rw = rw.read();
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int cycle = rand() % 10 + 1;
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while (cycle-- > 0) {
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wait(clk->posedge_event());
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}
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addr_ack = 1;
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wait(clk->posedge_event());
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addr_ack = 0;
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outstandingAddresses.push_back(_addr);
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outstandingType.push_back(_rw);
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cout << "at time " << sc_time_stamp() << ": ";
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cout << "received request for memory address " << _addr << endl;
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}
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}
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inline void design::data_phase() {
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while (1) {
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while (outstandingAddresses.empty()) {
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wait(clk->posedge_event());
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}
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int cycle = rand() % 10 + 1;
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while (cycle-- > 0) {
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wait(clk->posedge_event());
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}
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if (outstandingType.front() == false) {
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cout << "reading memory address " << outstandingAddresses.front() << " with value "
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<< memory[outstandingAddresses.front().to_ulong()] << endl;
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bus_data = memory[outstandingAddresses.front().to_ulong()];
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data_rdy = 1;
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wait(clk->posedge_event());
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data_rdy = 0;
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} else {
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cout << "writing memory address " << outstandingAddresses.front() << " with value "
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<< bus_data << endl;
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memory[outstandingAddresses.front().to_ulong()]=bus_data;
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data_rdy = 1;
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wait(clk->posedge_event());
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data_rdy = 0;
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}
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outstandingAddresses.pop_front();
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outstandingType.pop_front();
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}
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}
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extern void scv_tr_sqlite_init();
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int sc_main(int argc, char *argv[]) {
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scv_startup();
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#if 0
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scv_tr_text_init();
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const char* fileName = "my_db.txlog";
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#else
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scv_tr_sqlite_init();
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const char* fileName = "my_db";
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#endif
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scv_tr_db db(fileName);
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scv_tr_db::set_default_db(&db);
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sc_trace_file* tf = sc_create_vcd_trace_file("my_db");
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// create signals
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sc_clock clk("clk", 20.0, SC_NS, 0.5, 0.0, SC_NS, true);
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sc_signal<bool> rw;
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sc_signal<bool> addr_req;
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sc_signal<bool> addr_ack;
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sc_signal<sc_uint<8> > bus_addr;
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sc_signal<bool> data_rdy;
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sc_signal<sc_uint<8> > bus_data;
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// create modules/channels
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test t("t");
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rw_pipelined_transactor tr("tr");
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design duv("duv");
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// connect them up
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t.transactor(tr);
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tr.clk(clk);
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tr.rw(rw);
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tr.addr_req(addr_req);
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tr.addr_ack(addr_ack);
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tr.bus_addr(bus_addr);
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tr.data_rdy(data_rdy);
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tr.bus_data(bus_data);
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tr.trace(tf);
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duv.clk(clk);
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duv.rw(rw);
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duv.addr_req(addr_req);
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duv.addr_ack(addr_ack);
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duv.bus_addr(bus_addr);
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duv.data_rdy(data_rdy);
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duv.bus_data(bus_data);
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duv.trace(tf);
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// Accellera SystemC >=2.2 got picky about multiple drivers.
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// Disable check for bus simulation.
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sc_report_handler::set_actions(SC_ID_MORE_THAN_ONE_SIGNAL_DRIVER_, SC_DO_NOTHING);
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// run the simulation
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sc_start(1.0, SC_MS);
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sc_close_vcd_trace_file(tf);
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return 0;
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}
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