updates test cases
This commit is contained in:
parent
567d62cea1
commit
bf38ccd6db
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@ -37,7 +37,7 @@
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<stringAttribute key="org.eclipse.jdt.launching.PROGRAM_ARGUMENTS" value="-os ${target.os} -ws ${target.ws} -arch ${target.arch} -nl ${target.nl} -consoleLog"/>
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<stringAttribute key="org.eclipse.jdt.launching.PROJECT_ATTR" value="com.minres.scviewer.database.test"/>
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<stringAttribute key="org.eclipse.jdt.launching.SOURCE_PATH_PROVIDER" value="org.eclipse.pde.ui.workbenchClasspathProvider"/>
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<stringAttribute key="org.eclipse.jdt.launching.VM_ARGUMENTS" value="-Xms40m -Xmx2G"/>
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<stringAttribute key="org.eclipse.jdt.launching.VM_ARGUMENTS" value="-Xms40m -Xmx2G -ea"/>
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<stringAttribute key="pde.version" value="3.3"/>
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<stringAttribute key="product" value="com.minres.scviewer.e4.product"/>
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<booleanAttribute key="run_in_ui_thread" value="true"/>
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@ -6,8 +6,8 @@ begin_attribute (ID 0, name "addr", type "UNSIGNED")
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end_attribute (ID 1, name "data", type "UNSIGNED")
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)
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scv_tr_generator (ID 5, name "write", scv_tr_stream 1,
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begin_attribute (ID 0, name "addr", type "UNSIGNED")
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end_attribute (ID 1, name "data", type "UNSIGNED")
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begin_attribute (ID 0, name "wr.addr", type "UNSIGNED")
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begin_attribute (ID 1, name "wr.data", type "UNSIGNED")
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)
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scv_tr_generator (ID 6, name "addr", scv_tr_stream 2,
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begin_attribute (ID 0, name "addr", type "UNSIGNED")
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@ -24,231 +24,231 @@ tx_record_attribute 1 "data_size" UNSIGNED = 24
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tx_begin 2 6 0 s
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a 0
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tx_relation "addr_phase" 2 1
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tx_end 2 6 180 ns
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tx_begin 3 7 180 ns
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tx_end 2 6 100 ns
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tx_begin 3 7 100 ns
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tx_relation "data_phase" 3 1
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tx_begin 4 4 180 ns
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tx_begin 4 4 100 ns
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a 0
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tx_record_attribute 4 "data_size" UNSIGNED = 24
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tx_begin 5 6 180 ns
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tx_begin 5 6 100 ns
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a 0
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tx_relation "addr_phase" 5 4
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tx_end 3 7 280 ns
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a 0
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tx_end 1 4 280 ns
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a 0
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tx_end 5 6 300 ns
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tx_end 3 7 420 ns
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a 0
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tx_end 1 4 420 ns
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a 0
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tx_begin 6 4 420 ns
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tx_begin 6 7 300 ns
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tx_relation "data_phase" 6 4
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tx_begin 7 4 300 ns
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a 1
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tx_record_attribute 6 "data_size" UNSIGNED = 24
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tx_begin 7 6 420 ns
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tx_record_attribute 7 "data_size" UNSIGNED = 24
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tx_begin 8 6 300 ns
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a 1
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tx_relation "addr_phase" 7 6
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tx_begin 8 7 420 ns
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tx_relation "data_phase" 8 4
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tx_end 7 6 480 ns
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tx_end 8 7 620 ns
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tx_relation "addr_phase" 8 7
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tx_end 8 6 420 ns
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tx_end 6 7 460 ns
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a 0
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tx_end 4 4 620 ns
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tx_end 4 4 460 ns
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a 0
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tx_begin 9 4 620 ns
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tx_begin 9 4 460 ns
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a 1
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tx_record_attribute 9 "data_size" UNSIGNED = 24
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tx_begin 10 6 620 ns
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tx_begin 10 6 460 ns
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a 1
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tx_relation "addr_phase" 10 9
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tx_begin 11 7 620 ns
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tx_relation "data_phase" 11 6
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tx_end 11 7 700 ns
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tx_begin 11 7 460 ns
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tx_relation "data_phase" 11 7
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tx_end 11 7 600 ns
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a 1
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tx_end 6 4 700 ns
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tx_end 7 4 600 ns
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a 1
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tx_end 10 6 760 ns
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tx_begin 12 7 760 ns
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tx_end 10 6 640 ns
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tx_begin 12 7 640 ns
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tx_relation "data_phase" 12 9
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tx_begin 13 4 760 ns
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tx_begin 13 4 640 ns
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a 2
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tx_record_attribute 13 "data_size" UNSIGNED = 24
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tx_begin 14 6 760 ns
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tx_begin 14 6 640 ns
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a 2
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tx_relation "addr_phase" 14 13
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tx_end 12 7 740 ns
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a 1
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tx_end 9 4 740 ns
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a 1
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tx_end 14 6 880 ns
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tx_end 12 7 980 ns
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a 1
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tx_end 9 4 980 ns
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a 1
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tx_begin 15 4 980 ns
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tx_begin 15 7 880 ns
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tx_relation "data_phase" 15 13
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tx_begin 16 4 880 ns
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a 2
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tx_record_attribute 15 "data_size" UNSIGNED = 24
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tx_begin 16 6 980 ns
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tx_record_attribute 16 "data_size" UNSIGNED = 24
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tx_begin 17 6 880 ns
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a 2
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tx_relation "addr_phase" 16 15
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tx_begin 17 7 980 ns
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tx_relation "data_phase" 17 13
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tx_end 16 6 1040 ns
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tx_end 17 7 1200 ns
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tx_relation "addr_phase" 17 16
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tx_end 15 7 960 ns
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a 2
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tx_end 13 4 1200 ns
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tx_end 13 4 960 ns
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a 2
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tx_begin 18 4 1200 ns
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a 120
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tx_record_attribute 18 "data_size" UNSIGNED = 24
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tx_begin 19 6 1200 ns
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a 120
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tx_relation "addr_phase" 19 18
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tx_begin 20 7 1200 ns
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tx_relation "data_phase" 20 15
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tx_end 19 6 1300 ns
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tx_end 20 7 1340 ns
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tx_end 17 6 980 ns
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tx_begin 18 7 980 ns
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tx_relation "data_phase" 18 16
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tx_begin 19 4 980 ns
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a 24
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tx_record_attribute 19 "data_size" UNSIGNED = 24
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tx_begin 20 6 980 ns
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a 24
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tx_relation "addr_phase" 20 19
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tx_end 20 6 1040 ns
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tx_end 18 7 1180 ns
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a 2
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tx_end 15 4 1340 ns
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tx_end 16 4 1180 ns
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a 2
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tx_begin 21 4 1340 ns
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a 11
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tx_begin 21 4 1180 ns
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a 79
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tx_record_attribute 21 "data_size" UNSIGNED = 24
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tx_begin 22 6 1340 ns
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a 11
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tx_begin 22 6 1180 ns
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a 79
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tx_relation "addr_phase" 22 21
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tx_begin 23 7 1340 ns
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tx_relation "data_phase" 23 18
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tx_end 23 7 1420 ns
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a 120
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tx_end 18 4 1420 ns
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a 120
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tx_end 22 6 1540 ns
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tx_begin 24 7 1540 ns
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tx_relation "data_phase" 24 21
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tx_begin 25 4 1540 ns
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a 147
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tx_record_attribute 25 "data_size" UNSIGNED = 24
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tx_begin 26 6 1540 ns
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a 147
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tx_relation "addr_phase" 26 25
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tx_end 24 7 1660 ns
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a 11
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tx_end 21 4 1660 ns
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a 11
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tx_end 26 6 1740 ns
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tx_begin 27 7 1740 ns
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tx_relation "data_phase" 27 25
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tx_begin 28 4 1740 ns
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a 99
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tx_record_attribute 28 "data_size" UNSIGNED = 24
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tx_begin 29 6 1740 ns
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a 99
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tx_relation "addr_phase" 29 28
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tx_end 29 6 1800 ns
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tx_end 27 7 1980 ns
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a 147
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tx_end 25 4 1980 ns
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a 147
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tx_begin 30 4 1980 ns
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a 55
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tx_begin 23 7 1180 ns
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tx_relation "data_phase" 23 19
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tx_end 22 6 1300 ns
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tx_end 23 7 1400 ns
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a 24
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tx_end 19 4 1400 ns
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a 24
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tx_begin 24 4 1400 ns
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a 232
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tx_record_attribute 24 "data_size" UNSIGNED = 24
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tx_begin 25 6 1400 ns
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a 232
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tx_relation "addr_phase" 25 24
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tx_begin 26 7 1400 ns
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tx_relation "data_phase" 26 21
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tx_end 25 6 1460 ns
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tx_end 26 7 1560 ns
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a 79
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tx_end 21 4 1560 ns
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a 79
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tx_begin 27 4 1560 ns
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a 128
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tx_record_attribute 27 "data_size" UNSIGNED = 24
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tx_begin 28 6 1560 ns
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a 128
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tx_relation "addr_phase" 28 27
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tx_begin 29 7 1560 ns
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tx_relation "data_phase" 29 24
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tx_end 28 6 1660 ns
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tx_end 29 7 1720 ns
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a 232
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tx_end 24 4 1720 ns
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a 232
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tx_begin 30 4 1720 ns
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a 72
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tx_record_attribute 30 "data_size" UNSIGNED = 24
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tx_begin 31 6 1980 ns
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a 55
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tx_begin 31 6 1720 ns
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a 72
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tx_relation "addr_phase" 31 30
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tx_begin 32 7 1980 ns
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tx_relation "data_phase" 32 28
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tx_end 32 7 2060 ns
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a 99
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tx_end 28 4 2060 ns
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a 99
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tx_end 31 6 2100 ns
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tx_begin 33 7 2100 ns
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tx_relation "data_phase" 33 30
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tx_begin 34 4 2100 ns
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a 126
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tx_record_attribute 34 "data_size" UNSIGNED = 24
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tx_begin 35 6 2100 ns
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a 126
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tx_relation "addr_phase" 35 34
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tx_end 33 7 2340 ns
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a 55
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tx_end 30 4 2340 ns
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a 55
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tx_end 35 6 2340 ns
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tx_begin 36 7 2340 ns
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tx_relation "data_phase" 36 34
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tx_begin 37 5 2340 ns
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a 204
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tx_begin 32 7 1720 ns
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tx_relation "data_phase" 32 27
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tx_end 31 6 1800 ns
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tx_end 32 7 1880 ns
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a 128
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tx_end 27 4 1880 ns
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a 128
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tx_begin 33 4 1880 ns
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a 185
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tx_record_attribute 33 "data_size" UNSIGNED = 24
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tx_begin 34 6 1880 ns
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a 185
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tx_relation "addr_phase" 34 33
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tx_begin 35 7 1880 ns
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tx_relation "data_phase" 35 30
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tx_end 35 7 2080 ns
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a 72
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tx_end 30 4 2080 ns
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a 72
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tx_end 34 6 2080 ns
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tx_begin 36 7 2080 ns
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tx_relation "data_phase" 36 33
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tx_begin 37 5 2080 ns
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a 191
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a 1
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tx_record_attribute 37 "data_size" UNSIGNED = 24
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tx_begin 38 6 2340 ns
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a 204
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tx_begin 38 6 2080 ns
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a 191
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tx_relation "addr_phase" 38 37
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tx_end 38 6 2400 ns
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tx_end 36 7 2540 ns
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a 126
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tx_end 34 4 2540 ns
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a 126
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tx_begin 39 5 2540 ns
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a 242
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tx_end 38 6 2180 ns
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tx_end 36 7 2320 ns
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a 185
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tx_end 33 4 2320 ns
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a 185
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tx_begin 39 5 2320 ns
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a 8
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a 67
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tx_record_attribute 39 "data_size" UNSIGNED = 24
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tx_begin 40 6 2540 ns
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a 242
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tx_begin 40 6 2320 ns
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a 8
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tx_relation "addr_phase" 40 39
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tx_begin 41 8 2540 ns
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a 211
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tx_begin 41 8 2320 ns
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a 1
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tx_relation "data_phase" 41 37
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tx_end 41 8 2640 ns
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tx_end 37 5 2640 ns
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a 211
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tx_end 40 6 2780 ns
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tx_begin 42 8 2780 ns
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a 58
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tx_end 41 8 2360 ns
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tx_end 37 5 2360 ns
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tx_end 40 6 2420 ns
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tx_begin 42 8 2420 ns
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a 67
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tx_relation "data_phase" 42 39
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tx_begin 43 5 2780 ns
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a 135
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tx_begin 43 5 2420 ns
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a 55
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a 20
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tx_record_attribute 43 "data_size" UNSIGNED = 24
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tx_begin 44 6 2780 ns
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a 135
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tx_begin 44 6 2420 ns
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a 55
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tx_relation "addr_phase" 44 43
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tx_end 44 6 2960 ns
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tx_end 42 8 3 us
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tx_end 39 5 3 us
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a 58
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tx_begin 45 5 3 us
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a 26
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tx_record_attribute 45 "data_size" UNSIGNED = 24
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tx_begin 46 6 3 us
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a 26
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tx_relation "addr_phase" 46 45
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tx_begin 47 8 3 us
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a 31
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tx_relation "data_phase" 47 43
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tx_end 47 8 3140 ns
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tx_end 43 5 3140 ns
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a 31
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tx_end 46 6 3200 ns
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tx_begin 48 8 3200 ns
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a 37
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tx_relation "data_phase" 48 45
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tx_begin 49 5 3200 ns
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a 176
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tx_end 42 8 2540 ns
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tx_end 39 5 2540 ns
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tx_end 44 6 2620 ns
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tx_begin 45 8 2620 ns
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a 20
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tx_relation "data_phase" 45 43
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tx_begin 46 5 2620 ns
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a 56
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a 179
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tx_record_attribute 46 "data_size" UNSIGNED = 24
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tx_begin 47 6 2620 ns
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a 56
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tx_relation "addr_phase" 47 46
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tx_end 45 8 2780 ns
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tx_end 43 5 2780 ns
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tx_end 47 6 2860 ns
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tx_begin 48 8 2860 ns
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a 179
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tx_relation "data_phase" 48 46
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tx_begin 49 5 2860 ns
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a 250
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a 75
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tx_record_attribute 49 "data_size" UNSIGNED = 24
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tx_begin 50 6 3200 ns
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a 176
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tx_begin 50 6 2860 ns
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a 250
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tx_relation "addr_phase" 50 49
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tx_end 50 6 3300 ns
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tx_end 48 8 3380 ns
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tx_end 45 5 3380 ns
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a 37
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tx_begin 51 5 3380 ns
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a 58
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tx_record_attribute 51 "data_size" UNSIGNED = 24
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tx_begin 52 6 3380 ns
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a 58
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tx_relation "addr_phase" 52 51
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tx_begin 53 8 3380 ns
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a 220
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tx_relation "data_phase" 53 49
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tx_end 52 6 3440 ns
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tx_end 53 8 3560 ns
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tx_end 49 5 3560 ns
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a 220
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tx_begin 54 8 3560 ns
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a 109
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tx_relation "data_phase" 54 51
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tx_end 54 8 3660 ns
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tx_end 51 5 3660 ns
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a 109
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tx_end 48 8 2960 ns
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tx_end 46 5 2960 ns
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tx_end 50 6 2960 ns
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tx_begin 51 8 2960 ns
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a 75
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tx_relation "data_phase" 51 49
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tx_begin 52 5 2960 ns
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a 121
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a 168
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tx_record_attribute 52 "data_size" UNSIGNED = 24
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tx_begin 53 6 2960 ns
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a 121
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tx_relation "addr_phase" 53 52
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tx_end 51 8 3180 ns
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tx_end 49 5 3180 ns
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tx_end 53 6 3200 ns
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tx_begin 54 8 3200 ns
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a 168
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tx_relation "data_phase" 54 52
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tx_end 54 8 3400 ns
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tx_end 52 5 3400 ns
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File diff suppressed because it is too large
Load Diff
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@ -49,15 +49,19 @@ public class DatabaseServicesTest {
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assertTrue(f.exists());
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waveformDb.load(f);
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assertNotNull(waveformDb);
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List<IWaveform> waves= waveformDb.getAllWaves();
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assertEquals(14, waves.size());
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List<IWaveform> waveforms= waveformDb.getAllWaves();
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assertEquals(14, waveforms.size());
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assertEquals(2, waveformDb.getChildNodes().size());
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IWaveform bus_data_wave = waves.get(0);
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EventEntry bus_data_entry = bus_data_wave.getEvents().floorEntry(1400000000L);
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assertEquals("00001011", bus_data_entry.events[0].toString());
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IWaveform rw_wave = waves.get(2);
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EventEntry rw_entry = rw_wave.getEvents().floorEntry(2360000000L);
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waveforms.stream().filter(s -> s.getName().equals("bus_addr[7:0]")).forEach(s -> {
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EventEntry bus_data_entry = s.getEvents().floorEntry(1400000000L);
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assertEquals("01001111", bus_data_entry.events[0].toString());
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});
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waveforms.stream().filter(s -> s.getName().equals("rw")).forEach(s -> {
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EventEntry rw_entry = s.getEvents().floorEntry(2360000000L);
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assertEquals("1", rw_entry.events[0].toString());
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});
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}
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@Test
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@ -128,7 +132,6 @@ public class DatabaseServicesTest {
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assertEquals(1, w.getRowCount());
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}
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}
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//waveforms.stream().filter(s -> s.getId()==1).collect(Collectors.toList());
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waveforms.stream().filter(s -> s.getId()==1).forEach(s -> {
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assertEquals(27, s.getEvents().size());
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});
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@ -163,7 +166,6 @@ public class DatabaseServicesTest {
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assertEquals(1, w.getRowCount());
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}
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}
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//waveforms.stream().filter(s -> s.getId()==1).collect(Collectors.toList());
|
||||
waveforms.stream().filter(s -> s.getId()==1).forEach(s -> {
|
||||
assertEquals(27, s.getEvents().size());
|
||||
});
|
||||
|
|
@ -186,14 +188,17 @@ public class DatabaseServicesTest {
|
|||
assertTrue(f.exists());
|
||||
waveformDb.load(f);
|
||||
assertNotNull(waveformDb);
|
||||
List<IWaveform> waves= waveformDb.getAllWaves();
|
||||
assertEquals(14, waves.size());
|
||||
List<IWaveform> waveforms= waveformDb.getAllWaves();
|
||||
assertEquals(14, waveforms.size());
|
||||
assertEquals(2, waveformDb.getChildNodes().size());
|
||||
IWaveform bus_data_wave = waves.get(12);
|
||||
EventEntry bus_data_entry = bus_data_wave.getEvents().floorEntry(1400000000L);
|
||||
assertEquals("00001011", bus_data_entry.events[0].toString());
|
||||
IWaveform rw_wave = waves.get(2);
|
||||
EventEntry rw_entry = rw_wave.getEvents().floorEntry(2360000000L);
|
||||
waveforms.stream().filter(s -> s.getName().equals("bus_addr[7:0]")).forEach(s -> {
|
||||
EventEntry bus_data_entry = s.getEvents().floorEntry(1400000000L);
|
||||
assertEquals("01001111", bus_data_entry.events[0].toString());
|
||||
});
|
||||
|
||||
waveforms.stream().filter(s -> s.getName().equals("rw")).forEach(s -> {
|
||||
EventEntry rw_entry = s.getEvents().floorEntry(2360000000L);
|
||||
assertEquals("1", rw_entry.events[0].toString());
|
||||
});
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue