TGFS/TGC-ISS
10
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

updates Jenkinsfile

Browse Source
This commit is contained in:
Eyck-Alexander Jentzsch
2024-07-11 09:41:06 +02:00
parent ab4a0eeb6e
commit fa1c960247
1 changed files with 52 additions and 37 deletions
Download Patch File Download Diff File Expand all files Collapse all files

75
Jenkinsfile vendored
View File

@@ -19,54 +19,69 @@ pipeline {
agent { agent {
docker { docker {
image 'git.minres.com/tooling/riscof_sail:latest' image 'git.minres.com/tooling/riscof_sail:latest'
args ' -e CONAN_USER_HOME=/var/jenkins_home/workspace/riscof_sail' args '-e CONAN_USER_HOME=/var/jenkins_home/workspace/riscof_sail'
} }
} }
stages { stages {
stage("Checkout TGC-ISS"){ stage("Checkout TGC-Compliance and TGC-GEN"){
steps {
checkout_project("https://git.minres.com/TGFS/TGC-ISS.git", "develop")
}
}
stage("build TGC-ISS"){
steps {
sh 'conan profile new default --detect --force '
sh 'cmake -S . -B build -DCMAKE_BUILD_TYPE=Release -DWITH_ASMJIT=ON -DWITH_TCC=ON -DWITH_LLVM=ON'
sh 'cmake --build build -j'
}
}
stage("Checkout TGC-Compliance"){
steps { steps {
dir("TGC-COMPLIANCE"){ dir("TGC-COMPLIANCE"){
checkout_project("https://git.minres.com/TGFS/TGC-COMPLIANCE.git", "master") checkout_project("https://git.minres.com/TGFS/TGC-COMPLIANCE.git", "master")
} }
dir("TGC-GEN"){
checkout_project("https://git.minres.com/TGFS/TGC-GEN.git", "develop")
} }
} }
stage("Test backends"){ }
parallel { stage("generate cores and build TGC-ISS"){
stage("Test interp") {
steps { steps {
sh "mkdir interp" sh 'TGC-COMPLIANCE/scripts/generate_all -o dbt-rise-tgc'
sh "python3 TGC-COMPLIANCE/run_act.py -core TGC5C -sim build/dbt-rise-tgc/tgc-sim -w interp --local --backend interp" sh 'conan profile new default --detect --force'
sh 'cmake -S . -B build -DCMAKE_BUILD_TYPE=Release -DWITH_ASMJIT=ON -DWITH_TCC=ON -DWITH_LLVM=ON'
sh 'cmake --build build -j'
} }
} }
stage("Test tcc") { stage('ACT 32bit') {
matrix {
axes {
axis {
name 'CORE'
values 'TGC5A', 'TGC5B', 'TGC5C', 'TGC5D', 'TGC5E'
}
axis {
name 'BACKEND'
values 'interp', 'llvm', 'tcc', 'asmjit'
}
}
stages {
stage('Run riscof') {
steps { steps {
sh "mkdir tcc" sh "mkdir ${BACKEND}"
sh "python3 TGC-COMPLIANCE/run_act.py -core TGC5C -sim build/dbt-rise-tgc/tgc-sim -w tcc --local --backend tcc" sh "python3 TGC-COMPLIANCE/run_act.py -core ${CORE} -sim build/dbt-rise-tgc/tgc-sim -w ${BACKEND} --local --backend ${BACKEND}"
} }
} }
stage("Test asmjit") { }
}
}
stage('ACT 64bit') {
matrix {
axes {
axis {
name 'CORE'
values 'TGC6B', 'TGC6C', 'TGC6D', 'TGC6E'
}
axis {
name 'BACKEND'
values 'interp', 'llvm', 'asmjit'
}
}
stages {
stage('Run riscof') {
steps { steps {
sh "mkdir asmjit" sh "mkdir ${BACKEND}"
sh "python3 TGC-COMPLIANCE/run_act.py -core TGC5C -sim build/dbt-rise-tgc/tgc-sim -w asmjit --local --backend asmjit" sh "python3 TGC-COMPLIANCE/run_act.py -core ${CORE} -sim build/dbt-rise-tgc/tgc-sim -w ${BACKEND} --local --backend ${BACKEND}"
} }
} }
stage("Test llvm") {
steps {
sh "mkdir llvm"
sh "python3 TGC-COMPLIANCE/run_act.py -core TGC5C -sim build/dbt-rise-tgc/tgc-sim -w llvm --local --backend llvm"
}
} }
} }
} }