112 lines
3.5 KiB
C++
112 lines
3.5 KiB
C++
/*******************************************************************************
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* Copyright 2017 eyck@minres.com
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may not
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* use this file except in compliance with the License. You may obtain a copy
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* of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations under
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* the License.
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******************************************************************************/
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#ifndef _UART_REGS_H_
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#define _UART_REGS_H_
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#include <util/bit_field.h>
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#include <sysc/register.h>
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#include <sysc/tlmtarget.h>
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#include <sysc/utilities.h>
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namespace sysc {
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template<unsigned BUSWIDTH=32>
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class uart_regs :
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public sc_core::sc_module,
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public sysc::tlm_target<BUSWIDTH>,
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public sysc::resetable
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{
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protected:
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// storage declarations
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BEGIN_BF_DECL(txdata_t, uint32_t);
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BF_FIELD(data, 0, 8);
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BF_FIELD(full, 31, 1);
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END_BF_DECL() r_txdata;
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BEGIN_BF_DECL(rxdata_t, uint32_t);
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BF_FIELD(data, 0, 8);
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BF_FIELD(empty, 31, 1);
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END_BF_DECL() r_rxdata;
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BEGIN_BF_DECL(txctrl_t, uint32_t);
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BF_FIELD(txen, 0, 1);
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BF_FIELD(nstop, 1, 1);
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BF_FIELD(reserved, 2, 14);
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BF_FIELD(txcnt, 16, 3);
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END_BF_DECL() r_txctrl;
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BEGIN_BF_DECL(rxctrl_t, uint32_t);
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BF_FIELD(rxen, 0, 1);
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BF_FIELD(reserved, 1, 15);
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BF_FIELD(rxcnt, 16, 3);
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END_BF_DECL() r_rxctrl;
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BEGIN_BF_DECL(ie_t, uint32_t);
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BF_FIELD(txwm, 0, 1);
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BF_FIELD(rxwm, 1, 1);
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END_BF_DECL() r_ie;
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BEGIN_BF_DECL(ip_t, uint32_t);
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BF_FIELD(txwm, 0, 1);
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BF_FIELD(rxwm, 1, 1);
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END_BF_DECL() r_ip;
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BEGIN_BF_DECL(div_t, uint32_t);
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BF_FIELD(div, 0, 16);
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END_BF_DECL() r_div;
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// register declarations
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sysc::sc_register<typename txdata_t::StorageType> txdata;
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sysc::sc_register<typename rxdata_t::StorageType> rxdata;
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sysc::sc_register<typename txctrl_t::StorageType> txctrl;
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sysc::sc_register<typename rxctrl_t::StorageType> rxctrl;
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sysc::sc_register<typename ie_t::StorageType> ie;
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sysc::sc_register<typename ip_t::StorageType> ip;
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sysc::sc_register<typename div_t::StorageType> div;
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uart_regs(sc_core::sc_module_name nm);
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protected:
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sc_core::sc_time clk;
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};
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//////////////////////////////////////////////////////////////////////////////
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// member functions
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//////////////////////////////////////////////////////////////////////////////
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template<unsigned BUSWIDTH>
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uart_regs<BUSWIDTH>::uart_regs(sc_core::sc_module_name nm)
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: sc_core::sc_module(nm)
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, sysc::tlm_target<BUSWIDTH>(clk)
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, NAMED(txdata, r_txdata, 0, *this)
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, NAMED(rxdata, r_rxdata, 0, *this)
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, NAMED(txctrl, r_txctrl, 0, *this)
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, NAMED(rxctrl, r_rxctrl, 0, *this)
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, NAMED(ie, r_ie, 0, *this)
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, NAMED(ip, r_ip, 0, *this)
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, NAMED(div, r_div, 0, *this)
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{
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this->socket_map.addEntry(&txdata, 0x0UL, 0x4UL);
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this->socket_map.addEntry(&rxdata, 0x4UL, 0x4UL);
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this->socket_map.addEntry(&txctrl, 0x8UL, 0x4UL);
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this->socket_map.addEntry(&rxctrl, 0xcUL, 0x4UL);
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this->socket_map.addEntry(&ie, 0x10UL, 0x4UL);
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this->socket_map.addEntry(&ip, 0x14UL, 0x4UL);
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this->socket_map.addEntry(&div, 0x18UL, 0x4UL);
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}
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}
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#endif // _UART_REGS_H_
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