178 lines
5.9 KiB
C++
178 lines
5.9 KiB
C++
////////////////////////////////////////////////////////////////////////////////
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// Copyright (C) 2017, MINRES Technologies GmbH
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its contributors
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// may be used to endorse or promote products derived from this software
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// without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY0x200004, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// Contributors:
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// eyck@minres.com - initial API and implementation
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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// todo: truncate values beyond 7 (in prio_threshold write_cb)
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#include "plic.h"
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#include "gen/plic_regs.h"
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#include "scc/utilities.h"
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#include <scc/report.h>
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namespace sysc {
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plic::plic(sc_core::sc_module_name nm)
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: sc_core::sc_module(nm)
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, tlm_target<>(clk)
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, NAMED(clk_i)
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, NAMED(rst_i)
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, NAMED(global_interrupts_i, 256)
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, NAMED(core_interrupt_o)
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, NAMEDD(regs, plic_regs)
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{
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regs->registerResources(*this);
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// register callbacks
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init_callbacks();
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regs->claim_complete.set_write_cb(m_claim_complete_write_cb);
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// port callbacks
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SC_METHOD(global_int_port_cb);
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for (uint8_t i = 0; i < 255; i++) {
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sensitive << global_interrupts_i[i].pos();
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}
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dont_initialize();
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// register event callbacks
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SC_METHOD(clock_cb);
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sensitive << clk_i;
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SC_METHOD(reset_cb);
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sensitive << rst_i;
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}
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plic::~plic() {}
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void plic::init_callbacks() {
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m_claim_complete_write_cb = [=](scc::sc_register<uint32_t> reg, uint32_t v) -> bool {
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reg.put(v);
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reset_pending_int(v);
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// std::cout << "Value of register: 0x" << std::hex << reg << std::endl;
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// todo: reset related interrupt and find next high-prio interrupt
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return true;
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};
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}
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void plic::clock_cb() { this->clk = clk_i.read(); }
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void plic::reset_cb() {
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if (rst_i.read())
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regs->reset_start();
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else
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regs->reset_stop();
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}
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// Functional handling of interrupts:
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// - global_int_port_cb()
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// - set pending register bits
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// - called by: incoming global_int
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// - handle_pending_int()
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// - update claim register content
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// - generate core-interrupt pulse
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// - called by:
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// - incoming global_int
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// - complete-register write access
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// - reset_pending_int(int-id)
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// - reset pending bit
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// - call next handle_pending_int()
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// - called by:
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// - complete-reg write register content
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void plic::global_int_port_cb() {
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// set related pending bit if enable is set for incoming global_interrupt
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// todo: extend up to 255 bits (limited to 32 right now)
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for (uint32_t i = 1; i < 32; i++) {
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uint32_t enable_bits = regs->r_enabled;
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bool enable = enable_bits & (0x1 << i); // read enable bit
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if (enable && global_interrupts_i[i].read() == 1) {
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regs->r_pending = regs->r_pending | (0x1 << i);
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SCDEBUG("plic") << "pending interrupt identified: " << i;
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}
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}
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handle_pending_int();
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}
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void plic::handle_pending_int() {
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// identify high-prio pending interrupt and raise a core-interrupt
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uint32_t claim_int = 0; // claim interrupt
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uint32_t claim_prio = 0; // related priority (highest prio interrupt wins the race)
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bool raise_int = 0;
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uint32_t thold = regs->r_threshold.threshold; // threshold value
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// todo: extend up to 255 bits (limited to 32 right now)
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for (uint32_t i = 1; i < 32; i++) {
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uint32_t pending_bits = regs->r_pending;
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bool pending = (pending_bits & (0x1 << i)) ? true : false;
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uint32_t prio = regs->r_priority[i - 1].priority; // read priority value
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if (pending && thold < prio) {
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regs->r_pending = regs->r_pending | (0x1 << i);
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// below condition ensures implicitly that lowest id is selected in case of multiple identical
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// priority-interrupts
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if (prio > claim_prio) {
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claim_prio = prio;
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claim_int = i;
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raise_int = 1;
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SCDEBUG("plic") << "pending interrupt activated: " << i;
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}
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}
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}
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if (raise_int) {
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regs->r_claim_complete = claim_int;
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core_interrupt_o.write(1);
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// todo: evluate clock period
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} else {
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regs->r_claim_complete = 0;
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SCDEBUG("plic") << "no further pending interrupt.";
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}
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}
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void plic::reset_pending_int(uint32_t irq) {
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// todo: evaluate enable register (see spec)
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// todo: make sure that pending is set, otherwise don't reset irq ... read spec.
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SCDEBUG("plic") << "reset pending interrupt: " << irq;
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// reset related pending bit
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regs->r_pending &= ~(0x1 << irq);
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core_interrupt_o.write(0);
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// evaluate next pending interrupt
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handle_pending_int();
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}
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} /* namespace sysc */
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