273 lines
7.9 KiB
C++
273 lines
7.9 KiB
C++
////////////////////////////////////////////////////////////////////////////////
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// Copyright 2017 eyck@minres.com
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//
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// Licensed under the Apache License, Version 2.0 (the "License"); you may not
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// use this file except in compliance with the License. You may obtain a copy
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// of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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// License for the specific language governing permissions and limitations under
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// the License.
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////////////////////////////////////////////////////////////////////////////////
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/*
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* test_initiator.cpp
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*
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* Created on: 17.09.2017
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* Author: eyck@minres.com
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*/
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#include "test_initiator.h"
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#include <array>
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#include <scc/report.h>
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#include <scc/utilities.h>
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// todo: move into gen folder somewhere (adapt code-generator)
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#define PLIC_PRIO1_REG 0x0C000004
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#define PLIC_PRIO2_REG 0x0C000008
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#define PLIC_PRIO3_REG 0x0C00000C
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#define PLIC_PRIO4_REG 0x0C000010
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#define PLIC_PENDING_REG 0x0C001000
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#define PLIC_ENABLE_REG 0x0C002000
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#define PLIC_PRIO_TRESHOLD_REG 0x0C200000
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#define PLIC_CLAIM_COMPLETE_REG 0x0C200004
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namespace sysc {
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using namespace sc_core;
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test_initiator::test_initiator(sc_module_name nm)
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: sc_module(nm)
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, NAMED(intor)
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, NAMED(rst_i)
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, NAMED(global_interrupts_o, 256)
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, NAMED(core_interrupt_i) {
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SC_THREAD(run);
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SC_METHOD(core_irq_handler);
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sensitive << core_interrupt_i;
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dont_initialize();
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}
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void test_initiator::run() {
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// wait for reset
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if (rst_i.read() == false) wait(rst_i.posedge_event());
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wait(rst_i.negedge_event());
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wait(10_ns);
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// apply test-sequences
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test_unique_irq();
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test_frequent_irq();
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test_parallel_irq();
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test_irq_stress();
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// todo: review irq sequences from FW point of view ... expected ???
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wait(100_ns);
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sc_stop();
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}
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void test_initiator::test_unique_irq() {
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//// enable reg is not set
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// -> irq to be ignored
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// -> no core_interrupt
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// -> no entry in pending reg
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// generate interrupt pulse (note: 1 is lowest usable register)
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global_interrupts_o[2].write(true);
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wait(10_ns);
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global_interrupts_o[2].write(false);
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wait(10_ns);
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reg_check(PLIC_PENDING_REG, 0x0);
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wait(10_ns);
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reg_check(PLIC_CLAIM_COMPLETE_REG, 0x0);
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wait(10_ns);
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//// enable reg is set, then
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// -> pending bit change expected
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// -> core_interrupt expected
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read_bus(PLIC_PRIO1_REG);
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wait(10_ns);
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// enable single interrupt
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write_bus(PLIC_PRIO1_REG, 0x1);
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wait(10_ns);
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write_bus(PLIC_ENABLE_REG, 0x2);
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wait(10_ns);
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// generate interrupt pulse (note: 1 is lowest usable register)
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global_interrupts_o[1].write(true);
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wait(10_ns);
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global_interrupts_o[1].write(false);
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wait(10_ns);
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// read claim_complete register
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reg_check(PLIC_PENDING_REG, 0x2);
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wait(10_ns);
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reg_check(PLIC_CLAIM_COMPLETE_REG, 0x1);
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wait(10_ns);
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//// after writing to claim_complete reg (per fw)
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// -> pending bit expected to be unset
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// -> enable bit expected to be set ... test with / without enable being set
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write_bus(PLIC_CLAIM_COMPLETE_REG, 0x1);
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wait(10_ns);
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reg_check(PLIC_PENDING_REG, 0x0);
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wait(10_ns);
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reg_check(PLIC_CLAIM_COMPLETE_REG, 0x0);
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wait(10_ns);
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// todo: remove wait statements once the tlm_initiator is in place
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// todo: evaluate error messages ... provide correct pass/fail verdict
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wait(100_ns);
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}
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void test_initiator::test_frequent_irq() {}
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void test_initiator::test_parallel_irq() {
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//// create three parallel global_int requests
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// -> read and clear bits one after the other
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// -> different priorities applied (reverse order)
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// -> correct priority handing expected
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// -> three core interrupts expected in total
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// reverse order priority configuration
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write_bus(PLIC_PRIO1_REG, 0x3);
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wait(10_ns);
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write_bus(PLIC_PRIO2_REG, 0x2);
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wait(10_ns);
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write_bus(PLIC_PRIO3_REG, 0x1);
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wait(10_ns);
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// enable all three interrupts
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write_bus(PLIC_ENABLE_REG, 0xE);
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wait(10_ns);
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// generate interrupt pulse (note: 1 is lowest usable register)
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global_interrupts_o[1].write(true);
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wait(10_ns);
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global_interrupts_o[1].write(false);
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wait(10_ns);
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global_interrupts_o[2].write(true);
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wait(10_ns);
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global_interrupts_o[2].write(false);
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wait(10_ns);
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global_interrupts_o[3].write(true);
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wait(10_ns);
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global_interrupts_o[3].write(false);
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wait(10_ns);
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// expect three pending registers
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reg_check(PLIC_PENDING_REG, 0xE);
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wait(10_ns);
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// expect lowest interrupt id to be highest int
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reg_check(PLIC_CLAIM_COMPLETE_REG, 0x1);
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wait(10_ns);
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//// after writing to claim_complete reg (per fw)
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// -> next int to become highest irq
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write_bus(PLIC_CLAIM_COMPLETE_REG, 0x1);
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wait(10_ns);
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reg_check(PLIC_PENDING_REG, 0xC);
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wait(10_ns);
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reg_check(PLIC_CLAIM_COMPLETE_REG, 0x2);
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wait(10_ns);
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//// after writing to claim_complete reg again (per fw)
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// -> next int to become highest irq
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write_bus(PLIC_CLAIM_COMPLETE_REG, 0x2);
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wait(10_ns);
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reg_check(PLIC_PENDING_REG, 0x8);
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wait(10_ns);
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reg_check(PLIC_CLAIM_COMPLETE_REG, 0x3);
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wait(10_ns);
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//// after last writing to claim_complete reg again (per fw)
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// -> no further pending irq expected
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write_bus(PLIC_CLAIM_COMPLETE_REG, 0x3);
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wait(10_ns);
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reg_check(PLIC_PENDING_REG, 0x0);
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wait(10_ns);
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reg_check(PLIC_CLAIM_COMPLETE_REG, 0x0);
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wait(10_ns);
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// todo: advance upon register-write access ... remove above 10_ns waits
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// todo: evaluate error messages ... provide correct pass/fail verdict
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wait(100_ns);
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}
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void test_initiator::test_irq_stress() {}
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void test_initiator::write_bus(std::uint32_t adr, std::uint32_t dat) {
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tlm::tlm_generic_payload gp;
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std::array<uint8_t, 4> data;
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data[3] = 0xff & dat >> 24;
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data[2] = 0xff & dat >> 16;
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data[1] = 0xff & dat >> 8;
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data[0] = 0xff & dat;
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SCCDEBUG("test_initiator") << "write_bus(0x" << std::hex << adr << ") : " << dat;
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gp.set_command(tlm::TLM_WRITE_COMMAND);
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gp.set_address(adr);
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gp.set_data_ptr(data.data());
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gp.set_data_length(data.size());
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gp.set_streaming_width(4);
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sc_time delay;
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intor->b_transport(gp, delay);
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if (gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
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throw std::exception();
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}
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}
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std::uint32_t test_initiator::read_bus(std::uint32_t adr) {
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tlm::tlm_generic_payload gp;
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std::array<uint8_t, 4> data;
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gp.set_command(tlm::TLM_READ_COMMAND);
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gp.set_address(adr);
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gp.set_data_ptr(data.data());
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gp.set_data_length(data.size());
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gp.set_streaming_width(4);
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sc_time delay;
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intor->b_transport(gp, delay);
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if (gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
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// todo: improve output in case of exception, define own exception class to carry transaction-infos
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// ... i.e. out-of-range report with info about legal mem boundaries
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throw std::exception();
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}
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// todo: use reinterpret_cast instead
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std::uint32_t rdat = data[3] << 24 | data[2] << 16 | data[1] << 8 | data[0];
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SCCDEBUG("test_initiator") << "read_bus(0x" << std::hex << adr << ") -> " << rdat;
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return rdat;
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}
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void test_initiator::reg_check(std::uint32_t adr, std::uint32_t exp) {
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uint32_t dat = read_bus(adr);
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if (dat != exp) {
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SCCERR("test_initiator") << "register check failed for address 0x" << std::hex << adr << ": " << dat << " != " << exp;
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} else {
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SCCDEBUG("test_initiator") << "register check passed for address 0x" << std::hex << adr << ": " << dat;
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}
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}
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void test_initiator::core_irq_handler() {
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SCCDEBUG("test_initiator") << "core_interrupt_i edge detected -> " << core_interrupt_i.read();
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}
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} /* namespace sysc */
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