153 lines
6.5 KiB
C++
153 lines
6.5 KiB
C++
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#define SC_INCLUDE_DYNAMIC_PROCESSES
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#include "testbench.h"
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#include <factory.h>
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#include <tlm/scc/tlm_gp_shared.h>
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#include <catch2/catch_all.hpp>
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using namespace sc_core;
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factory::add<testbench> tb;
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bool operator==(tlm::tlm_generic_payload const& a, tlm::tlm_generic_payload const& b){
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auto ret = true;
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ret &= a.get_command() == b.get_command();
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ret &= a.get_address() == b.get_address();
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ret &= a.get_data_length() == b.get_data_length();
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for(auto i=0u; i<a.get_data_length(); ++i)
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ret &= a.get_data_ptr()[i] == b.get_data_ptr()[i];
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if(a.get_byte_enable_ptr() && b.get_byte_enable_ptr()) {
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ret &= a.get_byte_enable_length() == b.get_byte_enable_length();
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for(auto i=0u; i<a.get_byte_enable_length(); ++i)
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ret &= a.get_byte_enable_ptr()[i] == b.get_byte_enable_ptr()[i];
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}
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ret &= a.get_command() == b.get_command();
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if(!ret) SCCWARN()<<"Comparison failed: "<<a<<" and "<<b;
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return ret;
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}
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template<typename bus_cfg>
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tlm::tlm_generic_payload* prepare_trans(uint64_t start_address, size_t len, unsigned id_offs = 0,
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unsigned addr_offs = 0) {
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static uint8_t id{0};
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auto trans = tlm::scc::tlm_mm<>::get().allocate<axi::axi4_extension>(len);
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trans->set_address(start_address);
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tlm::scc::setId(*trans, id);
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auto ext = trans->get_extension<axi::axi4_extension>();
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trans->set_data_length(len);
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trans->set_streaming_width(len);
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ext->set_size(scc::ilog2(4));
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sc_assert(len < (bus_cfg::BUSWIDTH / 8) || len % (bus_cfg::BUSWIDTH / 8) == 0);
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auto length = (len * 8 - 1) / 32;
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if(start_address % (bus_cfg::BUSWIDTH / 8))
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length++;
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ext->set_length(length);
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// ext->set_burst(len * 8 > bus_cfg::buswidth ? axi::burst_e::INCR : axi::burst_e::FIXED);
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ext->set_burst(axi::burst_e::INCR);
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ext->set_id(id | id_offs);
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id = (id + 1) % 8;
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return trans;
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}
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inline void randomize(tlm::tlm_generic_payload& gp) {
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static uint8_t req_cnt{0};
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auto addr = gp.get_address();
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uint8_t const* src = reinterpret_cast<uint8_t const*>(&addr);
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for(size_t i = 0; i < gp.get_data_length(); ++i) {
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*(gp.get_data_ptr() + i) = i % 2 ? i : req_cnt;
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}
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req_cnt++;
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}
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TEST_CASE("pin level narrow burst", "[AXI][pin-level]") {
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struct {
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unsigned int ResetCycles{10};
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unsigned int BurstLengthByte{16};
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unsigned int NumberOfIterations{10};
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std::vector<tlm::scc::tlm_gp_shared_ptr> sent_read_tx, sent_write_tx;
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std::vector<tlm::scc::tlm_gp_shared_ptr> rcv_read_tx, rcv_write_tx;
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unsigned resp_cnt{0};
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} state;
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auto& dut = factory::get<testbench>();
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dut.tgt_pe.set_operation_cb([&state](axi::axi_protocol_types::tlm_payload_type& trans) -> unsigned {
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auto addr = trans.get_address();
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uint8_t const* src = reinterpret_cast<uint8_t const*>(&addr);
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for(size_t i = 0; i < trans.get_data_length(); ++i) {
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*(trans.get_data_ptr() + i) = i % 2 ? i : state.resp_cnt;
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}
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if(trans.is_read()) state.rcv_read_tx.emplace_back(&trans);
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if(trans.is_write()) state.rcv_write_tx.emplace_back(&trans);
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state.resp_cnt++;
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return 0;
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});
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dut.rst.write(false);
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sc_start(3*dut.clk.period());
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dut.rst.write(true);
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sc_start(3*dut.clk.period());
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auto run1 = sc_spawn([&dut, &state](){
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unsigned int StartAddr{0x20};
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for(int i = 0; i < state.NumberOfIterations; ++i) {
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SCCDEBUG("test") << "run0 executing transactions in iteration " << i;
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{ // 1
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tlm::scc::tlm_gp_shared_ptr trans = prepare_trans<testbench::bus_cfg>(StartAddr, state.BurstLengthByte);
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randomize(*trans);
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trans->set_command(tlm::TLM_READ_COMMAND);
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dut.intor_pe.transport(*trans, false);
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state.sent_read_tx.emplace_back(trans);
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if(trans->get_response_status() != tlm::TLM_OK_RESPONSE)
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SCCERR() << "Invalid response status" << trans->get_response_string();
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}
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StartAddr += state.BurstLengthByte;
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{ // 2
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tlm::scc::tlm_gp_shared_ptr trans = prepare_trans<testbench::bus_cfg>(StartAddr, state.BurstLengthByte);
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trans->set_command(tlm::TLM_WRITE_COMMAND);
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randomize(*trans);
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dut.intor_pe.transport(*trans, false);
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state.sent_read_tx.emplace_back(trans);
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if(trans->get_response_status() != tlm::TLM_OK_RESPONSE)
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SCCERR() << "Invalid response status" << trans->get_response_string();
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}
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StartAddr += state.BurstLengthByte;
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}
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});
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auto run2 = sc_spawn([&dut, &state](){
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unsigned int StartAddr{0x1020};
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for(int i = 0; i < state.NumberOfIterations; ++i) {
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SCCDEBUG("test") << "run1 executing transactions in iteration " << i;
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{ // 1
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tlm::scc::tlm_gp_shared_ptr trans = prepare_trans<testbench::bus_cfg>(StartAddr, state.BurstLengthByte, 0x8);
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randomize(*trans);
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trans->set_command(tlm::TLM_READ_COMMAND);
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dut.intor_pe.transport(*trans, false);
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state.sent_write_tx.emplace_back(trans);
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if(trans->get_response_status() != tlm::TLM_OK_RESPONSE)
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SCCERR() << "Invalid response status" << trans->get_response_string();
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}
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StartAddr += state.BurstLengthByte;
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{ // 2
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tlm::scc::tlm_gp_shared_ptr trans = prepare_trans<testbench::bus_cfg>(StartAddr, state.BurstLengthByte, 0x8);
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trans->set_command(tlm::TLM_WRITE_COMMAND);
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randomize(*trans);
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dut.intor_pe.transport(*trans, false);
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state.sent_write_tx.emplace_back(trans);
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if(trans->get_response_status() != tlm::TLM_OK_RESPONSE)
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SCCERR() << "Invalid response status" << trans->get_response_string();
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}
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StartAddr += state.BurstLengthByte;
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}
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});
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sc_start(1000 * dut.clk.period());
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REQUIRE(run1.terminated());
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REQUIRE(run2.terminated());
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REQUIRE(state.resp_cnt==40);
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REQUIRE(state.sent_write_tx.size() == state.rcv_write_tx.size());
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for(auto i = 0; i<state.sent_write_tx.size(); ++i)
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CHECK(*state.sent_write_tx[i] == *state.rcv_write_tx[i]);
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REQUIRE(state.sent_read_tx.size() == state.rcv_read_tx.size());
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for(auto i = 0; i<state.sent_write_tx.size(); ++i)
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CHECK(*state.sent_read_tx[i] == *state.rcv_read_tx[i]);
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}
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