131 lines
4.6 KiB
C++
131 lines
4.6 KiB
C++
////////////////////////////////////////////////////////////////////////////////
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// Copyright (C) 2017, MINRES Technologies GmbH
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its contributors
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// may be used to endorse or promote products derived from this software
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// without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// Created on: Sun Sep 17 23:56:50 CEST 2017
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// * uart_regs.h Author: <RDL Generator>
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//
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////////////////////////////////////////////////////////////////////////////////
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#ifndef _UART_REGS_H_
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#define _UART_REGS_H_
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#include <util/bit_field.h>
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#include <sysc/register.h>
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#include <sysc/tlmtarget.h>
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#include <sysc/utilities.h>
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namespace sysc {
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template<unsigned BUSWIDTH=32>
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class uart_regs :
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public sc_core::sc_module,
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public sysc::tlm_target<BUSWIDTH>,
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public sysc::resetable
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{
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protected:
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// storage declarations
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BEGIN_BF_DECL(txdata_t, uint32_t);
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BF_FIELD(data, 0, 8);
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BF_FIELD(full, 31, 1);
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END_BF_DECL() r_txdata;
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BEGIN_BF_DECL(rxdata_t, uint32_t);
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BF_FIELD(data, 0, 8);
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BF_FIELD(empty, 31, 1);
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END_BF_DECL() r_rxdata;
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BEGIN_BF_DECL(txctrl_t, uint32_t);
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BF_FIELD(txen, 0, 1);
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BF_FIELD(nstop, 1, 1);
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BF_FIELD(reserved, 2, 14);
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BF_FIELD(txcnt, 16, 3);
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END_BF_DECL() r_txctrl;
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BEGIN_BF_DECL(rxctrl_t, uint32_t);
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BF_FIELD(rxen, 0, 1);
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BF_FIELD(reserved, 1, 15);
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BF_FIELD(rxcnt, 16, 3);
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END_BF_DECL() r_rxctrl;
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BEGIN_BF_DECL(ie_t, uint32_t);
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BF_FIELD(txwm, 0, 1);
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BF_FIELD(rxwm, 1, 1);
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END_BF_DECL() r_ie;
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BEGIN_BF_DECL(ip_t, uint32_t);
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BF_FIELD(txwm, 0, 1);
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BF_FIELD(rxwm, 1, 1);
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END_BF_DECL() r_ip;
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BEGIN_BF_DECL(div_t, uint32_t);
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BF_FIELD(div, 0, 16);
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END_BF_DECL() r_div;
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// register declarations
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sysc::sc_register<typename txdata_t::StorageType> txdata;
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sysc::sc_register<typename rxdata_t::StorageType> rxdata;
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sysc::sc_register<typename txctrl_t::StorageType> txctrl;
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sysc::sc_register<typename rxctrl_t::StorageType> rxctrl;
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sysc::sc_register<typename ie_t::StorageType> ie;
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sysc::sc_register<typename ip_t::StorageType> ip;
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sysc::sc_register<typename div_t::StorageType> div;
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uart_regs(sc_core::sc_module_name nm);
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protected:
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sc_core::sc_time clk;
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};
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//////////////////////////////////////////////////////////////////////////////
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// member functions
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//////////////////////////////////////////////////////////////////////////////
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template<unsigned BUSWIDTH>
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uart_regs<BUSWIDTH>::uart_regs(sc_core::sc_module_name nm)
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: sc_core::sc_module(nm)
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, sysc::tlm_target<BUSWIDTH>(clk)
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, NAMED(txdata, r_txdata, 0, *this)
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, NAMED(rxdata, r_rxdata, 0, *this)
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, NAMED(txctrl, r_txctrl, 0, *this)
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, NAMED(rxctrl, r_rxctrl, 0, *this)
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, NAMED(ie, r_ie, 0, *this)
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, NAMED(ip, r_ip, 0, *this)
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, NAMED(div, r_div, 0, *this)
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{
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this->socket_map.addEntry(&txdata, 0x0UL, 0x4UL);
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this->socket_map.addEntry(&rxdata, 0x4UL, 0x4UL);
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this->socket_map.addEntry(&txctrl, 0x8UL, 0x4UL);
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this->socket_map.addEntry(&rxctrl, 0xcUL, 0x4UL);
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this->socket_map.addEntry(&ie, 0x10UL, 0x4UL);
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this->socket_map.addEntry(&ip, 0x14UL, 0x4UL);
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this->socket_map.addEntry(&div, 0x18UL, 0x4UL);
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}
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}
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#endif // _UART_REGS_H_
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