adds AXI4/ACEL unaligned addr burst tests
This commit is contained in:
parent
5490f0203f
commit
ea802247da
@ -14,7 +14,7 @@
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</extensions>
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</storageModule>
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<storageModule moduleId="cdtBuildSystem" version="4.0.0">
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<configuration artifactName="${ProjName}" buildProperties="" description="" id="cmake4eclipse.mbs.toolchain.cmake.134761605" name="Debug" optionalBuildProperties="org.eclipse.cdt.docker.launcher.containerbuild.property.selectedvolumes=,org.eclipse.cdt.docker.launcher.containerbuild.property.volumes=" parent="org.eclipse.cdt.build.core.emptycfg">
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<configuration artifactName="${ProjName}" buildProperties="" description="" id="cmake4eclipse.mbs.toolchain.cmake.134761605" name="Debug" optionalBuildProperties="org.eclipse.cdt.docker.launcher.containerbuild.property.volumes=,org.eclipse.cdt.docker.launcher.containerbuild.property.selectedvolumes=" parent="org.eclipse.cdt.build.core.emptycfg">
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<folderInfo id="cmake4eclipse.mbs.toolchain.cmake.134761605.1159094612" name="/" resourcePath="">
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<toolChain id="cmake4eclipse.mbs.toolchain.cmake.1883503430" name="CMake driven" superClass="cmake4eclipse.mbs.toolchain.cmake">
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<targetPlatform id="cmake4eclipse.mbs.targetPlatform.cmake.1279728098" name="Any Platform" superClass="cmake4eclipse.mbs.targetPlatform.cmake"/>
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2
scc
2
scc
@ -1 +1 @@
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Subproject commit e5439d3a32faaec0c1ac750c337597b48f855831
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Subproject commit bccc9269ff84181d1287dd6021ab5eb52f8909d0
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@ -24,7 +24,9 @@ void ABRThandler(int sig) { longjmp(abrt, 1); }
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int sc_main(int argc, char* argv[]) {
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signal(SIGABRT, ABRThandler);
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auto my_name = util::split(argv[0], '/').back();
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scc::init_logging(LogConfig().logLevel(getenv("SCC_TEST_VERBOSE") ? log::TRACE : log::FATAL).logAsync(false).msgTypeFieldWidth(35));
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auto level = getenv("SCC_TEST_VERBOSE");
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auto log_lvl = level ? static_cast<scc::log>(std::min(strtoul(level, nullptr, 10) + 4, 7UL)) : log::FATAL;
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scc::init_logging(LogConfig().logLevel(log_lvl).logAsync(false).msgTypeFieldWidth(35));
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// create tracer if environment variable SCC_TEST_TRACE is defined
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std::unique_ptr<scc::tracer> tracer;
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if(auto* test_trace = getenv("SCC_TEST_TRACE")) {
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@ -1,7 +1,7 @@
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project (axi4_pin_level)
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add_executable(${PROJECT_NAME}
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narrow_burst_test.cpp
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burst_test.cpp
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${test_util_SOURCE_DIR}/sc_main.cpp
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)
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target_link_libraries (${PROJECT_NAME} PUBLIC test_util)
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@ -11,6 +11,55 @@ using tlm_gp_shared_ptr_vec = std::vector<tlm::scc::tlm_gp_shared_ptr>;
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factory::add<testbench> tb;
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//// DataTransfer()
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//// ==============
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// void DataTransfer(uint64_t Start_Address, unsigned axsize, unsigned axlen, unsigned Data_Bus_Bytes, axi::burst_e Mode, bool IsWrite) {
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// auto Number_Bytes = 2u<<axsize;
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// auto Burst_Length = axlen+1;
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//// Data_Bus_Bytes is the number of 8-bit byte lanes in the bus
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//// Mode is the AXI transfer mode
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//// IsWrite is TRUE for a write, and FALSE for a read
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// auto addr = Start_Address; // Variable for current address
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// auto Aligned_Address = (unsigned(addr/Number_Bytes) * Number_Bytes);
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// auto aligned = (Aligned_Address == addr); // Check whether addr is aligned to nbytes
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// auto dtsize = Number_Bytes * Burst_Length; // Maximum total data transaction size
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// auto Lower_Wrap_Boundary = 0ULL;
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// auto Upper_Wrap_Boundary = 0ULL
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// if(Mode == axi::burst_e::WRAP){
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// Lower_Wrap_Boundary = (uint64_t(addr/dtsize) * dtsize);
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// // addr must be aligned for a wrapping burst
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// Upper_Wrap_Boundary = Lower_Wrap_Boundary + dtsize;
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// }
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// for(unsigned i=0; i<Burst_Length; ++i) {
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// auto n = i+1;
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// auto Lower_Byte_Lane = addr - (uint64_t(addr/Data_Bus_Bytes)) * Data_Bus_Bytes;
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// if(aligned){
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// auto Upper_Byte_Lane = Lower_Byte_Lane + Number_Bytes - 1;
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// } else {
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// auto Upper_Byte_Lane = Aligned_Address + Number_Bytes - 1
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// - (uint64_t(addr/Data_Bus_Bytes)) * Data_Bus_Bytes;
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// }
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// // Peform data transfer
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// if(IsWrite)
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// dwrite(addr, low_byte, high_byte);
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// else
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// dread(addr, low_byte, high_byte);
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// // Increment address if necessary
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// if(Mode != axi::burst_e::FIXED) {
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// if(aligned){
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// addr = addr + Number_Bytes;
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// if(Mode == axi::burst_e::WRAP){
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// // WRAP mode is always aligned
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// if(addr >= Upper_Wrap_Boundary) addr = Lower_Wrap_Boundary;
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// }
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// } else {
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// addr = Aligned_Address + Number_Bytes;
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// aligned = true; // All transfers after the first are aligned
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// }
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// }
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// }
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// return;
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// }
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bool is_equal(tlm::tlm_generic_payload const& a, tlm::tlm_generic_payload const& b) {
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auto ret = true;
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ret &= a.get_command() == b.get_command();
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@ -39,7 +88,9 @@ tlm::tlm_generic_payload* prepare_trans(uint64_t start_address, unsigned addr_in
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ext->set_size(scc::ilog2(width));
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sc_assert(len < (bus_cfg::BUSWIDTH / 8) || len % (bus_cfg::BUSWIDTH / 8) == 0);
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auto length = (len * 8 - 1) / (8 * width);
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if(width == (bus_cfg::BUSWIDTH / 8) && start_address % (bus_cfg::BUSWIDTH / 8))
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// if(width == (bus_cfg::BUSWIDTH / 8) && start_address % (bus_cfg::BUSWIDTH / 8))
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// length++;
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if(start_address % (bus_cfg::BUSWIDTH / 8) + width > (bus_cfg::BUSWIDTH / 8))
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length++;
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ext->set_length(length);
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// ext->set_burst(len * 8 > bus_cfg::buswidth ? axi::burst_e::INCR : axi::burst_e::FIXED);
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@ -82,7 +133,7 @@ template <typename STATE> unsigned run_scenario(STATE& state) {
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unsigned int StartAddr{0x0};
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for(int i = 0; i < state.NumberOfIterations; ++i) {
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tlm::scc::tlm_gp_shared_ptr trans =
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prepare_trans<testbench::bus_cfg>(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 1);
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prepare_trans<testbench::bus_cfg>(StartAddr + (state.unaligned ? 2 : 0), 4, state.BurstLengthByte, state.BurstSizeBytes, 1);
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trans->set_command(tlm::TLM_READ_COMMAND);
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SCCDEBUG("run1") << "iteration " << i << " TX: " << *trans;
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dut.intor_pe.transport(*trans, false);
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@ -95,7 +146,7 @@ template <typename STATE> unsigned run_scenario(STATE& state) {
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unsigned int StartAddr{0x2000};
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for(int i = 0; i < state.NumberOfIterations; ++i) {
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tlm::scc::tlm_gp_shared_ptr trans =
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prepare_trans<testbench::bus_cfg>(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 2);
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prepare_trans<testbench::bus_cfg>(StartAddr + (state.unaligned ? 2 : 0), 4, state.BurstLengthByte, state.BurstSizeBytes, 2);
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trans->set_command(tlm::TLM_WRITE_COMMAND);
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randomize(*trans);
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SCCDEBUG("run2") << "iteration " << i << " TX: " << *trans;
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@ -109,7 +160,7 @@ template <typename STATE> unsigned run_scenario(STATE& state) {
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unsigned int StartAddr{0x1000};
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for(int i = 0; i < state.NumberOfIterations; ++i) {
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tlm::scc::tlm_gp_shared_ptr trans =
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prepare_trans<testbench::bus_cfg>(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 3);
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prepare_trans<testbench::bus_cfg>(StartAddr + (state.unaligned ? 2 : 0), 4, state.BurstLengthByte, state.BurstSizeBytes, 3);
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trans->set_command(tlm::TLM_READ_COMMAND);
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SCCDEBUG("run3") << "iteration " << i << " TX: " << *trans;
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dut.intor_pe.transport(*trans, false);
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@ -122,7 +173,7 @@ template <typename STATE> unsigned run_scenario(STATE& state) {
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unsigned int StartAddr{0x3000};
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for(int i = 0; i < state.NumberOfIterations; ++i) {
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tlm::scc::tlm_gp_shared_ptr trans =
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prepare_trans<testbench::bus_cfg>(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 4);
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prepare_trans<testbench::bus_cfg>(StartAddr + (state.unaligned ? 2 : 0), 4, state.BurstLengthByte, state.BurstSizeBytes, 4);
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trans->set_command(tlm::TLM_WRITE_COMMAND);
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randomize(*trans);
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SCCDEBUG("run4") << "iteration " << i << " TX: " << *trans;
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@ -141,7 +192,8 @@ template <typename STATE> unsigned run_scenario(STATE& state) {
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return cycles;
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}
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void axi4_burst_alignment(bool pipelined_wrreq, bool write_bp) {
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void axi4_burst_alignment(bool pipelined_wrreq, bool write_bp, bool unaligned = false) {
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SCCINFO(__FUNCTION__) << "starting with pipelined_wrreq=" << pipelined_wrreq << " and write_bp=" << write_bp;
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struct {
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unsigned int ResetCycles{4};
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unsigned int BurstLengthByte{16};
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@ -150,8 +202,10 @@ void axi4_burst_alignment(bool pipelined_wrreq, bool write_bp) {
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std::unordered_map<unsigned, std::pair<tlm_gp_shared_ptr_vec, tlm_gp_shared_ptr_vec>> read_tx;
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std::unordered_map<unsigned, std::pair<tlm_gp_shared_ptr_vec, tlm_gp_shared_ptr_vec>> write_tx;
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unsigned resp_cnt{0};
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bool unaligned{false};
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} state;
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state.unaligned = unaligned;
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auto& dut = factory::get<testbench>();
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dut.intor_bfm.pipelined_wrreq = pipelined_wrreq;
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dut.tgt_pe.wr_data_accept_delay.set_value(write_bp ? 1 : 0);
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@ -176,13 +230,24 @@ void axi4_burst_alignment(bool pipelined_wrreq, bool write_bp) {
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auto const& recv_tx = e.second.second;
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REQUIRE(send_tx.size() == recv_tx.size());
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for(auto i = 0; i < send_tx.size(); ++i) {
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auto addr = send_tx[i]->get_address();
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if(addr % (testbench::bus_cfg::ADDRWIDTH / 8)) {
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CHECK(send_tx[i]->get_data_length() <= recv_tx[i]->get_data_length());
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CHECK(send_tx[i]->get_byte_enable_length() <= recv_tx[i]->get_byte_enable_length());
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// adjust the length of the read due to misalignment
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recv_tx[i]->set_data_length(send_tx[i]->get_data_length());
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recv_tx[i]->set_byte_enable_length(send_tx[i]->get_byte_enable_length());
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recv_tx[i]->set_streaming_width(send_tx[i]->get_streaming_width());
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}
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REQUIRE(send_tx[i]->get_response_status() == tlm::TLM_OK_RESPONSE);
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CHECK(is_equal(*send_tx[i], *recv_tx[i]));
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}
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}
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}
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void axi4_narrow_burst(bool pipelined_wrreq, bool write_bp) {
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void axi4_narrow_burst(bool pipelined_wrreq, bool write_bp, bool unaligned = false) {
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SCCINFO(__FUNCTION__) << "starting with pipelined_wrreq=" << pipelined_wrreq << ", write_bp = " << write_bp
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<< " and unaligned=" << unaligned;
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struct {
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unsigned int ResetCycles{4};
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unsigned int BurstLengthByte{16};
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@ -191,8 +256,10 @@ void axi4_narrow_burst(bool pipelined_wrreq, bool write_bp) {
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std::unordered_map<unsigned, std::pair<tlm_gp_shared_ptr_vec, tlm_gp_shared_ptr_vec>> read_tx;
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std::unordered_map<unsigned, std::pair<tlm_gp_shared_ptr_vec, tlm_gp_shared_ptr_vec>> write_tx;
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unsigned resp_cnt{0};
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bool unaligned{false};
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} state;
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state.unaligned = unaligned;
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auto& dut = factory::get<testbench>();
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dut.intor_bfm.pipelined_wrreq = pipelined_wrreq;
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dut.tgt_pe.wr_data_accept_delay.set_value(write_bp ? 1 : 0);
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@ -221,16 +288,32 @@ void axi4_narrow_burst(bool pipelined_wrreq, bool write_bp) {
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TEST_CASE("axi4_burst_alignment", "[AXI][pin-level]") { axi4_burst_alignment(false, false); }
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TEST_CASE("axi4_burst_alignment_unaligned_addr", "[AXI][pin-level]") { axi4_burst_alignment(false, false, true); }
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TEST_CASE("axi4_narrow_burst", "[AXI][pin-level]") { axi4_narrow_burst(false, false); }
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// TEST_CASE("axi4_narrow_burst_unaligned_addr", "[AXI][pin-level]") { axi4_narrow_burst(false, false, true); }
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TEST_CASE("axi4_burst_alignment_with_bp", "[AXI][pin-level]") { axi4_burst_alignment(false, true); }
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TEST_CASE("axi4_burst_alignment_with_bp_unaligned_addr", "[AXI][pin-level]") { axi4_burst_alignment(false, true, true); }
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TEST_CASE("axi4_narrow_burst_with_bp", "[AXI][pin-level]") { axi4_narrow_burst(false, true); }
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// TEST_CASE("axi4_narrow_burst_with_bp_unaligned_addr", "[AXI][pin-level]") { axi4_narrow_burst(false, true, true); }
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TEST_CASE("axi4_burst_alignment_pipelined_write", "[AXI][pin-level]") { axi4_burst_alignment(true, false); }
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TEST_CASE("axi4_burst_alignment_pipelined_write_unaligned_addr", "[AXI][pin-level]") { axi4_burst_alignment(true, false, true); }
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TEST_CASE("axi4_narrow_burst_pipelined_write", "[AXI][pin-level]") { axi4_narrow_burst(true, false); }
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// TEST_CASE("axi4_narrow_burst_pipelined_write_unaligned_addr", "[AXI][pin-level]") { axi4_narrow_burst(true, false, true); }
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TEST_CASE("axi4_burst_alignment_pipelined_write_with_bp", "[AXI][pin-level]") { axi4_burst_alignment(true, true); }
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TEST_CASE("axi4_burst_alignment_pipelined_write_with_bp_unaligned_addr", "[AXI][pin-level]") { axi4_burst_alignment(true, true, true); }
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TEST_CASE("axi4_narrow_burst_pipelined_write_with_bp", "[AXI][pin-level]") { axi4_narrow_burst(true, true); }
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// TEST_CASE("axi4_narrow_burst_pipelined_write_with_bp_unaligned_addr", "[AXI][pin-level]") { axi4_narrow_burst(true, true, true); }
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116
tests/axi4_pin_level/waves.gtkw
Normal file
116
tests/axi4_pin_level/waves.gtkw
Normal file
@ -0,0 +1,116 @@
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[*]
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[*] GTKWave Analyzer v3.3.118 (w)1999-2023 BSI
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[*] Wed Jan 8 16:33:12 2025
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[*]
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[dumpfile] "/scratch/eyck/workarea/MINRES/SystemC-Components-Test/axi4_pin_level.fst"
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[dumpfile_mtime] "Wed Jan 8 16:32:32 2025"
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[dumpfile_size] 7261
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[savefile] "/scratch/eyck/workarea/MINRES/SystemC-Components-Test/tests/axi4_pin_level/waves.gtkw"
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[timestart] 0
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[size] 2560 1288
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[pos] -1 -1
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*-20.062529 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[treeopen] testbench.
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[sst_width] 304
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[signals_width] 243
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[sst_expanded] 1
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[sst_vpaned_height] 396
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@28
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testbench.clk
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testbench.rst
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@800200
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-ar
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@28
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testbench.ar_valid
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testbench.ar_ready
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@22
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testbench.ar_addr[31:0]
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@28
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testbench.ar_burst[1:0]
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@22
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testbench.ar_cache[3:0]
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testbench.ar_id[3:0]
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testbench.ar_len[7:0]
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@28
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testbench.ar_lock
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testbench.ar_prot[2:0]
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@22
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testbench.ar_qos[3:0]
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testbench.ar_region[3:0]
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@28
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testbench.ar_size[2:0]
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testbench.ar_user
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@1000200
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-ar
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@800200
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-r
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@28
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testbench.r_valid
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testbench.r_ready
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testbench.r_last
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@22
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testbench.r_data[63:0]
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testbench.r_id[3:0]
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@28
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testbench.r_resp[1:0]
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testbench.r_trace
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testbench.r_user
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@1000200
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-r
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@800200
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-aw
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@28
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testbench.aw_valid
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testbench.aw_ready
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@22
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testbench.aw_id[3:0]
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testbench.aw_addr[31:0]
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@28
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testbench.aw_burst[1:0]
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@22
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testbench.aw_cache[3:0]
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testbench.aw_len[7:0]
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@28
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testbench.aw_lock
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testbench.aw_prot[2:0]
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@22
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testbench.aw_qos[3:0]
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testbench.aw_region[3:0]
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@28
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testbench.aw_size[2:0]
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testbench.aw_user
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@1000200
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-aw
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@800200
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-w
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@29
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testbench.w_valid
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testbench.w_ready
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testbench.w_ack
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@23
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testbench.w_data[63:0]
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testbench.w_id[3:0]
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@29
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testbench.w_last
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@23
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testbench.w_strb[7:0]
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@29
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testbench.w_trace
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testbench.w_user
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@1000200
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-w
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@800200
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-b
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@28
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testbench.b_valid
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testbench.b_ready
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@22
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testbench.b_id[3:0]
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@28
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testbench.b_resp[1:0]
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testbench.b_trace
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testbench.b_user
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@1000200
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-b
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[pattern_trace] 1
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[pattern_trace] 0
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@ -2,12 +2,12 @@
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#define SC_INCLUDE_DYNAMIC_PROCESSES
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#include <sysc/kernel/sc_simcontext.h>
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||||
#endif
|
||||
#include <array>
|
||||
#include <catch2/catch_all.hpp>
|
||||
#include <factory.h>
|
||||
#include <scc/cci_param_restricted.h>
|
||||
#include <scc/utilities.h>
|
||||
#include <systemc>
|
||||
|
||||
using namespace sc_core;
|
||||
|
||||
struct top : public sc_core::sc_module {
|
||||
|
||||
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Reference in New Issue
Block a user