SystemC/SystemC-Components-Test
8
0
Fork 0
Code Issues Pull Requests Projects 1 Releases Wiki Activity

Updated source to test LevelDB and fit to latest sc-components

Browse Source
This commit is contained in:
Eyck Jentzsch
2018-11-04 13:43:58 +01:00
parent 4e4da25eea
commit e911ce6581
20 changed files with 179 additions and 233 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
examples/simple_system/CMakeLists.txt
View File

@ -17,6 +17,7 @@ target_link_libraries (simple_system LINK_PUBLIC sc-components)
target_link_libraries (simple_system LINK_PUBLIC ${SystemC_LIBRARIES})
target_link_libraries (simple_system LINK_PUBLIC ${SCV_LIBRARIES})
target_link_libraries (simple_system LINK_PUBLIC ${Boost_LIBRARIES} )
target_link_libraries (simple_system LINK_PUBLIC ${CONAN_LIBS_LEVELDB})
target_link_libraries (simple_system LINK_PUBLIC ${CMAKE_THREAD_LIBS_INIT})
target_link_libraries (simple_system LINK_PUBLIC ${ZLIB_LIBRARY})
target_link_libraries (simple_system LINK_PUBLIC ${CMAKE_DL_LIBS})

8
examples/simple_system/gen/e300_plat_t.h
View File

@ -18,10 +18,10 @@
// need double braces, see
// https://stackoverflow.com/questions/6893700/how-to-construct-stdarray-object-with-initializer-list#6894191
const std::array<scc::target_memory_map_entry<32>, 4> e300_plat_map = {{
{&i_plic, 0x0c000000, 0x200008},
{&i_gpio, 0x10012000, 0x1000},
{&i_uart, 0x10013000, 0x1000},
{&i_spi, 0x10014000, 0x1000},
{i_plic.socket, 0x0c000000, 0x200008},
{i_gpio.socket, 0x10012000, 0x1000},
{i_uart.socket, 0x10013000, 0x1000},
{i_spi.socket, 0x10014000, 0x1000},
}};
#endif /* _E300_PLAT_MAP_H_ */

28
examples/simple_system/gpio.cpp
View File

@ -42,8 +42,10 @@
namespace sysc {
gpio::gpio(sc_core::sc_module_name nm)
: sc_core::sc_module(nm)
using namespace sc_core;
gpio::gpio(sc_module_name nm)
: sc_module(nm)
, tlm_target<>(clk)
, NAMED(clk_i)
, NAMED(rst_i)
@ -53,7 +55,7 @@ gpio::gpio(sc_core::sc_module_name nm)
, NAMED(iof1_o, 32)
, NAMED(iof0_i, 32)
, NAMED(iof1_i, 32)
, NAMEDD(gpio_regs, regs)
, NAMEDD(regs, gpio_regs)
{
regs->registerResources(*this);
SC_METHOD(clock_cb);
@ -62,7 +64,7 @@ gpio::gpio(sc_core::sc_module_name nm)
sensitive << rst_i;
dont_initialize();
auto pins_i_cb =[this](unsigned int tag, tlm::tlm_signal_gp<>& gp,
tlm::tlm_phase& phase, sc_core::sc_time& delay)->tlm::tlm_sync_enum{
tlm::tlm_phase& phase, sc_time& delay)->tlm::tlm_sync_enum{
this->pin_input(tag, gp, delay);
return tlm::TLM_COMPLETED;
};
@ -72,7 +74,7 @@ gpio::gpio(sc_core::sc_module_name nm)
++i;
}
auto iof0_i_cb =[this](unsigned int tag, tlm::tlm_signal_gp<>& gp,
tlm::tlm_phase& phase, sc_core::sc_time& delay)->tlm::tlm_sync_enum{
tlm::tlm_phase& phase, sc_time& delay)->tlm::tlm_sync_enum{
last_iof0[tag]=gp.get_value();
this->iof_input(tag, 0, gp, delay);
return tlm::TLM_COMPLETED;
@ -83,7 +85,7 @@ gpio::gpio(sc_core::sc_module_name nm)
++i;
}
auto iof1_i_cb =[this](unsigned int tag, tlm::tlm_signal_gp<>& gp,
tlm::tlm_phase& phase, sc_core::sc_time& delay)->tlm::tlm_sync_enum{
tlm::tlm_phase& phase, sc_time& delay)->tlm::tlm_sync_enum{
last_iof1[tag]=gp.get_value();
this->iof_input(tag, 1, gp, delay);
return tlm::TLM_COMPLETED;
@ -93,7 +95,7 @@ gpio::gpio(sc_core::sc_module_name nm)
s.register_nb_transport(iof1_i_cb, i);
++i;
}
auto update_pins_cb = [this](scc::sc_register<uint32_t> &reg, uint32_t data, sc_core::sc_time d) -> bool {
auto update_pins_cb = [this](scc::sc_register<uint32_t> &reg, uint32_t data, sc_time d) -> bool {
if (!this->regs->in_reset()) {
auto changed_bits = (reg.get()^data);
reg.put(data);
@ -124,7 +126,7 @@ void gpio::clock_cb() {
}
tlm::tlm_phase gpio::write_output(tlm::tlm_signal_gp<bool>& gp, size_t i, bool val) {
sc_core::sc_time delay{SC_ZERO_TIME};
sc_time delay{SC_ZERO_TIME};
tlm::tlm_phase phase{ tlm::BEGIN_REQ };
gp.set_command(tlm::TLM_WRITE_COMMAND);
gp.set_response_status(tlm::TLM_OK_RESPONSE);
@ -134,7 +136,7 @@ tlm::tlm_phase gpio::write_output(tlm::tlm_signal_gp<bool>& gp, size_t i, bool v
}
void gpio::update_pins(uint32_t changed_bits) {
sc_core::sc_inout_rv<32>::data_type out_val;
sc_inout_rv<32>::data_type out_val;
tlm::tlm_signal_gp<bool> gp;
bool val;
for(size_t i=0, mask = 1; i<32; ++i, mask<<=1){
@ -157,7 +159,7 @@ void gpio::update_pins(uint32_t changed_bits) {
}
}
void gpio::pin_input(unsigned int tag, tlm::tlm_signal_gp<bool>& gp, sc_core::sc_time& delay) {
void gpio::pin_input(unsigned int tag, tlm::tlm_signal_gp<bool>& gp, sc_time& delay) {
if(delay>SC_ZERO_TIME){
wait(delay);
delay=SC_ZERO_TIME;
@ -182,7 +184,7 @@ void gpio::forward_pin_input(unsigned int tag, tlm::tlm_signal_gp<bool>& gp) {
auto& socket = regs->iof_sel&mask?iof1_o[tag]:iof0_o[tag];
tlm::tlm_signal_gp<> new_gp;
for(size_t i=0; i<socket.size(); ++i){
sc_core::sc_time delay{SC_ZERO_TIME};
sc_time delay{SC_ZERO_TIME};
tlm::tlm_phase phase{tlm::BEGIN_REQ};
new_gp.set_command(tlm::TLM_WRITE_COMMAND);
new_gp.set_response_status(tlm::TLM_OK_RESPONSE);
@ -193,7 +195,7 @@ void gpio::forward_pin_input(unsigned int tag, tlm::tlm_signal_gp<bool>& gp) {
}
}
void gpio::iof_input(unsigned int tag, unsigned iof_idx, tlm::tlm_signal_gp<>& gp, sc_core::sc_time& delay) {
void gpio::iof_input(unsigned int tag, unsigned iof_idx, tlm::tlm_signal_gp<>& gp, sc_time& delay) {
if(delay>SC_ZERO_TIME){
wait(delay);
delay=SC_ZERO_TIME;
@ -204,7 +206,7 @@ void gpio::iof_input(unsigned int tag, unsigned iof_idx, tlm::tlm_signal_gp<>& g
if(iof_idx == idx){
auto& socket = pins_o[tag];
for(size_t i=0; i<socket.size(); ++i){
sc_core::sc_time delay{SC_ZERO_TIME};
sc_time delay{SC_ZERO_TIME};
tlm::tlm_phase phase{tlm::BEGIN_REQ};
tlm::tlm_signal_gp<> new_gp;
new_gp.set_command(tlm::TLM_WRITE_COMMAND);

10
examples/simple_system/plic.cpp
View File

@ -50,7 +50,7 @@ plic::plic(sc_core::sc_module_name nm)
, NAMED(rst_i)
, NAMED(global_interrupts_i, 256)
, NAMED(core_interrupt_o)
, NAMEDD(plic_regs, regs)
, NAMEDD(regs, plic_regs)
{
regs->registerResources(*this);
@ -120,7 +120,7 @@ void plic::global_int_port_cb() {
if (enable && global_interrupts_i[i].read() == 1) {
regs->r_pending = regs->r_pending | (0x1 << i);
LOG(INFO) << "pending interrupt identified: " << i;
SCDEBUG("plic") << "pending interrupt identified: " << i;
}
}
@ -148,7 +148,7 @@ void plic::handle_pending_int() {
claim_prio = prio;
claim_int = i;
raise_int = 1;
LOG(INFO) << "pending interrupt activated: " << i;
SCDEBUG("plic") << "pending interrupt activated: " << i;
}
}
}
@ -159,14 +159,14 @@ void plic::handle_pending_int() {
// todo: evluate clock period
} else {
regs->r_claim_complete = 0;
LOG(INFO) << "no further pending interrupt.";
SCDEBUG("plic") << "no further pending interrupt.";
}
}
void plic::reset_pending_int(uint32_t irq) {
// todo: evaluate enable register (see spec)
// todo: make sure that pending is set, otherwise don't reset irq ... read spec.
LOG(INFO) << "reset pending interrupt: " << irq;
SCDEBUG("plic") << "reset pending interrupt: " << irq;
// reset related pending bit
regs->r_pending &= ~(0x1 << irq);
core_interrupt_o.write(0);

2
examples/simple_system/simple_system.cpp
View File

@ -44,7 +44,7 @@ simple_system::simple_system(sc_core::sc_module_name nm)
i_master.intor(i_router.target[0]);
size_t i = 0;
for (const auto &e : e300_plat_map) {
i_router.initiator[i](e.target->socket);
i_router.initiator[i](e.target);
i_router.add_target_range(i, e.start, e.size);
i++;
}

2
examples/simple_system/simple_system.h
View File

@ -48,7 +48,7 @@ public:
sc_core::sc_signal<sc_core::sc_time> s_clk;
sc_core::sc_signal<bool> s_rst;
sc_core::sc_vector<sc_core::sc_signal<bool>> s_global_interrupts;
sc_core::sc_signal<bool> s_core_interrupt;
sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS> s_core_interrupt;
sc_core::sc_vector<tlm::tlm_signal<>> s_gpio;
simple_system(sc_core::sc_module_name nm);

2
examples/simple_system/spi.cpp
View File

@ -25,7 +25,7 @@ spi::spi(sc_core::sc_module_name nm)
, tlm_target<>(clk)
, NAMED(clk_i)
, NAMED(rst_i)
, NAMEDD(spi_regs, regs) {
, NAMEDD(regs, spi_regs) {
regs->registerResources(*this);
SC_METHOD(clock_cb);
sensitive << clk_i;

22
examples/simple_system/test_initiator.cpp
View File

@ -36,8 +36,10 @@
#define PLIC_CLAIM_COMPLETE_REG 0x0C200004
namespace sysc {
test_initiator::test_initiator(sc_core::sc_module_name nm)
: sc_core::sc_module(nm)
using namespace sc_core;
test_initiator::test_initiator(sc_module_name nm)
: sc_module(nm)
, NAMED(intor)
, NAMED(rst_i)
, NAMED(global_interrupts_o, 256)
@ -62,6 +64,8 @@ void test_initiator::run() {
test_irq_stress();
// todo: review irq sequences from FW point of view ... expected ???
wait(100_ns);
sc_stop();
}
void test_initiator::test_unique_irq() {
@ -211,14 +215,14 @@ void test_initiator::write_bus(std::uint32_t adr, std::uint32_t dat) {
data[1] = 0xff & dat >> 8;
data[0] = 0xff & dat;
LOG(INFO) << "write_bus(0x" << std::hex << adr << ") : " << dat;
SCDEBUG("test_initiator") << "write_bus(0x" << std::hex << adr << ") : " << dat;
gp.set_command(tlm::TLM_WRITE_COMMAND);
gp.set_address(adr);
gp.set_data_ptr(data.data());
gp.set_data_length(data.size());
gp.set_streaming_width(4);
sc_core::sc_time delay;
sc_time delay;
intor->b_transport(gp, delay);
if (gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
@ -236,7 +240,7 @@ std::uint32_t test_initiator::read_bus(std::uint32_t adr) {
gp.set_data_ptr(data.data());
gp.set_data_length(data.size());
gp.set_streaming_width(4);
sc_core::sc_time delay;
sc_time delay;
intor->b_transport(gp, delay);
if (gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
@ -248,21 +252,21 @@ std::uint32_t test_initiator::read_bus(std::uint32_t adr) {
// todo: use reinterpret_cast instead
std::uint32_t rdat = data[3] << 24 | data[2] << 16 | data[1] << 8 | data[0];
LOG(INFO) << "read_bus(0x" << std::hex << adr << ") -> " << rdat;
SCDEBUG("test_initiator") << "read_bus(0x" << std::hex << adr << ") -> " << rdat;
return rdat;
}
void test_initiator::reg_check(std::uint32_t adr, std::uint32_t exp) {
uint32_t dat = read_bus(adr);
if (dat != exp) {
LOG(ERROR) << "register check failed for address 0x" << std::hex << adr << ": " << dat << " != " << exp;
SCERR("test_initiator") << "register check failed for address 0x" << std::hex << adr << ": " << dat << " != " << exp;
} else {
LOG(INFO) << "register check passed for address 0x" << std::hex << adr << ": " << dat;
SCDEBUG("test_initiator") << "register check passed for address 0x" << std::hex << adr << ": " << dat;
}
}
void test_initiator::core_irq_handler() {
LOG(INFO) << "core_interrupt_i edge detected -> " << core_interrupt_i.read();
SCDEBUG("test_initiator") << "core_interrupt_i edge detected -> " << core_interrupt_i.read();
}
} /* namespace sysc */

2
examples/simple_system/uart.cpp
View File

@ -25,7 +25,7 @@ uart::uart(sc_core::sc_module_name nm)
, tlm_target<>(clk)
, NAMED(clk_i)
, NAMED(rst_i)
, NAMEDD(uart_regs, regs) {
, NAMEDD(regs, uart_regs) {
regs->registerResources(*this);
SC_METHOD(clock_cb);
sensitive << clk_i;

1
examples/transaction_recording/CMakeLists.txt
View File

@ -11,6 +11,7 @@ target_link_libraries (transaction_recording LINK_PUBLIC sc-components)
target_link_libraries (transaction_recording LINK_PUBLIC ${SystemC_LIBRARIES})
target_link_libraries (transaction_recording LINK_PUBLIC ${SCV_LIBRARIES})
target_link_libraries (transaction_recording LINK_PUBLIC ${Boost_LIBRARIES} )
target_link_libraries (transaction_recording LINK_PUBLIC ${CONAN_LIBS_LEVELDB})
target_link_libraries (transaction_recording LINK_PUBLIC ${ZLIB_LIBRARIES} )
target_link_libraries (transaction_recording LINK_PUBLIC ${CMAKE_THREAD_LIBS_INIT})
target_link_libraries (transaction_recording LINK_PUBLIC ${CMAKE_DL_LIBS})

51
examples/transaction_recording/scv_tr_recording_example.cpp
View File

@ -19,11 +19,11 @@
#include "scc/scv_tr_db.h"
#include "scc/report.h"
//47ms #define SQLITE_DB
//27ms
#define CTXT_DB
//29ms #define BINARY_DB
//27ms TEXT_DB
// text 11308µs/11602µs
// compressed 10365µs/ 9860µs
// binary 13233µs/10698µs
// SQLite 30363µs/30018µs
// LeveDB 23898µs/22367µs
// hack to fake a true fifo_mutex
#define fifo_mutex sc_mutex
@ -330,25 +330,38 @@ inline void design::data_phase() {
}
}
inline const char* init_db(char type){
switch(type){
case '2':
scv_tr_compressed_init();
return "my_db.txlog";
break;
case '3':
scv_tr_binary_init();
return "my_db.txb";
break;
case '4':
scv_tr_sqlite_init();
return "my_db.txdb";
break;
case '5':
scv_tr_ldb_init();
return "my_db.txldb";
break;
default:
scv_tr_text_init();
return "my_db.txlog";
break;
}
}
int sc_main(int argc, char *argv[]) {
auto start = std::chrono::system_clock::now();
scv_startup();
scc::init_logging(logging::INFO);
LOGGER(SystemC)::print_time() = false;
#if defined(BINARY_DB)
scv_tr_binary_init();
const char *fileName = "my_db";
#elif defined(CTXT_DB)
scv_tr_compressed_init();
const char* fileName = "my_db.txlog";
#elif defined(SQLITE_DB)
scv_tr_sqlite_init();
const char* fileName = "my_db.txdb";
#else
scv_tr_text_init();
const char* fileName = "my_db.txlog";
#endif
const char *fileName = argc==2? init_db(argv[1][0]): "my_db.txlog";
if(argc<2) scv_tr_text_init();
scv_tr_db db(fileName);
scv_tr_db::set_default_db(&db);
sc_trace_file *tf = sc_create_vcd_trace_file("my_db");