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Fixed code generation to use sc_register_indexed

This commit is contained in:
Eyck Jentzsch 2017-09-20 22:34:51 +02:00
parent e719dc1118
commit e332ef87c1
4 changed files with 9 additions and 9 deletions
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4
examples/simple_system/gen/plic_regs.h
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@ -28,7 +28,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Created on: Wed Sep 20 11:47:24 CEST 2017
// Created on: Wed Sep 20 22:30:45 CEST 2017
// * plic_regs.h Author: <RDL Generator>
//
////////////////////////////////////////////////////////////////////////////////
@ -65,7 +65,7 @@ protected:
uint32_t r_claim_complete;
// register declarations
sysc::sc_register_field<priority_t, 255> priority;
sysc::sc_register_indexed<priority_t, 255> priority;
sysc::sc_register<uint32_t> pending;
sysc::sc_register<uint32_t> enabled;
sysc::sc_register<threshold_t> threshold;

2
examples/simple_system/gen/spi_regs.h
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@ -28,7 +28,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Created on: Wed Sep 20 11:47:24 CEST 2017
// Created on: Wed Sep 20 22:30:45 CEST 2017
// * spi_regs.h Author: <RDL Generator>
//
////////////////////////////////////////////////////////////////////////////////

2
examples/simple_system/gen/uart_regs.h
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@ -28,7 +28,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Created on: Wed Sep 20 11:47:24 CEST 2017
// Created on: Wed Sep 20 22:30:45 CEST 2017
// * uart_regs.h Author: <RDL Generator>
//
////////////////////////////////////////////////////////////////////////////////

2
sc-components

@ -1 +1 @@
Subproject commit 0ae9ca921a3c59f7f5e0cad119314e65bd50c327
Subproject commit 4bc26642e349906f6e81619ea8a26bf533c3f46f