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adds AXI4 pin level test and moves all tests to automatic discovery

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This commit is contained in:
Eyck Jentzsch
2022-10-03 11:08:39 +02:00
parent b68b8c3045
commit e0c3e3d898
6 changed files with 62 additions and 31 deletions
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3
tests/axi4_pin_level/CMakeLists.txt
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@ -6,5 +6,4 @@ add_executable(${PROJECT_NAME}
)
target_link_libraries (${PROJECT_NAME} PUBLIC test_util)
add_test(NAME narrow_burst COMMAND ${PROJECT_NAME})
#catch_discover_tests(${PROJECT_NAME})
catch_discover_tests(${PROJECT_NAME})

50
tests/axi4_pin_level/narrow_burst_test.cpp
View File

@ -29,7 +29,7 @@ bool operator==(tlm::tlm_generic_payload const& a, tlm::tlm_generic_payload cons
}
template<typename bus_cfg>
tlm::tlm_generic_payload* prepare_trans(uint64_t start_address, unsigned len, unsigned width, unsigned id_offs) {
tlm::tlm_generic_payload* prepare_trans(uint64_t start_address, unsigned addr_incr, unsigned len, unsigned width, unsigned id_offs) {
static uint8_t id{0};
auto trans = tlm::scc::tlm_mm<>::get().allocate<axi::axi4_extension>(len);
trans->set_address(start_address);
@ -39,7 +39,7 @@ tlm::tlm_generic_payload* prepare_trans(uint64_t start_address, unsigned len, un
trans->set_streaming_width(len);
ext->set_size(scc::ilog2(width));
sc_assert(len < (bus_cfg::BUSWIDTH / 8) || len % (bus_cfg::BUSWIDTH / 8) == 0);
auto length = (len * 8 - 1) / 32;
auto length = (len * 8 - 1) / (8*width);
if(width==(bus_cfg::BUSWIDTH / 8) && start_address % (bus_cfg::BUSWIDTH / 8))
length++;
ext->set_length(length);
@ -88,7 +88,7 @@ void run_scenario(STATE& state){
for(int i = 0; i < state.NumberOfIterations; ++i) {
SCCDEBUG(__FUNCTION__) << "run0 executing transactions in iteration " << i;
{ // 1
tlm::scc::tlm_gp_shared_ptr trans = prepare_trans<testbench::bus_cfg>(StartAddr, state.BurstLengthByte, state.BurstSizeBytes, 0);
tlm::scc::tlm_gp_shared_ptr trans = prepare_trans<testbench::bus_cfg>(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 0);
randomize(*trans);
trans->set_command(tlm::TLM_READ_COMMAND);
SCCDEBUG(__FUNCTION__)<<"TX: "<<*trans;
@ -99,7 +99,7 @@ void run_scenario(STATE& state){
SCCERR(__FUNCTION__) << "Invalid response status" << trans->get_response_string();
}
{ // 2
tlm::scc::tlm_gp_shared_ptr trans = prepare_trans<testbench::bus_cfg>(StartAddr, state.BurstLengthByte, state.BurstSizeBytes, 0);
tlm::scc::tlm_gp_shared_ptr trans = prepare_trans<testbench::bus_cfg>(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 0);
trans->set_command(tlm::TLM_WRITE_COMMAND);
randomize(*trans);
SCCDEBUG(__FUNCTION__)<<"TX: "<<*trans;
@ -118,7 +118,7 @@ void run_scenario(STATE& state){
for(int i = 0; i < state.NumberOfIterations; ++i) {
SCCDEBUG(__FUNCTION__) << "run1 executing transactions in iteration " << i;
{ // 1
tlm::scc::tlm_gp_shared_ptr trans = prepare_trans<testbench::bus_cfg>(StartAddr, state.BurstLengthByte, state.BurstSizeBytes, 0x8);
tlm::scc::tlm_gp_shared_ptr trans = prepare_trans<testbench::bus_cfg>(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 0x8);
randomize(*trans);
trans->set_command(tlm::TLM_READ_COMMAND);
SCCDEBUG(__FUNCTION__)<<"TX: "<<*trans;
@ -129,7 +129,7 @@ void run_scenario(STATE& state){
SCCERR(__FUNCTION__) << "Invalid response status" << trans->get_response_string();
}
{ // 2
tlm::scc::tlm_gp_shared_ptr trans = prepare_trans<testbench::bus_cfg>(StartAddr, state.BurstLengthByte, state.BurstSizeBytes, 0x8);
tlm::scc::tlm_gp_shared_ptr trans = prepare_trans<testbench::bus_cfg>(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 0x8);
trans->set_command(tlm::TLM_WRITE_COMMAND);
randomize(*trans);
SCCDEBUG(__FUNCTION__)<<"TX: "<<*trans;
@ -143,11 +143,47 @@ void run_scenario(STATE& state){
}
});
sc_start(120 * dut.clk.period());
REQUIRE(run1.terminated());
REQUIRE(run2.terminated());
}
TEST_CASE("pin level narrow burst", "[AXI][pin-level]") {
TEST_CASE("axi4_burst_alignment", "[AXI][pin-level]") {
struct {
unsigned int ResetCycles{4};
unsigned int BurstLengthByte{16};
unsigned int BurstSizeBytes{8};
unsigned int NumberOfIterations{8};
std::unordered_map<unsigned, std::pair<std::vector<tlm::scc::tlm_gp_shared_ptr>, std::vector<tlm::scc::tlm_gp_shared_ptr>>> read_tx;
std::unordered_map<unsigned, std::pair<std::vector<tlm::scc::tlm_gp_shared_ptr>, std::vector<tlm::scc::tlm_gp_shared_ptr>>> write_tx;
unsigned resp_cnt{0};
} state;
run_scenario(state);
REQUIRE(sc_report_handler::get_count(SC_ERROR) == 0);
REQUIRE(sc_report_handler::get_count(SC_WARNING) == 0);
REQUIRE(state.resp_cnt==4*state.NumberOfIterations);
for(auto& e: state.write_tx) {
auto const& send_tx = e.second.first;
auto const& recv_tx = e.second.second;
REQUIRE(send_tx.size() == recv_tx.size());
for(auto i = 0; i<send_tx.size(); ++i)
CHECK(*send_tx[i] == *recv_tx[i]);
}
for(auto& e: state.read_tx) {
auto const& send_tx = e.second.first;
auto const& recv_tx = e.second.second;
REQUIRE(send_tx.size() == recv_tx.size());
for(auto i = 0; i<send_tx.size(); ++i)
CHECK(*send_tx[i] == *recv_tx[i]);
}
}
TEST_CASE("axi4_narrow_burst", "[AXI][pin-level]") {
struct {
unsigned int ResetCycles{4};
unsigned int BurstLengthByte{16};