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@ -29,7 +29,7 @@ bool operator==(tlm::tlm_generic_payload const& a, tlm::tlm_generic_payload cons
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}
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template<typename bus_cfg>
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tlm::tlm_generic_payload* prepare_trans(uint64_t start_address, unsigned len, unsigned width, unsigned id_offs) {
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tlm::tlm_generic_payload* prepare_trans(uint64_t start_address, unsigned addr_incr, unsigned len, unsigned width, unsigned id_offs) {
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static uint8_t id{0};
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auto trans = tlm::scc::tlm_mm<>::get().allocate<axi::axi4_extension>(len);
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trans->set_address(start_address);
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@ -39,7 +39,7 @@ tlm::tlm_generic_payload* prepare_trans(uint64_t start_address, unsigned len, un
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trans->set_streaming_width(len);
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ext->set_size(scc::ilog2(width));
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sc_assert(len < (bus_cfg::BUSWIDTH / 8) || len % (bus_cfg::BUSWIDTH / 8) == 0);
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auto length = (len * 8 - 1) / 32;
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auto length = (len * 8 - 1) / (8*width);
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if(width==(bus_cfg::BUSWIDTH / 8) && start_address % (bus_cfg::BUSWIDTH / 8))
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length++;
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ext->set_length(length);
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@ -88,7 +88,7 @@ void run_scenario(STATE& state){
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for(int i = 0; i < state.NumberOfIterations; ++i) {
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SCCDEBUG(__FUNCTION__) << "run0 executing transactions in iteration " << i;
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{ // 1
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tlm::scc::tlm_gp_shared_ptr trans = prepare_trans<testbench::bus_cfg>(StartAddr, state.BurstLengthByte, state.BurstSizeBytes, 0);
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tlm::scc::tlm_gp_shared_ptr trans = prepare_trans<testbench::bus_cfg>(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 0);
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randomize(*trans);
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trans->set_command(tlm::TLM_READ_COMMAND);
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SCCDEBUG(__FUNCTION__)<<"TX: "<<*trans;
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@ -99,7 +99,7 @@ void run_scenario(STATE& state){
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SCCERR(__FUNCTION__) << "Invalid response status" << trans->get_response_string();
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}
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{ // 2
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tlm::scc::tlm_gp_shared_ptr trans = prepare_trans<testbench::bus_cfg>(StartAddr, state.BurstLengthByte, state.BurstSizeBytes, 0);
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tlm::scc::tlm_gp_shared_ptr trans = prepare_trans<testbench::bus_cfg>(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 0);
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trans->set_command(tlm::TLM_WRITE_COMMAND);
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randomize(*trans);
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SCCDEBUG(__FUNCTION__)<<"TX: "<<*trans;
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@ -118,7 +118,7 @@ void run_scenario(STATE& state){
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for(int i = 0; i < state.NumberOfIterations; ++i) {
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SCCDEBUG(__FUNCTION__) << "run1 executing transactions in iteration " << i;
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{ // 1
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tlm::scc::tlm_gp_shared_ptr trans = prepare_trans<testbench::bus_cfg>(StartAddr, state.BurstLengthByte, state.BurstSizeBytes, 0x8);
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tlm::scc::tlm_gp_shared_ptr trans = prepare_trans<testbench::bus_cfg>(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 0x8);
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randomize(*trans);
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trans->set_command(tlm::TLM_READ_COMMAND);
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SCCDEBUG(__FUNCTION__)<<"TX: "<<*trans;
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@ -129,7 +129,7 @@ void run_scenario(STATE& state){
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SCCERR(__FUNCTION__) << "Invalid response status" << trans->get_response_string();
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}
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{ // 2
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tlm::scc::tlm_gp_shared_ptr trans = prepare_trans<testbench::bus_cfg>(StartAddr, state.BurstLengthByte, state.BurstSizeBytes, 0x8);
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tlm::scc::tlm_gp_shared_ptr trans = prepare_trans<testbench::bus_cfg>(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 0x8);
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trans->set_command(tlm::TLM_WRITE_COMMAND);
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randomize(*trans);
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SCCDEBUG(__FUNCTION__)<<"TX: "<<*trans;
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@ -143,11 +143,47 @@ void run_scenario(STATE& state){
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}
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});
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sc_start(120 * dut.clk.period());
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REQUIRE(run1.terminated());
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REQUIRE(run2.terminated());
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}
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TEST_CASE("pin level narrow burst", "[AXI][pin-level]") {
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TEST_CASE("axi4_burst_alignment", "[AXI][pin-level]") {
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struct {
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unsigned int ResetCycles{4};
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unsigned int BurstLengthByte{16};
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unsigned int BurstSizeBytes{8};
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unsigned int NumberOfIterations{8};
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std::unordered_map<unsigned, std::pair<std::vector<tlm::scc::tlm_gp_shared_ptr>, std::vector<tlm::scc::tlm_gp_shared_ptr>>> read_tx;
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std::unordered_map<unsigned, std::pair<std::vector<tlm::scc::tlm_gp_shared_ptr>, std::vector<tlm::scc::tlm_gp_shared_ptr>>> write_tx;
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unsigned resp_cnt{0};
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} state;
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run_scenario(state);
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REQUIRE(sc_report_handler::get_count(SC_ERROR) == 0);
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REQUIRE(sc_report_handler::get_count(SC_WARNING) == 0);
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REQUIRE(state.resp_cnt==4*state.NumberOfIterations);
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for(auto& e: state.write_tx) {
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auto const& send_tx = e.second.first;
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auto const& recv_tx = e.second.second;
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REQUIRE(send_tx.size() == recv_tx.size());
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for(auto i = 0; i<send_tx.size(); ++i)
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CHECK(*send_tx[i] == *recv_tx[i]);
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}
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for(auto& e: state.read_tx) {
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auto const& send_tx = e.second.first;
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auto const& recv_tx = e.second.second;
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REQUIRE(send_tx.size() == recv_tx.size());
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for(auto i = 0; i<send_tx.size(); ++i)
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CHECK(*send_tx[i] == *recv_tx[i]);
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}
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}
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TEST_CASE("axi4_narrow_burst", "[AXI][pin-level]") {
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struct {
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unsigned int ResetCycles{4};
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unsigned int BurstLengthByte{16};
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