SystemC/SystemC-Components-Test
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update scc, add minimal test for ordered_semaphore

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This commit is contained in:
Eyck Jentzsch
2020-05-26 12:35:53 +02:00
parent d3da1aefcf
commit ae5ba9ca8e
9 changed files with 144 additions and 24 deletions
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8
examples/simple_system/plic.cpp
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@@ -119,7 +119,7 @@ void plic::global_int_port_cb() {
if (enable && global_interrupts_i[i].read() == 1) {
regs->r_pending = regs->r_pending | (0x1 << i);
SCDEBUG("plic") << "pending interrupt identified: " << i;
SCCDEBUG("plic") << "pending interrupt identified: " << i;
}
}
@@ -147,7 +147,7 @@ void plic::handle_pending_int() {
claim_prio = prio;
claim_int = i;
raise_int = 1;
SCDEBUG("plic") << "pending interrupt activated: " << i;
SCCDEBUG("plic") << "pending interrupt activated: " << i;
}
}
}
@@ -158,14 +158,14 @@ void plic::handle_pending_int() {
// todo: evluate clock period
} else {
regs->r_claim_complete = 0;
SCDEBUG("plic") << "no further pending interrupt.";
SCCDEBUG("plic") << "no further pending interrupt.";
}
}
void plic::reset_pending_int(uint32_t irq) {
// todo: evaluate enable register (see spec)
// todo: make sure that pending is set, otherwise don't reset irq ... read spec.
SCDEBUG("plic") << "reset pending interrupt: " << irq;
SCCDEBUG("plic") << "reset pending interrupt: " << irq;
// reset related pending bit
regs->r_pending &= ~(0x1 << irq);
core_interrupt_o.write(0);

4
examples/simple_system/sc_main.cpp
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@@ -67,7 +67,7 @@ int sc_main(int argc, char *argv[]) {
///////////////////////////////////////////////////////////////////////////
// configure logging
///////////////////////////////////////////////////////////////////////////
scc::init_logging(vm.count("debug")?logging::DEBUG:logging::INFO);
scc::init_logging(vm.count("debug")?scc::log::DEBUG:scc::log::INFO);
///////////////////////////////////////////////////////////////////////////
// set up tracing & transaction recording
///////////////////////////////////////////////////////////////////////////
@@ -86,7 +86,7 @@ int sc_main(int argc, char *argv[]) {
// todo: provide end-of-simulation macros
if (!sc_core::sc_end_of_simulation_invoked()) {
SCERR() << "simulation timed out";
SCCERR() << "simulation timed out";
sc_core::sc_stop();
}
return SUCCESS;

10
examples/simple_system/test_initiator.cpp
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@@ -215,7 +215,7 @@ void test_initiator::write_bus(std::uint32_t adr, std::uint32_t dat) {
data[1] = 0xff & dat >> 8;
data[0] = 0xff & dat;
SCDEBUG("test_initiator") << "write_bus(0x" << std::hex << adr << ") : " << dat;
SCCDEBUG("test_initiator") << "write_bus(0x" << std::hex << adr << ") : " << dat;
gp.set_command(tlm::TLM_WRITE_COMMAND);
gp.set_address(adr);
@@ -252,21 +252,21 @@ std::uint32_t test_initiator::read_bus(std::uint32_t adr) {
// todo: use reinterpret_cast instead
std::uint32_t rdat = data[3] << 24 | data[2] << 16 | data[1] << 8 | data[0];
SCDEBUG("test_initiator") << "read_bus(0x" << std::hex << adr << ") -> " << rdat;
SCCDEBUG("test_initiator") << "read_bus(0x" << std::hex << adr << ") -> " << rdat;
return rdat;
}
void test_initiator::reg_check(std::uint32_t adr, std::uint32_t exp) {
uint32_t dat = read_bus(adr);
if (dat != exp) {
SCERR("test_initiator") << "register check failed for address 0x" << std::hex << adr << ": " << dat << " != " << exp;
SCCERR("test_initiator") << "register check failed for address 0x" << std::hex << adr << ": " << dat << " != " << exp;
} else {
SCDEBUG("test_initiator") << "register check passed for address 0x" << std::hex << adr << ": " << dat;
SCCDEBUG("test_initiator") << "register check passed for address 0x" << std::hex << adr << ": " << dat;
}
}
void test_initiator::core_irq_handler() {
SCDEBUG("test_initiator") << "core_interrupt_i edge detected -> " << core_interrupt_i.read();
SCCDEBUG("test_initiator") << "core_interrupt_i edge detected -> " << core_interrupt_i.read();
}
} /* namespace sysc */